utility.hh revision 6019
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 36019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 46019Shines@cs.fsu.edu * All rights reserved. 56019Shines@cs.fsu.edu * 66019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 76019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 86019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 96019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 106019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 116019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 126019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 136019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 146019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu * this software without specific prior written permission. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * Authors: Korey Sewell 306019Shines@cs.fsu.edu * Stephen Hines 316019Shines@cs.fsu.edu */ 326019Shines@cs.fsu.edu 336019Shines@cs.fsu.edu#ifndef __ARCH_ARM_UTILITY_HH__ 346019Shines@cs.fsu.edu#define __ARCH_ARM_UTILITY_HH__ 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.edu#include "arch/arm/types.hh" 376019Shines@cs.fsu.edu#include "base/misc.hh" 386019Shines@cs.fsu.edu#include "config/full_system.hh" 396019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 406019Shines@cs.fsu.edu#include "sim/host.hh" 416019Shines@cs.fsu.edu 426019Shines@cs.fsu.educlass ThreadContext; 436019Shines@cs.fsu.edu 446019Shines@cs.fsu.edunamespace ArmISA { 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu //Floating Point Utility Functions 476019Shines@cs.fsu.edu uint64_t fpConvert(ConvertType cvt_type, double fp_val); 486019Shines@cs.fsu.edu double roundFP(double val, int digits); 496019Shines@cs.fsu.edu double truncFP(double val); 506019Shines@cs.fsu.edu 516019Shines@cs.fsu.edu bool getCondCode(uint32_t fcsr, int cc); 526019Shines@cs.fsu.edu uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 536019Shines@cs.fsu.edu uint32_t genInvalidVector(uint32_t fcsr); 546019Shines@cs.fsu.edu 556019Shines@cs.fsu.edu bool isNan(void *val_ptr, int size); 566019Shines@cs.fsu.edu bool isQnan(void *val_ptr, int size); 576019Shines@cs.fsu.edu bool isSnan(void *val_ptr, int size); 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edu /** 606019Shines@cs.fsu.edu * Function to insure ISA semantics about 0 registers. 616019Shines@cs.fsu.edu * @param tc The thread context. 626019Shines@cs.fsu.edu */ 636019Shines@cs.fsu.edu template <class TC> 646019Shines@cs.fsu.edu void zeroRegisters(TC *tc); 656019Shines@cs.fsu.edu 666019Shines@cs.fsu.edu // Instruction address compression hooks 676019Shines@cs.fsu.edu static inline Addr realPCToFetchPC(const Addr &addr) { 686019Shines@cs.fsu.edu return addr; 696019Shines@cs.fsu.edu } 706019Shines@cs.fsu.edu 716019Shines@cs.fsu.edu static inline Addr fetchPCToRealPC(const Addr &addr) { 726019Shines@cs.fsu.edu return addr; 736019Shines@cs.fsu.edu } 746019Shines@cs.fsu.edu 756019Shines@cs.fsu.edu // the size of "fetched" instructions 766019Shines@cs.fsu.edu static inline size_t fetchInstSize() { 776019Shines@cs.fsu.edu return sizeof(MachInst); 786019Shines@cs.fsu.edu } 796019Shines@cs.fsu.edu 806019Shines@cs.fsu.edu static inline MachInst makeRegisterCopy(int dest, int src) { 816019Shines@cs.fsu.edu panic("makeRegisterCopy not implemented"); 826019Shines@cs.fsu.edu return 0; 836019Shines@cs.fsu.edu } 846019Shines@cs.fsu.edu 856019Shines@cs.fsu.edu inline void startupCPU(ThreadContext *tc, int cpuId) 866019Shines@cs.fsu.edu { 876019Shines@cs.fsu.edu tc->activate(0); 886019Shines@cs.fsu.edu } 896019Shines@cs.fsu.edu}; 906019Shines@cs.fsu.edu 916019Shines@cs.fsu.edu 926019Shines@cs.fsu.edu#endif 93