tarmac_tracer.hh revision 13915
112642Sgiacomo.travaglini@arm.com/* 212642Sgiacomo.travaglini@arm.com * Copyright (c) 2017-2018 ARM Limited 312642Sgiacomo.travaglini@arm.com * All rights reserved 412642Sgiacomo.travaglini@arm.com * 512642Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612642Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712642Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812642Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912642Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012642Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112642Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212642Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312642Sgiacomo.travaglini@arm.com * 1412642Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512642Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612642Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712642Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812642Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912642Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012642Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112642Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212642Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312642Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412642Sgiacomo.travaglini@arm.com * 2512642Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612642Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712642Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812642Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912642Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012642Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112642Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212642Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312642Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412642Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512642Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612642Sgiacomo.travaglini@arm.com * 3712642Sgiacomo.travaglini@arm.com * Authors: Giacomo Travaglini 3812642Sgiacomo.travaglini@arm.com */ 3912642Sgiacomo.travaglini@arm.com 4012642Sgiacomo.travaglini@arm.com/** 4112642Sgiacomo.travaglini@arm.com * @file: This file declares the interface of the Tarmac Tracer: 4212642Sgiacomo.travaglini@arm.com * the tracer based on the Tarmac specification. 4312642Sgiacomo.travaglini@arm.com */ 4412642Sgiacomo.travaglini@arm.com 4512642Sgiacomo.travaglini@arm.com#ifndef __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__ 4612642Sgiacomo.travaglini@arm.com#define __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__ 4712642Sgiacomo.travaglini@arm.com 4812642Sgiacomo.travaglini@arm.com#include "arch/arm/tracers/tarmac_record.hh" 4912642Sgiacomo.travaglini@arm.com#include "arch/arm/tracers/tarmac_record_v8.hh" 5012642Sgiacomo.travaglini@arm.com#include "params/TarmacTracer.hh" 5112642Sgiacomo.travaglini@arm.com#include "sim/insttracer.hh" 5212642Sgiacomo.travaglini@arm.com 5312642Sgiacomo.travaglini@arm.comclass ThreadContext; 5412642Sgiacomo.travaglini@arm.com 5512642Sgiacomo.travaglini@arm.comnamespace Trace { 5612642Sgiacomo.travaglini@arm.com 5712642Sgiacomo.travaglini@arm.com/** 5812642Sgiacomo.travaglini@arm.com * This object type is encapsulating the informations needed by 5912642Sgiacomo.travaglini@arm.com * a Tarmac record to generate it's own entries. 6012642Sgiacomo.travaglini@arm.com */ 6112642Sgiacomo.travaglini@arm.comclass TarmacContext 6212642Sgiacomo.travaglini@arm.com{ 6312642Sgiacomo.travaglini@arm.com public: 6412642Sgiacomo.travaglini@arm.com TarmacContext(ThreadContext* _thread, 6512642Sgiacomo.travaglini@arm.com const StaticInstPtr _staticInst, 6613915Sgabeblack@google.com ArmISA::PCState _pc) 6712642Sgiacomo.travaglini@arm.com : thread(_thread), staticInst(_staticInst), pc(_pc) 6812642Sgiacomo.travaglini@arm.com {} 6912642Sgiacomo.travaglini@arm.com 7012642Sgiacomo.travaglini@arm.com std::string tarmacCpuName() const; 7112642Sgiacomo.travaglini@arm.com 7212642Sgiacomo.travaglini@arm.com public: 7312642Sgiacomo.travaglini@arm.com ThreadContext* thread; 7412642Sgiacomo.travaglini@arm.com const StaticInstPtr staticInst; 7513915Sgabeblack@google.com ArmISA::PCState pc; 7612642Sgiacomo.travaglini@arm.com}; 7712642Sgiacomo.travaglini@arm.com 7812642Sgiacomo.travaglini@arm.com/** 7912642Sgiacomo.travaglini@arm.com * Tarmac Tracer: this tracer generates a new Tarmac Record for 8012642Sgiacomo.travaglini@arm.com * every instruction being executed in gem5. 8112642Sgiacomo.travaglini@arm.com * The record is made by a collection of entries which are stored 8212642Sgiacomo.travaglini@arm.com * in the tracer queues. 8312642Sgiacomo.travaglini@arm.com */ 8412642Sgiacomo.travaglini@arm.comclass TarmacTracer : public InstTracer 8512642Sgiacomo.travaglini@arm.com{ 8612642Sgiacomo.travaglini@arm.com friend class TarmacTracerRecord; 8712642Sgiacomo.travaglini@arm.com friend class TarmacTracerRecordV8; 8812642Sgiacomo.travaglini@arm.com 8912642Sgiacomo.travaglini@arm.com public: 9012642Sgiacomo.travaglini@arm.com typedef TarmacTracerParams Params; 9112642Sgiacomo.travaglini@arm.com 9212642Sgiacomo.travaglini@arm.com TarmacTracer(const Params *p); 9312642Sgiacomo.travaglini@arm.com 9412642Sgiacomo.travaglini@arm.com /** 9512642Sgiacomo.travaglini@arm.com * Generates a TarmacTracerRecord, depending on the Tarmac version. 9612642Sgiacomo.travaglini@arm.com * At the moment supported formats are: 9712642Sgiacomo.travaglini@arm.com * - Tarmac 9812642Sgiacomo.travaglini@arm.com * - TarmacV8 9912642Sgiacomo.travaglini@arm.com */ 10012642Sgiacomo.travaglini@arm.com InstRecord* getInstRecord(Tick when, ThreadContext *tc, 10112642Sgiacomo.travaglini@arm.com const StaticInstPtr staticInst, 10213915Sgabeblack@google.com ArmISA::PCState pc, 10312642Sgiacomo.travaglini@arm.com const StaticInstPtr macroStaticInst = NULL); 10412642Sgiacomo.travaglini@arm.com 10512642Sgiacomo.travaglini@arm.com protected: 10612642Sgiacomo.travaglini@arm.com typedef std::unique_ptr<Printable> PEntryPtr; 10712642Sgiacomo.travaglini@arm.com typedef TarmacTracerRecord::InstPtr InstPtr; 10812642Sgiacomo.travaglini@arm.com typedef TarmacTracerRecord::MemPtr MemPtr; 10912642Sgiacomo.travaglini@arm.com typedef TarmacTracerRecord::RegPtr RegPtr; 11012642Sgiacomo.travaglini@arm.com 11112642Sgiacomo.travaglini@arm.com /** 11212642Sgiacomo.travaglini@arm.com * startTick and endTick allow to trace a specific window of ticks 11312642Sgiacomo.travaglini@arm.com * rather than the entire CPU execution. 11412642Sgiacomo.travaglini@arm.com */ 11512642Sgiacomo.travaglini@arm.com Tick startTick; 11612642Sgiacomo.travaglini@arm.com Tick endTick; 11712642Sgiacomo.travaglini@arm.com 11812642Sgiacomo.travaglini@arm.com /** 11912642Sgiacomo.travaglini@arm.com * Collection of heterogeneous printable entries: could be 12012642Sgiacomo.travaglini@arm.com * representing either instructions, register or memory entries. 12112642Sgiacomo.travaglini@arm.com * When dealing with MacroInstructions the following separate queues 12212642Sgiacomo.travaglini@arm.com * will be used. micro-instruction entries will be buffered and 12312642Sgiacomo.travaglini@arm.com * dumped to the tracefile only at the end of the Macro. 12412642Sgiacomo.travaglini@arm.com */ 12512642Sgiacomo.travaglini@arm.com std::vector<InstPtr> instQueue; 12612642Sgiacomo.travaglini@arm.com std::vector<MemPtr> memQueue; 12712642Sgiacomo.travaglini@arm.com std::vector<RegPtr> regQueue; 12812642Sgiacomo.travaglini@arm.com}; 12912642Sgiacomo.travaglini@arm.com 13012642Sgiacomo.travaglini@arm.com} // namespace Trace 13112642Sgiacomo.travaglini@arm.com 13212642Sgiacomo.travaglini@arm.com#endif // __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__ 133