tlb.cc revision 10418
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2010-2013 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include <string> 466019Shines@cs.fsu.edu#include <vector> 476019Shines@cs.fsu.edu 486116Snate@binkert.org#include "arch/arm/faults.hh" 496019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 508782Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 518756Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 5210037SARM gem5 Developers#include "arch/arm/stage2_lookup.hh" 5310037SARM gem5 Developers#include "arch/arm/stage2_mmu.hh" 546019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 556019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 566019Shines@cs.fsu.edu#include "base/inifile.hh" 576019Shines@cs.fsu.edu#include "base/str.hh" 586019Shines@cs.fsu.edu#include "base/trace.hh" 5910024Sdam.sunwoo@arm.com#include "cpu/base.hh" 606019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 618232Snate@binkert.org#include "debug/Checkpoint.hh" 628232Snate@binkert.org#include "debug/TLB.hh" 638232Snate@binkert.org#include "debug/TLBVerbose.hh" 646116Snate@binkert.org#include "mem/page_table.hh" 656116Snate@binkert.org#include "params/ArmTLB.hh" 668756Sgblack@eecs.umich.edu#include "sim/full_system.hh" 676019Shines@cs.fsu.edu#include "sim/process.hh" 686019Shines@cs.fsu.edu 696019Shines@cs.fsu.eduusing namespace std; 706019Shines@cs.fsu.eduusing namespace ArmISA; 716019Shines@cs.fsu.edu 7210037SARM gem5 DevelopersTLB::TLB(const ArmTLBParams *p) 7310037SARM gem5 Developers : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), 7410418Sandreas.hansson@arm.com isStage2(p->is_stage2), stage2Req(false), _attr(0), 7510418Sandreas.hansson@arm.com directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), 7610418Sandreas.hansson@arm.com stage2Mmu(NULL), rangeMRU(1), bootUncacheability(false), 7710418Sandreas.hansson@arm.com miscRegValid(false), curTranType(NormalTran) 786019Shines@cs.fsu.edu{ 7910037SARM gem5 Developers tableWalker->setTlb(this); 807399SAli.Saidi@ARM.com 8110037SARM gem5 Developers // Cache system-level properties 8210037SARM gem5 Developers haveLPAE = tableWalker->haveLPAE(); 8310037SARM gem5 Developers haveVirtualization = tableWalker->haveVirtualization(); 8410037SARM gem5 Developers haveLargeAsid64 = tableWalker->haveLargeAsid64(); 856019Shines@cs.fsu.edu} 866019Shines@cs.fsu.edu 876019Shines@cs.fsu.eduTLB::~TLB() 886019Shines@cs.fsu.edu{ 8910037SARM gem5 Developers delete[] table; 9010037SARM gem5 Developers} 9110037SARM gem5 Developers 9210037SARM gem5 Developersvoid 9310037SARM gem5 DevelopersTLB::init() 9410037SARM gem5 Developers{ 9510037SARM gem5 Developers if (stage2Mmu && !isStage2) 9610037SARM gem5 Developers stage2Tlb = stage2Mmu->stage2Tlb(); 9710037SARM gem5 Developers} 9810037SARM gem5 Developers 9910037SARM gem5 Developersvoid 10010037SARM gem5 DevelopersTLB::setMMU(Stage2MMU *m) 10110037SARM gem5 Developers{ 10210037SARM gem5 Developers stage2Mmu = m; 10310037SARM gem5 Developers tableWalker->setMMU(m); 1046019Shines@cs.fsu.edu} 1056019Shines@cs.fsu.edu 1067694SAli.Saidi@ARM.combool 1077694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 1087694SAli.Saidi@ARM.com{ 10910037SARM gem5 Developers updateMiscReg(tc); 11010037SARM gem5 Developers 11110037SARM gem5 Developers if (directToStage2) { 11210037SARM gem5 Developers assert(stage2Tlb); 11310037SARM gem5 Developers return stage2Tlb->translateFunctional(tc, va, pa); 11410037SARM gem5 Developers } 11510037SARM gem5 Developers 11610037SARM gem5 Developers TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false, 11710037SARM gem5 Developers aarch64 ? aarch64EL : EL1); 1187694SAli.Saidi@ARM.com if (!e) 1197694SAli.Saidi@ARM.com return false; 1207694SAli.Saidi@ARM.com pa = e->pAddr(va); 1217694SAli.Saidi@ARM.com return true; 1227694SAli.Saidi@ARM.com} 1237694SAli.Saidi@ARM.com 1249738Sandreas@sandberg.pp.seFault 1259738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 1269738Sandreas@sandberg.pp.se{ 1279738Sandreas@sandberg.pp.se return NoFault; 1289738Sandreas@sandberg.pp.se} 1299738Sandreas@sandberg.pp.se 1307404SAli.Saidi@ARM.comTlbEntry* 13110037SARM gem5 DevelopersTLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, 13210037SARM gem5 Developers bool functional, bool ignore_asn, uint8_t target_el) 1336019Shines@cs.fsu.edu{ 1347404SAli.Saidi@ARM.com 1357404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1367404SAli.Saidi@ARM.com 13710037SARM gem5 Developers // Maintaining LRU array 1387404SAli.Saidi@ARM.com int x = 0; 1397404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 14010037SARM gem5 Developers if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false, 14110037SARM gem5 Developers target_el)) || 14210037SARM gem5 Developers (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) { 14310037SARM gem5 Developers // We only move the hit entry ahead when the position is higher 14410037SARM gem5 Developers // than rangeMRU 1459535Smrinmoy.ghosh@arm.com if (x > rangeMRU && !functional) { 1467697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 1477697SAli.Saidi@ARM.com for(int i = x; i > 0; i--) 14810037SARM gem5 Developers table[i] = table[i - 1]; 1497697SAli.Saidi@ARM.com table[0] = tmp_entry; 1507697SAli.Saidi@ARM.com retval = &table[0]; 1517697SAli.Saidi@ARM.com } else { 1527697SAli.Saidi@ARM.com retval = &table[x]; 1537697SAli.Saidi@ARM.com } 1547404SAli.Saidi@ARM.com break; 1557404SAli.Saidi@ARM.com } 15610037SARM gem5 Developers ++x; 1577404SAli.Saidi@ARM.com } 1587404SAli.Saidi@ARM.com 15910037SARM gem5 Developers DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d " 16010037SARM gem5 Developers "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " 16110037SARM gem5 Developers "el: %d\n", 16210037SARM gem5 Developers va, asn, retval ? "hit" : "miss", vmid, hyp, secure, 16310037SARM gem5 Developers retval ? retval->pfn : 0, retval ? retval->size : 0, 16410037SARM gem5 Developers retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0, 16510037SARM gem5 Developers retval ? retval->ns : 0, retval ? retval->nstid : 0, 16610037SARM gem5 Developers retval ? retval->global : 0, retval ? retval->asid : 0, 16710367SAndrew.Bardsley@arm.com retval ? retval->el : 0); 16810037SARM gem5 Developers 1697404SAli.Saidi@ARM.com return retval; 1706019Shines@cs.fsu.edu} 1716019Shines@cs.fsu.edu 1726019Shines@cs.fsu.edu// insert a new TLB entry 1736019Shines@cs.fsu.eduvoid 1747404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1756019Shines@cs.fsu.edu{ 1767404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 17710037SARM gem5 Developers " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" 17810037SARM gem5 Developers " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn, 17910037SARM gem5 Developers entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, 18010037SARM gem5 Developers entry.global, entry.valid, entry.nonCacheable, entry.xn, 18110037SARM gem5 Developers entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid, 18210037SARM gem5 Developers entry.isHyp); 1837404SAli.Saidi@ARM.com 18410037SARM gem5 Developers if (table[size - 1].valid) 18510037SARM gem5 Developers DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x " 18610037SARM gem5 Developers "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n", 1877697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 18810037SARM gem5 Developers table[size-1].vmid, table[size-1].pfn << table[size-1].N, 18910037SARM gem5 Developers table[size-1].size, table[size-1].ap, table[size-1].ns, 19010037SARM gem5 Developers table[size-1].nstid, table[size-1].global, table[size-1].isHyp, 19110037SARM gem5 Developers table[size-1].el); 1927404SAli.Saidi@ARM.com 1937697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1947404SAli.Saidi@ARM.com 19510037SARM gem5 Developers for (int i = size - 1; i > 0; --i) 19610037SARM gem5 Developers table[i] = table[i-1]; 1977697SAli.Saidi@ARM.com table[0] = entry; 1987734SAli.Saidi@ARM.com 1997734SAli.Saidi@ARM.com inserts++; 2006019Shines@cs.fsu.edu} 2016019Shines@cs.fsu.edu 2026019Shines@cs.fsu.eduvoid 20310037SARM gem5 DevelopersTLB::printTlb() const 2047404SAli.Saidi@ARM.com{ 2057404SAli.Saidi@ARM.com int x = 0; 2067404SAli.Saidi@ARM.com TlbEntry *te; 2077404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 2087404SAli.Saidi@ARM.com while (x < size) { 20910037SARM gem5 Developers te = &table[x]; 21010037SARM gem5 Developers if (te->valid) 21110037SARM gem5 Developers DPRINTF(TLB, " * %s\n", te->print()); 21210037SARM gem5 Developers ++x; 2137404SAli.Saidi@ARM.com } 2147404SAli.Saidi@ARM.com} 2157404SAli.Saidi@ARM.com 2167404SAli.Saidi@ARM.comvoid 21710037SARM gem5 DevelopersTLB::flushAllSecurity(bool secure_lookup, uint8_t target_el, bool ignore_el) 2186019Shines@cs.fsu.edu{ 21910037SARM gem5 Developers DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n", 22010037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 2217404SAli.Saidi@ARM.com int x = 0; 2227404SAli.Saidi@ARM.com TlbEntry *te; 2237404SAli.Saidi@ARM.com while (x < size) { 22410037SARM gem5 Developers te = &table[x]; 22510037SARM gem5 Developers if (te->valid && secure_lookup == !te->nstid && 22610037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 22710037SARM gem5 Developers checkELMatch(target_el, te->el, ignore_el)) { 22810037SARM gem5 Developers 22910037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 23010037SARM gem5 Developers te->valid = false; 23110037SARM gem5 Developers flushedEntries++; 23210037SARM gem5 Developers } 23310037SARM gem5 Developers ++x; 2347404SAli.Saidi@ARM.com } 2357404SAli.Saidi@ARM.com 23610037SARM gem5 Developers flushTlb++; 23710037SARM gem5 Developers 23810037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 23910037SARM gem5 Developers // if we're currently in hyp mode 24010037SARM gem5 Developers if (!isStage2 && isHyp) { 24110037SARM gem5 Developers stage2Tlb->flushAllSecurity(secure_lookup, true); 24210037SARM gem5 Developers } 24310037SARM gem5 Developers} 24410037SARM gem5 Developers 24510037SARM gem5 Developersvoid 24610037SARM gem5 DevelopersTLB::flushAllNs(bool hyp, uint8_t target_el, bool ignore_el) 24710037SARM gem5 Developers{ 24810037SARM gem5 Developers DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n", 24910037SARM gem5 Developers (hyp ? "hyp" : "non-hyp")); 25010037SARM gem5 Developers int x = 0; 25110037SARM gem5 Developers TlbEntry *te; 25210037SARM gem5 Developers while (x < size) { 25310037SARM gem5 Developers te = &table[x]; 25410037SARM gem5 Developers if (te->valid && te->nstid && te->isHyp == hyp && 25510037SARM gem5 Developers checkELMatch(target_el, te->el, ignore_el)) { 25610037SARM gem5 Developers 25710037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 25810037SARM gem5 Developers flushedEntries++; 25910037SARM gem5 Developers te->valid = false; 26010037SARM gem5 Developers } 26110037SARM gem5 Developers ++x; 26210037SARM gem5 Developers } 2637734SAli.Saidi@ARM.com 2647734SAli.Saidi@ARM.com flushTlb++; 26510037SARM gem5 Developers 26610037SARM gem5 Developers // If there's a second stage TLB (and we're not it) then flush it as well 26710037SARM gem5 Developers if (!isStage2 && !hyp) { 26810037SARM gem5 Developers stage2Tlb->flushAllNs(false, true); 26910037SARM gem5 Developers } 2706019Shines@cs.fsu.edu} 2716019Shines@cs.fsu.edu 2727404SAli.Saidi@ARM.comvoid 27310037SARM gem5 DevelopersTLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el) 2747404SAli.Saidi@ARM.com{ 27510037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x " 27610037SARM gem5 Developers "(%s lookup)\n", mva, asn, (secure_lookup ? 27710037SARM gem5 Developers "secure" : "non-secure")); 27810037SARM gem5 Developers _flushMva(mva, asn, secure_lookup, false, false, target_el); 2797734SAli.Saidi@ARM.com flushTlbMvaAsid++; 2807404SAli.Saidi@ARM.com} 2817404SAli.Saidi@ARM.com 2827404SAli.Saidi@ARM.comvoid 28310037SARM gem5 DevelopersTLB::flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el) 2847404SAli.Saidi@ARM.com{ 28510037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn, 28610037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 2877404SAli.Saidi@ARM.com 28810037SARM gem5 Developers int x = 0 ; 2897404SAli.Saidi@ARM.com TlbEntry *te; 2907404SAli.Saidi@ARM.com 2917404SAli.Saidi@ARM.com while (x < size) { 2927404SAli.Saidi@ARM.com te = &table[x]; 29310037SARM gem5 Developers if (te->valid && te->asid == asn && secure_lookup == !te->nstid && 29410037SARM gem5 Developers (te->vmid == vmid || secure_lookup) && 29510037SARM gem5 Developers checkELMatch(target_el, te->el, false)) { 29610037SARM gem5 Developers 2977404SAli.Saidi@ARM.com te->valid = false; 29810037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 2997734SAli.Saidi@ARM.com flushedEntries++; 3007404SAli.Saidi@ARM.com } 30110037SARM gem5 Developers ++x; 3027404SAli.Saidi@ARM.com } 3037734SAli.Saidi@ARM.com flushTlbAsid++; 3047404SAli.Saidi@ARM.com} 3057404SAli.Saidi@ARM.com 3067404SAli.Saidi@ARM.comvoid 30710037SARM gem5 DevelopersTLB::flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el) 3087404SAli.Saidi@ARM.com{ 30910037SARM gem5 Developers DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva, 31010037SARM gem5 Developers (secure_lookup ? "secure" : "non-secure")); 31110037SARM gem5 Developers _flushMva(mva, 0xbeef, secure_lookup, hyp, true, target_el); 31210037SARM gem5 Developers flushTlbMva++; 31310037SARM gem5 Developers} 3147404SAli.Saidi@ARM.com 31510037SARM gem5 Developersvoid 31610037SARM gem5 DevelopersTLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp, 31710037SARM gem5 Developers bool ignore_asn, uint8_t target_el) 31810037SARM gem5 Developers{ 3197404SAli.Saidi@ARM.com TlbEntry *te; 32010037SARM gem5 Developers // D5.7.2: Sign-extend address to 64 bits 32110037SARM gem5 Developers mva = sext<56>(mva); 32210037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 32310037SARM gem5 Developers target_el); 32410037SARM gem5 Developers while (te != NULL) { 32510037SARM gem5 Developers if (secure_lookup == !te->nstid) { 32610037SARM gem5 Developers DPRINTF(TLB, " - %s\n", te->print()); 3277404SAli.Saidi@ARM.com te->valid = false; 3287734SAli.Saidi@ARM.com flushedEntries++; 3297404SAli.Saidi@ARM.com } 33010037SARM gem5 Developers te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 33110037SARM gem5 Developers target_el); 3327404SAli.Saidi@ARM.com } 33310037SARM gem5 Developers} 33410037SARM gem5 Developers 33510037SARM gem5 Developersbool 33610037SARM gem5 DevelopersTLB::checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el) 33710037SARM gem5 Developers{ 33810037SARM gem5 Developers bool elMatch = true; 33910037SARM gem5 Developers if (!ignore_el) { 34010037SARM gem5 Developers if (target_el == 2 || target_el == 3) { 34110037SARM gem5 Developers elMatch = (tentry_el == target_el); 34210037SARM gem5 Developers } else { 34310037SARM gem5 Developers elMatch = (tentry_el == 0) || (tentry_el == 1); 34410037SARM gem5 Developers } 34510037SARM gem5 Developers } 34610037SARM gem5 Developers return elMatch; 3477404SAli.Saidi@ARM.com} 3487404SAli.Saidi@ARM.com 3496019Shines@cs.fsu.eduvoid 3509439SAndreas.Sandberg@ARM.comTLB::drainResume() 3519439SAndreas.Sandberg@ARM.com{ 3529439SAndreas.Sandberg@ARM.com // We might have unserialized something or switched CPUs, so make 3539439SAndreas.Sandberg@ARM.com // sure to re-read the misc regs. 3549439SAndreas.Sandberg@ARM.com miscRegValid = false; 3559439SAndreas.Sandberg@ARM.com} 3569439SAndreas.Sandberg@ARM.com 3579439SAndreas.Sandberg@ARM.comvoid 35810194SGeoffrey.Blake@arm.comTLB::takeOverFrom(BaseTLB *_otlb) 35910194SGeoffrey.Blake@arm.com{ 36010194SGeoffrey.Blake@arm.com TLB *otlb = dynamic_cast<TLB*>(_otlb); 36110194SGeoffrey.Blake@arm.com /* Make sure we actually have a valid type */ 36210194SGeoffrey.Blake@arm.com if (otlb) { 36310194SGeoffrey.Blake@arm.com _attr = otlb->_attr; 36410194SGeoffrey.Blake@arm.com haveLPAE = otlb->haveLPAE; 36510194SGeoffrey.Blake@arm.com directToStage2 = otlb->directToStage2; 36610194SGeoffrey.Blake@arm.com stage2Req = otlb->stage2Req; 36710194SGeoffrey.Blake@arm.com bootUncacheability = otlb->bootUncacheability; 36810194SGeoffrey.Blake@arm.com 36910194SGeoffrey.Blake@arm.com /* Sync the stage2 MMU if they exist in both 37010194SGeoffrey.Blake@arm.com * the old CPU and the new 37110194SGeoffrey.Blake@arm.com */ 37210194SGeoffrey.Blake@arm.com if (!isStage2 && 37310194SGeoffrey.Blake@arm.com stage2Tlb && otlb->stage2Tlb) { 37410194SGeoffrey.Blake@arm.com stage2Tlb->takeOverFrom(otlb->stage2Tlb); 37510194SGeoffrey.Blake@arm.com } 37610194SGeoffrey.Blake@arm.com } else { 37710194SGeoffrey.Blake@arm.com panic("Incompatible TLB type!"); 37810194SGeoffrey.Blake@arm.com } 37910194SGeoffrey.Blake@arm.com} 38010194SGeoffrey.Blake@arm.com 38110194SGeoffrey.Blake@arm.comvoid 3826019Shines@cs.fsu.eduTLB::serialize(ostream &os) 3836019Shines@cs.fsu.edu{ 3847733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 3857733SAli.Saidi@ARM.com 3867733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 38710037SARM gem5 Developers SERIALIZE_SCALAR(haveLPAE); 38810037SARM gem5 Developers SERIALIZE_SCALAR(directToStage2); 38910037SARM gem5 Developers SERIALIZE_SCALAR(stage2Req); 39010037SARM gem5 Developers SERIALIZE_SCALAR(bootUncacheability); 3918353SAli.Saidi@ARM.com 3928353SAli.Saidi@ARM.com int num_entries = size; 3938353SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 3947733SAli.Saidi@ARM.com for(int i = 0; i < size; i++){ 3957733SAli.Saidi@ARM.com nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 3967733SAli.Saidi@ARM.com table[i].serialize(os); 3977733SAli.Saidi@ARM.com } 3986019Shines@cs.fsu.edu} 3996019Shines@cs.fsu.edu 4006019Shines@cs.fsu.eduvoid 4016019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 4026019Shines@cs.fsu.edu{ 4037733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 4046019Shines@cs.fsu.edu 4057733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 40610037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLPAE); 40710037SARM gem5 Developers UNSERIALIZE_SCALAR(directToStage2); 40810037SARM gem5 Developers UNSERIALIZE_SCALAR(stage2Req); 40910037SARM gem5 Developers UNSERIALIZE_SCALAR(bootUncacheability); 41010037SARM gem5 Developers 4118353SAli.Saidi@ARM.com int num_entries; 4128353SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(num_entries); 4138353SAli.Saidi@ARM.com for(int i = 0; i < min(size, num_entries); i++){ 4147733SAli.Saidi@ARM.com table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 4157733SAli.Saidi@ARM.com } 4166019Shines@cs.fsu.edu} 4176019Shines@cs.fsu.edu 4186019Shines@cs.fsu.eduvoid 4196019Shines@cs.fsu.eduTLB::regStats() 4206019Shines@cs.fsu.edu{ 4217734SAli.Saidi@ARM.com instHits 4227734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 4237734SAli.Saidi@ARM.com .desc("ITB inst hits") 4247734SAli.Saidi@ARM.com ; 4257734SAli.Saidi@ARM.com 4267734SAli.Saidi@ARM.com instMisses 4277734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 4287734SAli.Saidi@ARM.com .desc("ITB inst misses") 4297734SAli.Saidi@ARM.com ; 4307734SAli.Saidi@ARM.com 4317734SAli.Saidi@ARM.com instAccesses 4327734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 4337734SAli.Saidi@ARM.com .desc("ITB inst accesses") 4347734SAli.Saidi@ARM.com ; 4357734SAli.Saidi@ARM.com 4367734SAli.Saidi@ARM.com readHits 4376019Shines@cs.fsu.edu .name(name() + ".read_hits") 4386019Shines@cs.fsu.edu .desc("DTB read hits") 4396019Shines@cs.fsu.edu ; 4406019Shines@cs.fsu.edu 4417734SAli.Saidi@ARM.com readMisses 4426019Shines@cs.fsu.edu .name(name() + ".read_misses") 4436019Shines@cs.fsu.edu .desc("DTB read misses") 4446019Shines@cs.fsu.edu ; 4456019Shines@cs.fsu.edu 4467734SAli.Saidi@ARM.com readAccesses 4476019Shines@cs.fsu.edu .name(name() + ".read_accesses") 4486019Shines@cs.fsu.edu .desc("DTB read accesses") 4496019Shines@cs.fsu.edu ; 4506019Shines@cs.fsu.edu 4517734SAli.Saidi@ARM.com writeHits 4526019Shines@cs.fsu.edu .name(name() + ".write_hits") 4536019Shines@cs.fsu.edu .desc("DTB write hits") 4546019Shines@cs.fsu.edu ; 4556019Shines@cs.fsu.edu 4567734SAli.Saidi@ARM.com writeMisses 4576019Shines@cs.fsu.edu .name(name() + ".write_misses") 4586019Shines@cs.fsu.edu .desc("DTB write misses") 4596019Shines@cs.fsu.edu ; 4606019Shines@cs.fsu.edu 4617734SAli.Saidi@ARM.com writeAccesses 4626019Shines@cs.fsu.edu .name(name() + ".write_accesses") 4636019Shines@cs.fsu.edu .desc("DTB write accesses") 4646019Shines@cs.fsu.edu ; 4656019Shines@cs.fsu.edu 4666019Shines@cs.fsu.edu hits 4676019Shines@cs.fsu.edu .name(name() + ".hits") 4686019Shines@cs.fsu.edu .desc("DTB hits") 4696019Shines@cs.fsu.edu ; 4706019Shines@cs.fsu.edu 4716019Shines@cs.fsu.edu misses 4726019Shines@cs.fsu.edu .name(name() + ".misses") 4736019Shines@cs.fsu.edu .desc("DTB misses") 4746019Shines@cs.fsu.edu ; 4756019Shines@cs.fsu.edu 4766019Shines@cs.fsu.edu accesses 4776019Shines@cs.fsu.edu .name(name() + ".accesses") 4786019Shines@cs.fsu.edu .desc("DTB accesses") 4796019Shines@cs.fsu.edu ; 4806019Shines@cs.fsu.edu 4817734SAli.Saidi@ARM.com flushTlb 4827734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 4837734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 4847734SAli.Saidi@ARM.com ; 4857734SAli.Saidi@ARM.com 4867734SAli.Saidi@ARM.com flushTlbMva 4877734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 4887734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 4897734SAli.Saidi@ARM.com ; 4907734SAli.Saidi@ARM.com 4917734SAli.Saidi@ARM.com flushTlbMvaAsid 4927734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 4937734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 4947734SAli.Saidi@ARM.com ; 4957734SAli.Saidi@ARM.com 4967734SAli.Saidi@ARM.com flushTlbAsid 4977734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 4987734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 4997734SAli.Saidi@ARM.com ; 5007734SAli.Saidi@ARM.com 5017734SAli.Saidi@ARM.com flushedEntries 5027734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 5037734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 5047734SAli.Saidi@ARM.com ; 5057734SAli.Saidi@ARM.com 5067734SAli.Saidi@ARM.com alignFaults 5077734SAli.Saidi@ARM.com .name(name() + ".align_faults") 5087734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 5097734SAli.Saidi@ARM.com ; 5107734SAli.Saidi@ARM.com 5117734SAli.Saidi@ARM.com prefetchFaults 5127734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 5137734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 5147734SAli.Saidi@ARM.com ; 5157734SAli.Saidi@ARM.com 5167734SAli.Saidi@ARM.com domainFaults 5177734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 5187734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 5197734SAli.Saidi@ARM.com ; 5207734SAli.Saidi@ARM.com 5217734SAli.Saidi@ARM.com permsFaults 5227734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 5237734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 5247734SAli.Saidi@ARM.com ; 5257734SAli.Saidi@ARM.com 5267734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 5277734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 5287734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 5297734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 5307734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 5317734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 5326019Shines@cs.fsu.edu} 5336019Shines@cs.fsu.edu 5347404SAli.Saidi@ARM.comFault 5357404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 53610037SARM gem5 Developers Translation *translation, bool &delay, bool timing) 5377404SAli.Saidi@ARM.com{ 53810037SARM gem5 Developers updateMiscReg(tc); 53910037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 54010037SARM gem5 Developers Addr vaddr = 0; 54110037SARM gem5 Developers if (aarch64) 54210037SARM gem5 Developers vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 54310037SARM gem5 Developers else 54410037SARM gem5 Developers vaddr = vaddr_tainted; 5457294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 5467294Sgblack@eecs.umich.edu 5477404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 5487404SAli.Saidi@ARM.com bool is_write = (mode == Write); 5497404SAli.Saidi@ARM.com 5507404SAli.Saidi@ARM.com if (!is_fetch) { 5517294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 5527404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 55310037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 55410037SARM gem5 Developers // LPAE is always disabled in SE mode 55510037SARM gem5 Developers return new DataAbort(vaddr_tainted, 55610037SARM gem5 Developers TlbEntry::DomainType::NoAccess, is_write, 55710037SARM gem5 Developers ArmFault::AlignmentFault, isStage2, 55810037SARM gem5 Developers ArmFault::VmsaTran); 5597294Sgblack@eecs.umich.edu } 5607294Sgblack@eecs.umich.edu } 5617294Sgblack@eecs.umich.edu } 5626019Shines@cs.fsu.edu 5637093Sgblack@eecs.umich.edu Addr paddr; 5647404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 5657404SAli.Saidi@ARM.com 5667093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 56710037SARM gem5 Developers return Fault(new GenericPageTableFault(vaddr_tainted)); 5687093Sgblack@eecs.umich.edu req->setPaddr(paddr); 5696019Shines@cs.fsu.edu 5706019Shines@cs.fsu.edu return NoFault; 5717404SAli.Saidi@ARM.com} 5727404SAli.Saidi@ARM.com 5737404SAli.Saidi@ARM.comFault 57410037SARM gem5 DevelopersTLB::trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain) 5757406SAli.Saidi@ARM.com{ 5767406SAli.Saidi@ARM.com return NoFault; 5777406SAli.Saidi@ARM.com} 5787406SAli.Saidi@ARM.com 5797406SAli.Saidi@ARM.comFault 58010037SARM gem5 DevelopersTLB::walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 58110037SARM gem5 Developers bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level) 5827406SAli.Saidi@ARM.com{ 5837406SAli.Saidi@ARM.com return NoFault; 5847406SAli.Saidi@ARM.com} 5857406SAli.Saidi@ARM.com 5867406SAli.Saidi@ARM.comFault 58710037SARM gem5 DevelopersTLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 58810037SARM gem5 Developers{ 58910037SARM gem5 Developers Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 59010037SARM gem5 Developers uint32_t flags = req->getFlags(); 59110037SARM gem5 Developers bool is_fetch = (mode == Execute); 59210037SARM gem5 Developers bool is_write = (mode == Write); 59310037SARM gem5 Developers bool is_priv = isPriv && !(flags & UserMode); 59410037SARM gem5 Developers 59510037SARM gem5 Developers // Get the translation type from the actuall table entry 59610037SARM gem5 Developers ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran 59710037SARM gem5 Developers : ArmFault::VmsaTran; 59810037SARM gem5 Developers 59910037SARM gem5 Developers // If this is the second stage of translation and the request is for a 60010037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 60110037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 60210037SARM gem5 Developers // as a device or strongly ordered. 60310037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 60410037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 60510037SARM gem5 Developers return new DataAbort(vaddr, te->domain, is_write, 60610037SARM gem5 Developers ArmFault::PermissionLL + te->lookupLevel, 60710037SARM gem5 Developers isStage2, tranMethod); 60810037SARM gem5 Developers } 60910037SARM gem5 Developers 61010037SARM gem5 Developers // Generate an alignment fault for unaligned data accesses to device or 61110037SARM gem5 Developers // strongly ordered memory 61210037SARM gem5 Developers if (!is_fetch) { 61310037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 61410037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 61510037SARM gem5 Developers alignFaults++; 61610037SARM gem5 Developers return new DataAbort(vaddr, TlbEntry::DomainType::NoAccess, is_write, 61710037SARM gem5 Developers ArmFault::AlignmentFault, isStage2, 61810037SARM gem5 Developers tranMethod); 61910037SARM gem5 Developers } 62010037SARM gem5 Developers } 62110037SARM gem5 Developers } 62210037SARM gem5 Developers 62310037SARM gem5 Developers if (te->nonCacheable) { 62410037SARM gem5 Developers // Prevent prefetching from I/O devices. 62510037SARM gem5 Developers if (req->isPrefetch()) { 62610037SARM gem5 Developers // Here we can safely use the fault status for the short 62710037SARM gem5 Developers // desc. format in all cases 62810037SARM gem5 Developers return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable, 62910037SARM gem5 Developers isStage2, tranMethod); 63010037SARM gem5 Developers } 63110037SARM gem5 Developers } 63210037SARM gem5 Developers 63310037SARM gem5 Developers if (!te->longDescFormat) { 63410037SARM gem5 Developers switch ((dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) { 63510037SARM gem5 Developers case 0: 63610037SARM gem5 Developers domainFaults++; 63710037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x" 63810037SARM gem5 Developers " domain: %#x write:%d\n", dacr, 63910037SARM gem5 Developers static_cast<uint8_t>(te->domain), is_write); 64010037SARM gem5 Developers if (is_fetch) 64110037SARM gem5 Developers return new PrefetchAbort(vaddr, 64210037SARM gem5 Developers ArmFault::DomainLL + te->lookupLevel, 64310037SARM gem5 Developers isStage2, tranMethod); 64410037SARM gem5 Developers else 64510037SARM gem5 Developers return new DataAbort(vaddr, te->domain, is_write, 64610037SARM gem5 Developers ArmFault::DomainLL + te->lookupLevel, 64710037SARM gem5 Developers isStage2, tranMethod); 64810037SARM gem5 Developers case 1: 64910037SARM gem5 Developers // Continue with permissions check 65010037SARM gem5 Developers break; 65110037SARM gem5 Developers case 2: 65210037SARM gem5 Developers panic("UNPRED domain\n"); 65310037SARM gem5 Developers case 3: 65410037SARM gem5 Developers return NoFault; 65510037SARM gem5 Developers } 65610037SARM gem5 Developers } 65710037SARM gem5 Developers 65810037SARM gem5 Developers // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits 65910037SARM gem5 Developers uint8_t ap = te->longDescFormat ? te->ap << 1 : te->ap; 66010037SARM gem5 Developers uint8_t hap = te->hap; 66110037SARM gem5 Developers 66210037SARM gem5 Developers if (sctlr.afe == 1 || te->longDescFormat) 66310037SARM gem5 Developers ap |= 1; 66410037SARM gem5 Developers 66510037SARM gem5 Developers bool abt; 66610037SARM gem5 Developers bool isWritable = true; 66710037SARM gem5 Developers // If this is a stage 2 access (eg for reading stage 1 page table entries) 66810037SARM gem5 Developers // then don't perform the AP permissions check, we stil do the HAP check 66910037SARM gem5 Developers // below. 67010037SARM gem5 Developers if (isStage2) { 67110037SARM gem5 Developers abt = false; 67210037SARM gem5 Developers } else { 67310037SARM gem5 Developers switch (ap) { 67410037SARM gem5 Developers case 0: 67510037SARM gem5 Developers DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", 67610037SARM gem5 Developers (int)sctlr.rs); 67710037SARM gem5 Developers if (!sctlr.xp) { 67810037SARM gem5 Developers switch ((int)sctlr.rs) { 67910037SARM gem5 Developers case 2: 68010037SARM gem5 Developers abt = is_write; 68110037SARM gem5 Developers break; 68210037SARM gem5 Developers case 1: 68310037SARM gem5 Developers abt = is_write || !is_priv; 68410037SARM gem5 Developers break; 68510037SARM gem5 Developers case 0: 68610037SARM gem5 Developers case 3: 68710037SARM gem5 Developers default: 68810037SARM gem5 Developers abt = true; 68910037SARM gem5 Developers break; 69010037SARM gem5 Developers } 69110037SARM gem5 Developers } else { 69210037SARM gem5 Developers abt = true; 69310037SARM gem5 Developers } 69410037SARM gem5 Developers break; 69510037SARM gem5 Developers case 1: 69610037SARM gem5 Developers abt = !is_priv; 69710037SARM gem5 Developers break; 69810037SARM gem5 Developers case 2: 69910037SARM gem5 Developers abt = !is_priv && is_write; 70010037SARM gem5 Developers isWritable = is_priv; 70110037SARM gem5 Developers break; 70210037SARM gem5 Developers case 3: 70310037SARM gem5 Developers abt = false; 70410037SARM gem5 Developers break; 70510037SARM gem5 Developers case 4: 70610037SARM gem5 Developers panic("UNPRED premissions\n"); 70710037SARM gem5 Developers case 5: 70810037SARM gem5 Developers abt = !is_priv || is_write; 70910037SARM gem5 Developers isWritable = false; 71010037SARM gem5 Developers break; 71110037SARM gem5 Developers case 6: 71210037SARM gem5 Developers case 7: 71310037SARM gem5 Developers abt = is_write; 71410037SARM gem5 Developers isWritable = false; 71510037SARM gem5 Developers break; 71610037SARM gem5 Developers default: 71710037SARM gem5 Developers panic("Unknown permissions %#x\n", ap); 71810037SARM gem5 Developers } 71910037SARM gem5 Developers } 72010037SARM gem5 Developers 72110037SARM gem5 Developers bool hapAbt = is_write ? !(hap & 2) : !(hap & 1); 72210037SARM gem5 Developers bool xn = te->xn || (isWritable && sctlr.wxn) || 72310037SARM gem5 Developers (ap == 3 && sctlr.uwxn && is_priv); 72410037SARM gem5 Developers if (is_fetch && (abt || xn || 72510037SARM gem5 Developers (te->longDescFormat && te->pxn && !is_priv) || 72610037SARM gem5 Developers (isSecure && te->ns && scr.sif))) { 72710037SARM gem5 Developers permsFaults++; 72810037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " 72910037SARM gem5 Developers "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n", 73010037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe); 73110037SARM gem5 Developers return new PrefetchAbort(vaddr, 73210037SARM gem5 Developers ArmFault::PermissionLL + te->lookupLevel, 73310037SARM gem5 Developers isStage2, tranMethod); 73410037SARM gem5 Developers } else if (abt | hapAbt) { 73510037SARM gem5 Developers permsFaults++; 73610037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 73710037SARM gem5 Developers " write:%d\n", ap, is_priv, is_write); 73810037SARM gem5 Developers return new DataAbort(vaddr, te->domain, is_write, 73910037SARM gem5 Developers ArmFault::PermissionLL + te->lookupLevel, 74010037SARM gem5 Developers isStage2 | !abt, tranMethod); 74110037SARM gem5 Developers } 74210037SARM gem5 Developers return NoFault; 74310037SARM gem5 Developers} 74410037SARM gem5 Developers 74510037SARM gem5 Developers 74610037SARM gem5 DevelopersFault 74710037SARM gem5 DevelopersTLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 74810037SARM gem5 Developers ThreadContext *tc) 74910037SARM gem5 Developers{ 75010037SARM gem5 Developers assert(aarch64); 75110037SARM gem5 Developers 75210037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 75310037SARM gem5 Developers Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 75410037SARM gem5 Developers 75510037SARM gem5 Developers uint32_t flags = req->getFlags(); 75610037SARM gem5 Developers bool is_fetch = (mode == Execute); 75710037SARM gem5 Developers bool is_write = (mode == Write); 75810037SARM gem5 Developers bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 75910037SARM gem5 Developers 76010037SARM gem5 Developers updateMiscReg(tc, curTranType); 76110037SARM gem5 Developers 76210037SARM gem5 Developers // If this is the second stage of translation and the request is for a 76310037SARM gem5 Developers // stage 1 page table walk then we need to check the HCR.PTW bit. This 76410037SARM gem5 Developers // allows us to generate a fault if the request targets an area marked 76510037SARM gem5 Developers // as a device or strongly ordered. 76610037SARM gem5 Developers if (isStage2 && req->isPTWalk() && hcr.ptw && 76710037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 76810037SARM gem5 Developers return new DataAbort(vaddr_tainted, te->domain, is_write, 76910037SARM gem5 Developers ArmFault::PermissionLL + te->lookupLevel, 77010037SARM gem5 Developers isStage2, ArmFault::LpaeTran); 77110037SARM gem5 Developers } 77210037SARM gem5 Developers 77310037SARM gem5 Developers // Generate an alignment fault for unaligned accesses to device or 77410037SARM gem5 Developers // strongly ordered memory 77510037SARM gem5 Developers if (!is_fetch) { 77610037SARM gem5 Developers if (te->mtype != TlbEntry::MemoryType::Normal) { 77710037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 77810037SARM gem5 Developers alignFaults++; 77910037SARM gem5 Developers return new DataAbort(vaddr_tainted, 78010037SARM gem5 Developers TlbEntry::DomainType::NoAccess, is_write, 78110037SARM gem5 Developers ArmFault::AlignmentFault, isStage2, 78210037SARM gem5 Developers ArmFault::LpaeTran); 78310037SARM gem5 Developers } 78410037SARM gem5 Developers } 78510037SARM gem5 Developers } 78610037SARM gem5 Developers 78710037SARM gem5 Developers if (te->nonCacheable) { 78810037SARM gem5 Developers // Prevent prefetching from I/O devices. 78910037SARM gem5 Developers if (req->isPrefetch()) { 79010037SARM gem5 Developers // Here we can safely use the fault status for the short 79110037SARM gem5 Developers // desc. format in all cases 79210037SARM gem5 Developers return new PrefetchAbort(vaddr_tainted, 79310037SARM gem5 Developers ArmFault::PrefetchUncacheable, 79410037SARM gem5 Developers isStage2, ArmFault::LpaeTran); 79510037SARM gem5 Developers } 79610037SARM gem5 Developers } 79710037SARM gem5 Developers 79810037SARM gem5 Developers uint8_t ap = 0x3 & (te->ap); // 2-bit access protection field 79910037SARM gem5 Developers bool grant = false; 80010037SARM gem5 Developers 80110037SARM gem5 Developers uint8_t xn = te->xn; 80210037SARM gem5 Developers uint8_t pxn = te->pxn; 80310037SARM gem5 Developers bool r = !is_write && !is_fetch; 80410037SARM gem5 Developers bool w = is_write; 80510037SARM gem5 Developers bool x = is_fetch; 80610037SARM gem5 Developers DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 80710037SARM gem5 Developers "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 80810037SARM gem5 Developers 80910037SARM gem5 Developers if (isStage2) { 81010037SARM gem5 Developers panic("Virtualization in AArch64 state is not supported yet"); 81110037SARM gem5 Developers } else { 81210037SARM gem5 Developers switch (aarch64EL) { 81310037SARM gem5 Developers case EL0: 81410037SARM gem5 Developers { 81510037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 81610037SARM gem5 Developers switch (perm) { 81710037SARM gem5 Developers case 0: 81810037SARM gem5 Developers case 1: 81910037SARM gem5 Developers case 8: 82010037SARM gem5 Developers case 9: 82110037SARM gem5 Developers grant = x; 82210037SARM gem5 Developers break; 82310037SARM gem5 Developers case 4: 82410037SARM gem5 Developers case 5: 82510037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 82610037SARM gem5 Developers break; 82710037SARM gem5 Developers case 6: 82810037SARM gem5 Developers case 7: 82910037SARM gem5 Developers grant = r || w; 83010037SARM gem5 Developers break; 83110037SARM gem5 Developers case 12: 83210037SARM gem5 Developers case 13: 83310037SARM gem5 Developers grant = r || x; 83410037SARM gem5 Developers break; 83510037SARM gem5 Developers case 14: 83610037SARM gem5 Developers case 15: 83710037SARM gem5 Developers grant = r; 83810037SARM gem5 Developers break; 83910037SARM gem5 Developers default: 84010037SARM gem5 Developers grant = false; 84110037SARM gem5 Developers } 84210037SARM gem5 Developers } 84310037SARM gem5 Developers break; 84410037SARM gem5 Developers case EL1: 84510037SARM gem5 Developers { 84610037SARM gem5 Developers uint8_t perm = (ap << 2) | (xn << 1) | pxn; 84710037SARM gem5 Developers switch (perm) { 84810037SARM gem5 Developers case 0: 84910037SARM gem5 Developers case 2: 85010037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn); 85110037SARM gem5 Developers break; 85210037SARM gem5 Developers case 1: 85310037SARM gem5 Developers case 3: 85410037SARM gem5 Developers case 4: 85510037SARM gem5 Developers case 5: 85610037SARM gem5 Developers case 6: 85710037SARM gem5 Developers case 7: 85810037SARM gem5 Developers // regions that are writeable at EL0 should not be 85910037SARM gem5 Developers // executable at EL1 86010037SARM gem5 Developers grant = r || w; 86110037SARM gem5 Developers break; 86210037SARM gem5 Developers case 8: 86310037SARM gem5 Developers case 10: 86410037SARM gem5 Developers case 12: 86510037SARM gem5 Developers case 14: 86610037SARM gem5 Developers grant = r || x; 86710037SARM gem5 Developers break; 86810037SARM gem5 Developers case 9: 86910037SARM gem5 Developers case 11: 87010037SARM gem5 Developers case 13: 87110037SARM gem5 Developers case 15: 87210037SARM gem5 Developers grant = r; 87310037SARM gem5 Developers break; 87410037SARM gem5 Developers default: 87510037SARM gem5 Developers grant = false; 87610037SARM gem5 Developers } 87710037SARM gem5 Developers } 87810037SARM gem5 Developers break; 87910037SARM gem5 Developers case EL2: 88010037SARM gem5 Developers case EL3: 88110037SARM gem5 Developers { 88210037SARM gem5 Developers uint8_t perm = (ap & 0x2) | xn; 88310037SARM gem5 Developers switch (perm) { 88410037SARM gem5 Developers case 0: 88510037SARM gem5 Developers grant = r || w || (x && !sctlr.wxn) ; 88610037SARM gem5 Developers break; 88710037SARM gem5 Developers case 1: 88810037SARM gem5 Developers grant = r || w; 88910037SARM gem5 Developers break; 89010037SARM gem5 Developers case 2: 89110037SARM gem5 Developers grant = r || x; 89210037SARM gem5 Developers break; 89310037SARM gem5 Developers case 3: 89410037SARM gem5 Developers grant = r; 89510037SARM gem5 Developers break; 89610037SARM gem5 Developers default: 89710037SARM gem5 Developers grant = false; 89810037SARM gem5 Developers } 89910037SARM gem5 Developers } 90010037SARM gem5 Developers break; 90110037SARM gem5 Developers } 90210037SARM gem5 Developers } 90310037SARM gem5 Developers 90410037SARM gem5 Developers if (!grant) { 90510037SARM gem5 Developers if (is_fetch) { 90610037SARM gem5 Developers permsFaults++; 90710037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. " 90810037SARM gem5 Developers "AP:%d priv:%d write:%d ns:%d sif:%d " 90910037SARM gem5 Developers "sctlr.afe: %d\n", 91010037SARM gem5 Developers ap, is_priv, is_write, te->ns, scr.sif, sctlr.afe); 91110037SARM gem5 Developers // Use PC value instead of vaddr because vaddr might be aligned to 91210037SARM gem5 Developers // cache line and should not be the address reported in FAR 91310037SARM gem5 Developers return new PrefetchAbort(req->getPC(), 91410037SARM gem5 Developers ArmFault::PermissionLL + te->lookupLevel, 91510037SARM gem5 Developers isStage2, ArmFault::LpaeTran); 91610037SARM gem5 Developers } else { 91710037SARM gem5 Developers permsFaults++; 91810037SARM gem5 Developers DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d " 91910037SARM gem5 Developers "priv:%d write:%d\n", ap, is_priv, is_write); 92010037SARM gem5 Developers return new DataAbort(vaddr_tainted, te->domain, is_write, 92110037SARM gem5 Developers ArmFault::PermissionLL + te->lookupLevel, 92210037SARM gem5 Developers isStage2, ArmFault::LpaeTran); 92310037SARM gem5 Developers } 92410037SARM gem5 Developers } 92510037SARM gem5 Developers 92610037SARM gem5 Developers return NoFault; 92710037SARM gem5 Developers} 92810037SARM gem5 Developers 92910037SARM gem5 DevelopersFault 9307404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 93110037SARM gem5 Developers Translation *translation, bool &delay, bool timing, 93210037SARM gem5 Developers TLB::ArmTranslationType tranType, bool functional) 9337404SAli.Saidi@ARM.com{ 9348733Sgeoffrey.blake@arm.com // No such thing as a functional timing access 9358733Sgeoffrey.blake@arm.com assert(!(timing && functional)); 9368733Sgeoffrey.blake@arm.com 93710037SARM gem5 Developers updateMiscReg(tc, tranType); 93810037SARM gem5 Developers 93910037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 94010037SARM gem5 Developers Addr vaddr = 0; 94110037SARM gem5 Developers if (aarch64) 94210037SARM gem5 Developers vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 94310037SARM gem5 Developers else 94410037SARM gem5 Developers vaddr = vaddr_tainted; 94510037SARM gem5 Developers uint32_t flags = req->getFlags(); 94610037SARM gem5 Developers 94710037SARM gem5 Developers bool is_fetch = (mode == Execute); 94810037SARM gem5 Developers bool is_write = (mode == Write); 94910037SARM gem5 Developers bool long_desc_format = aarch64 || (haveLPAE && ttbcr.eae); 95010037SARM gem5 Developers ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran 95110037SARM gem5 Developers : ArmFault::VmsaTran; 95210037SARM gem5 Developers 95310037SARM gem5 Developers req->setAsid(asid); 95410037SARM gem5 Developers 95510037SARM gem5 Developers DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", 95610037SARM gem5 Developers isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 95710037SARM gem5 Developers 95810037SARM gem5 Developers DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 95910037SARM gem5 Developers "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2, 96010037SARM gem5 Developers scr, sctlr, flags, tranType); 96110037SARM gem5 Developers 96210037SARM gem5 Developers // Generate an alignment fault for unaligned PC 96310037SARM gem5 Developers if (aarch64 && is_fetch && (req->getPC() & mask(2))) { 96410037SARM gem5 Developers return new PCAlignmentFault(req->getPC()); 9658202SAli.Saidi@ARM.com } 9667749SAli.Saidi@ARM.com 9677603SGene.Wu@arm.com // If this is a clrex instruction, provide a PA of 0 with no fault 9687603SGene.Wu@arm.com // This will force the monitor to set the tracked address to 0 9697603SGene.Wu@arm.com // a bit of a hack but this effectively clrears this processors monitor 9707705Sgblack@eecs.umich.edu if (flags & Request::CLEAR_LL){ 97110037SARM gem5 Developers // @todo: check implications of security extensions 9727603SGene.Wu@arm.com req->setPaddr(0); 9737606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 9747705Sgblack@eecs.umich.edu req->setFlags(Request::CLEAR_LL); 9757603SGene.Wu@arm.com return NoFault; 9767603SGene.Wu@arm.com } 9777608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 9787608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 9797608SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 9807608SGene.Wu@arm.com } 9817404SAli.Saidi@ARM.com if (!is_fetch) { 9827404SAli.Saidi@ARM.com assert(flags & MustBeOne); 9837404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 98410037SARM gem5 Developers if (vaddr & mask(flags & AlignmentMask)) { 9857734SAli.Saidi@ARM.com alignFaults++; 98610037SARM gem5 Developers return new DataAbort(vaddr_tainted, 98710037SARM gem5 Developers TlbEntry::DomainType::NoAccess, is_write, 98810037SARM gem5 Developers ArmFault::AlignmentFault, isStage2, 98910037SARM gem5 Developers tranMethod); 9907404SAli.Saidi@ARM.com } 9917404SAli.Saidi@ARM.com } 9927404SAli.Saidi@ARM.com } 9937404SAli.Saidi@ARM.com 99410037SARM gem5 Developers // If guest MMU is off or hcr.vm=0 go straight to stage2 99510037SARM gem5 Developers if ((isStage2 && !hcr.vm) || (!isStage2 && !sctlr.m)) { 9967404SAli.Saidi@ARM.com 9977093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 99810037SARM gem5 Developers // When the MMU is off the security attribute corresponds to the 99910037SARM gem5 Developers // security state of the processor 100010037SARM gem5 Developers if (isSecure) 100110037SARM gem5 Developers req->setFlags(Request::SECURE); 100210037SARM gem5 Developers 100310037SARM gem5 Developers // @todo: double check this (ARM ARM issue C B3.2.1) 100410037SARM gem5 Developers if (long_desc_format || sctlr.tre == 0) { 10057404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 10067404SAli.Saidi@ARM.com } else { 10077404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 100810037SARM gem5 Developers req->setFlags(Request::UNCACHEABLE); 10097404SAli.Saidi@ARM.com } 10107436Sdam.sunwoo@arm.com 10117436Sdam.sunwoo@arm.com // Set memory attributes 10127436Sdam.sunwoo@arm.com TlbEntry temp_te; 101310037SARM gem5 Developers temp_te.ns = !isSecure; 101410037SARM gem5 Developers if (isStage2 || hcr.dc == 0 || isSecure || 101510037SARM gem5 Developers (isHyp && !(tranType & S1CTran))) { 101610037SARM gem5 Developers 101710037SARM gem5 Developers temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal 101810037SARM gem5 Developers : TlbEntry::MemoryType::StronglyOrdered; 101910037SARM gem5 Developers temp_te.innerAttrs = 0x0; 102010037SARM gem5 Developers temp_te.outerAttrs = 0x0; 102110037SARM gem5 Developers temp_te.shareable = true; 102210037SARM gem5 Developers temp_te.outerShareable = true; 102310037SARM gem5 Developers } else { 102410037SARM gem5 Developers temp_te.mtype = TlbEntry::MemoryType::Normal; 102510037SARM gem5 Developers temp_te.innerAttrs = 0x3; 102610037SARM gem5 Developers temp_te.outerAttrs = 0x3; 102710037SARM gem5 Developers temp_te.shareable = false; 102810037SARM gem5 Developers temp_te.outerShareable = false; 102910037SARM gem5 Developers } 103010037SARM gem5 Developers temp_te.setAttributes(long_desc_format); 103110367SAndrew.Bardsley@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: " 103210367SAndrew.Bardsley@arm.com "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", 103310037SARM gem5 Developers temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs, 103410037SARM gem5 Developers isStage2); 10357436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 10367436Sdam.sunwoo@arm.com 103710037SARM gem5 Developers return trickBoxCheck(req, mode, TlbEntry::DomainType::NoAccess); 10387404SAli.Saidi@ARM.com } 10397404SAli.Saidi@ARM.com 104010037SARM gem5 Developers DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n", 104110037SARM gem5 Developers isStage2 ? "IPA" : "VA", vaddr_tainted, asid); 10427404SAli.Saidi@ARM.com // Translation enabled 10437404SAli.Saidi@ARM.com 104410037SARM gem5 Developers TlbEntry *te = NULL; 104510037SARM gem5 Developers TlbEntry mergeTe; 104610037SARM gem5 Developers Fault fault = getResultTe(&te, req, tc, mode, translation, timing, 104710037SARM gem5 Developers functional, &mergeTe); 104810037SARM gem5 Developers // only proceed if we have a valid table entry 104910037SARM gem5 Developers if ((te == NULL) && (fault == NoFault)) delay = true; 105010037SARM gem5 Developers 105110037SARM gem5 Developers // If we have the table entry transfer some of the attributes to the 105210037SARM gem5 Developers // request that triggered the translation 105310037SARM gem5 Developers if (te != NULL) { 105410037SARM gem5 Developers // Set memory attributes 105510037SARM gem5 Developers DPRINTF(TLBVerbose, 105610367SAndrew.Bardsley@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, " 105710367SAndrew.Bardsley@arm.com "outerAttrs: %d, mtype: %d, isStage2: %d\n", 105810037SARM gem5 Developers te->shareable, te->innerAttrs, te->outerAttrs, 105910037SARM gem5 Developers static_cast<uint8_t>(te->mtype), isStage2); 106010037SARM gem5 Developers setAttr(te->attributes); 106110037SARM gem5 Developers if (te->nonCacheable) { 106210037SARM gem5 Developers req->setFlags(Request::UNCACHEABLE); 106310037SARM gem5 Developers } 106410037SARM gem5 Developers 106510037SARM gem5 Developers if (!bootUncacheability && 106610037SARM gem5 Developers ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) { 106710037SARM gem5 Developers req->setFlags(Request::UNCACHEABLE); 106810037SARM gem5 Developers } 106910037SARM gem5 Developers 107010037SARM gem5 Developers req->setPaddr(te->pAddr(vaddr)); 107110037SARM gem5 Developers if (isSecure && !te->ns) { 107210037SARM gem5 Developers req->setFlags(Request::SECURE); 107310037SARM gem5 Developers } 107410037SARM gem5 Developers if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 107510037SARM gem5 Developers (te->mtype != TlbEntry::MemoryType::Normal)) { 107610037SARM gem5 Developers // Unaligned accesses to Device memory should always cause an 107710037SARM gem5 Developers // abort regardless of sctlr.a 107810037SARM gem5 Developers alignFaults++; 107910037SARM gem5 Developers return new DataAbort(vaddr_tainted, 108010037SARM gem5 Developers TlbEntry::DomainType::NoAccess, is_write, 108110037SARM gem5 Developers ArmFault::AlignmentFault, isStage2, 108210037SARM gem5 Developers tranMethod); 108310037SARM gem5 Developers } 108410037SARM gem5 Developers 108510037SARM gem5 Developers // Check for a trickbox generated address fault 108610037SARM gem5 Developers if (fault == NoFault) { 108710037SARM gem5 Developers fault = trickBoxCheck(req, mode, te->domain); 108810037SARM gem5 Developers } 108910037SARM gem5 Developers } 109010037SARM gem5 Developers 109110037SARM gem5 Developers // Generate Illegal Inst Set State fault if IL bit is set in CPSR 109210037SARM gem5 Developers if (fault == NoFault) { 109310037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 109410037SARM gem5 Developers if (aarch64 && is_fetch && cpsr.il == 1) { 109510037SARM gem5 Developers return new IllegalInstSetStateFault(); 109610037SARM gem5 Developers } 109710037SARM gem5 Developers } 109810037SARM gem5 Developers 109910037SARM gem5 Developers return fault; 110010037SARM gem5 Developers} 110110037SARM gem5 Developers 110210037SARM gem5 DevelopersFault 110310037SARM gem5 DevelopersTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 110410037SARM gem5 Developers TLB::ArmTranslationType tranType) 110510037SARM gem5 Developers{ 110610037SARM gem5 Developers updateMiscReg(tc, tranType); 110710037SARM gem5 Developers 110810037SARM gem5 Developers if (directToStage2) { 110910037SARM gem5 Developers assert(stage2Tlb); 111010037SARM gem5 Developers return stage2Tlb->translateAtomic(req, tc, mode, tranType); 111110037SARM gem5 Developers } 111210037SARM gem5 Developers 111310037SARM gem5 Developers bool delay = false; 111410037SARM gem5 Developers Fault fault; 111510037SARM gem5 Developers if (FullSystem) 111610037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 111710037SARM gem5 Developers else 111810037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 111910037SARM gem5 Developers assert(!delay); 112010037SARM gem5 Developers return fault; 112110037SARM gem5 Developers} 112210037SARM gem5 Developers 112310037SARM gem5 DevelopersFault 112410037SARM gem5 DevelopersTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 112510037SARM gem5 Developers TLB::ArmTranslationType tranType) 112610037SARM gem5 Developers{ 112710037SARM gem5 Developers updateMiscReg(tc, tranType); 112810037SARM gem5 Developers 112910037SARM gem5 Developers if (directToStage2) { 113010037SARM gem5 Developers assert(stage2Tlb); 113110037SARM gem5 Developers return stage2Tlb->translateFunctional(req, tc, mode, tranType); 113210037SARM gem5 Developers } 113310037SARM gem5 Developers 113410037SARM gem5 Developers bool delay = false; 113510037SARM gem5 Developers Fault fault; 113610037SARM gem5 Developers if (FullSystem) 113710037SARM gem5 Developers fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 113810037SARM gem5 Developers else 113910037SARM gem5 Developers fault = translateSe(req, tc, mode, NULL, delay, false); 114010037SARM gem5 Developers assert(!delay); 114110037SARM gem5 Developers return fault; 114210037SARM gem5 Developers} 114310037SARM gem5 Developers 114410037SARM gem5 DevelopersFault 114510037SARM gem5 DevelopersTLB::translateTiming(RequestPtr req, ThreadContext *tc, 114610037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 114710037SARM gem5 Developers{ 114810037SARM gem5 Developers updateMiscReg(tc, tranType); 114910037SARM gem5 Developers 115010037SARM gem5 Developers if (directToStage2) { 115110037SARM gem5 Developers assert(stage2Tlb); 115210037SARM gem5 Developers return stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 115310037SARM gem5 Developers } 115410037SARM gem5 Developers 115510037SARM gem5 Developers assert(translation); 115610037SARM gem5 Developers 115710037SARM gem5 Developers return translateComplete(req, tc, translation, mode, tranType, isStage2); 115810037SARM gem5 Developers} 115910037SARM gem5 Developers 116010037SARM gem5 DevelopersFault 116110037SARM gem5 DevelopersTLB::translateComplete(RequestPtr req, ThreadContext *tc, 116210037SARM gem5 Developers Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 116310037SARM gem5 Developers bool callFromS2) 116410037SARM gem5 Developers{ 116510037SARM gem5 Developers bool delay = false; 116610037SARM gem5 Developers Fault fault; 116710037SARM gem5 Developers if (FullSystem) 116810037SARM gem5 Developers fault = translateFs(req, tc, mode, translation, delay, true, tranType); 116910037SARM gem5 Developers else 117010037SARM gem5 Developers fault = translateSe(req, tc, mode, translation, delay, true); 117110037SARM gem5 Developers DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 117210037SARM gem5 Developers NoFault); 117310037SARM gem5 Developers // If we have a translation, and we're not in the middle of doing a stage 117410037SARM gem5 Developers // 2 translation tell the translation that we've either finished or its 117510037SARM gem5 Developers // going to take a while. By not doing this when we're in the middle of a 117610037SARM gem5 Developers // stage 2 translation we prevent marking the translation as delayed twice, 117710037SARM gem5 Developers // one when the translation starts and again when the stage 1 translation 117810037SARM gem5 Developers // completes. 117910037SARM gem5 Developers if (translation && (callFromS2 || !stage2Req || req->hasPaddr() || fault != NoFault)) { 118010037SARM gem5 Developers if (!delay) 118110037SARM gem5 Developers translation->finish(fault, req, tc, mode); 118210037SARM gem5 Developers else 118310037SARM gem5 Developers translation->markDelayed(); 118410037SARM gem5 Developers } 118510037SARM gem5 Developers return fault; 118610037SARM gem5 Developers} 118710037SARM gem5 Developers 118810037SARM gem5 DevelopersBaseMasterPort* 118910037SARM gem5 DevelopersTLB::getMasterPort() 119010037SARM gem5 Developers{ 119110037SARM gem5 Developers return &tableWalker->getMasterPort("port"); 119210037SARM gem5 Developers} 119310037SARM gem5 Developers 119410037SARM gem5 DevelopersDmaPort& 119510037SARM gem5 DevelopersTLB::getWalkerPort() 119610037SARM gem5 Developers{ 119710037SARM gem5 Developers return tableWalker->getWalkerPort(); 119810037SARM gem5 Developers} 119910037SARM gem5 Developers 120010037SARM gem5 Developersvoid 120110037SARM gem5 DevelopersTLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) 120210037SARM gem5 Developers{ 120310037SARM gem5 Developers // check if the regs have changed, or the translation mode is different. 120410037SARM gem5 Developers // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle 120510037SARM gem5 Developers // one type of translation anyway 120610037SARM gem5 Developers if (miscRegValid && ((tranType == curTranType) || isStage2)) { 120710037SARM gem5 Developers return; 120810037SARM gem5 Developers } 120910037SARM gem5 Developers 121010037SARM gem5 Developers DPRINTF(TLBVerbose, "TLB variables changed!\n"); 121110037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 121210037SARM gem5 Developers // Dependencies: SCR/SCR_EL3, CPSR 121310037SARM gem5 Developers isSecure = inSecureState(tc); 121410037SARM gem5 Developers isSecure &= (tranType & HypMode) == 0; 121510037SARM gem5 Developers isSecure &= (tranType & S1S2NsTran) == 0; 121610037SARM gem5 Developers aarch64 = !cpsr.width; 121710037SARM gem5 Developers if (aarch64) { // AArch64 121810037SARM gem5 Developers aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; 121910037SARM gem5 Developers switch (aarch64EL) { 122010037SARM gem5 Developers case EL0: 122110037SARM gem5 Developers case EL1: 122210037SARM gem5 Developers { 122310037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 122410037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 122510037SARM gem5 Developers uint64_t ttbr_asid = ttbcr.a1 ? 122610037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR1_EL1) : 122710037SARM gem5 Developers tc->readMiscReg(MISCREG_TTBR0_EL1); 122810037SARM gem5 Developers asid = bits(ttbr_asid, 122910037SARM gem5 Developers (haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48); 123010037SARM gem5 Developers } 123110037SARM gem5 Developers break; 123210037SARM gem5 Developers case EL2: 123310037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); 123410037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL2); 123510037SARM gem5 Developers asid = -1; 123610037SARM gem5 Developers break; 123710037SARM gem5 Developers case EL3: 123810037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 123910037SARM gem5 Developers ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 124010037SARM gem5 Developers asid = -1; 124110037SARM gem5 Developers break; 124210037SARM gem5 Developers } 124310037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR_EL3); 124410037SARM gem5 Developers isPriv = aarch64EL != EL0; 124510037SARM gem5 Developers // @todo: modify this behaviour to support Virtualization in 124610037SARM gem5 Developers // AArch64 124710037SARM gem5 Developers vmid = 0; 124810037SARM gem5 Developers isHyp = false; 124910037SARM gem5 Developers directToStage2 = false; 125010037SARM gem5 Developers stage2Req = false; 125110037SARM gem5 Developers } else { // AArch32 125210037SARM gem5 Developers sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc, 125310037SARM gem5 Developers !isSecure)); 125410037SARM gem5 Developers ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc, 125510037SARM gem5 Developers !isSecure)); 125610037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR); 125710037SARM gem5 Developers isPriv = cpsr.mode != MODE_USER; 125810037SARM gem5 Developers if (haveLPAE && ttbcr.eae) { 125910037SARM gem5 Developers // Long-descriptor translation table format in use 126010037SARM gem5 Developers uint64_t ttbr_asid = tc->readMiscReg( 126110037SARM gem5 Developers flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1 126210037SARM gem5 Developers : MISCREG_TTBR0, 126310037SARM gem5 Developers tc, !isSecure)); 126410037SARM gem5 Developers asid = bits(ttbr_asid, 55, 48); 126510037SARM gem5 Developers } else { 126610037SARM gem5 Developers // Short-descriptor translation table format in use 126710037SARM gem5 Developers CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked( 126810037SARM gem5 Developers MISCREG_CONTEXTIDR, tc,!isSecure)); 126910037SARM gem5 Developers asid = context_id.asid; 127010037SARM gem5 Developers } 127110037SARM gem5 Developers prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc, 127210037SARM gem5 Developers !isSecure)); 127310037SARM gem5 Developers nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc, 127410037SARM gem5 Developers !isSecure)); 127510037SARM gem5 Developers dacr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_DACR, tc, 127610037SARM gem5 Developers !isSecure)); 127710037SARM gem5 Developers hcr = tc->readMiscReg(MISCREG_HCR); 127810037SARM gem5 Developers 127910037SARM gem5 Developers if (haveVirtualization) { 128010037SARM gem5 Developers vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); 128110037SARM gem5 Developers isHyp = cpsr.mode == MODE_HYP; 128210037SARM gem5 Developers isHyp |= tranType & HypMode; 128310037SARM gem5 Developers isHyp &= (tranType & S1S2NsTran) == 0; 128410037SARM gem5 Developers isHyp &= (tranType & S1CTran) == 0; 128510037SARM gem5 Developers if (isHyp) { 128610037SARM gem5 Developers sctlr = tc->readMiscReg(MISCREG_HSCTLR); 128710037SARM gem5 Developers } 128810037SARM gem5 Developers // Work out if we should skip the first stage of translation and go 128910037SARM gem5 Developers // directly to stage 2. This value is cached so we don't have to 129010037SARM gem5 Developers // compute it for every translation. 129110037SARM gem5 Developers stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure && 129210037SARM gem5 Developers !(tranType & S1CTran); 129310037SARM gem5 Developers directToStage2 = stage2Req && !sctlr.m; 129410037SARM gem5 Developers } else { 129510037SARM gem5 Developers vmid = 0; 129610037SARM gem5 Developers stage2Req = false; 129710037SARM gem5 Developers isHyp = false; 129810037SARM gem5 Developers directToStage2 = false; 129910037SARM gem5 Developers } 130010037SARM gem5 Developers } 130110037SARM gem5 Developers miscRegValid = true; 130210037SARM gem5 Developers curTranType = tranType; 130310037SARM gem5 Developers} 130410037SARM gem5 Developers 130510037SARM gem5 DevelopersFault 130610037SARM gem5 DevelopersTLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 130710037SARM gem5 Developers Translation *translation, bool timing, bool functional, 130810037SARM gem5 Developers bool is_secure, TLB::ArmTranslationType tranType) 130910037SARM gem5 Developers{ 131010037SARM gem5 Developers bool is_fetch = (mode == Execute); 131110037SARM gem5 Developers bool is_write = (mode == Write); 131210037SARM gem5 Developers 131310037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 131410037SARM gem5 Developers Addr vaddr = 0; 131510037SARM gem5 Developers ExceptionLevel target_el = aarch64 ? aarch64EL : EL1; 131610037SARM gem5 Developers if (aarch64) { 131710037SARM gem5 Developers vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el); 131810037SARM gem5 Developers } else { 131910037SARM gem5 Developers vaddr = vaddr_tainted; 132010037SARM gem5 Developers } 132110037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 132210037SARM gem5 Developers if (*te == NULL) { 132310037SARM gem5 Developers if (req->isPrefetch()) { 132410037SARM gem5 Developers // if the request is a prefetch don't attempt to fill the TLB or go 132510037SARM gem5 Developers // any further with the memory access (here we can safely use the 132610037SARM gem5 Developers // fault status for the short desc. format in all cases) 13277734SAli.Saidi@ARM.com prefetchFaults++; 132810037SARM gem5 Developers return new PrefetchAbort(vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); 13297611SGene.Wu@arm.com } 13307734SAli.Saidi@ARM.com 13317734SAli.Saidi@ARM.com if (is_fetch) 13327734SAli.Saidi@ARM.com instMisses++; 13337734SAli.Saidi@ARM.com else if (is_write) 13347734SAli.Saidi@ARM.com writeMisses++; 13357734SAli.Saidi@ARM.com else 13367734SAli.Saidi@ARM.com readMisses++; 13377734SAli.Saidi@ARM.com 13387404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 13397404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 134010037SARM gem5 Developers DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n", 134110037SARM gem5 Developers vaddr_tainted, asid, vmid); 134210037SARM gem5 Developers Fault fault; 134310037SARM gem5 Developers fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode, 134410037SARM gem5 Developers translation, timing, functional, is_secure, 134510037SARM gem5 Developers tranType); 134610037SARM gem5 Developers // for timing mode, return and wait for table walk, 134710037SARM gem5 Developers if (timing || fault != NoFault) { 13487437Sdam.sunwoo@arm.com return fault; 13497437Sdam.sunwoo@arm.com } 13507404SAli.Saidi@ARM.com 135110037SARM gem5 Developers *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 135210037SARM gem5 Developers if (!*te) 13537404SAli.Saidi@ARM.com printTlb(); 135410037SARM gem5 Developers assert(*te); 13557734SAli.Saidi@ARM.com } else { 13567734SAli.Saidi@ARM.com if (is_fetch) 13577734SAli.Saidi@ARM.com instHits++; 13587734SAli.Saidi@ARM.com else if (is_write) 13597734SAli.Saidi@ARM.com writeHits++; 13607734SAli.Saidi@ARM.com else 13617734SAli.Saidi@ARM.com readHits++; 13627404SAli.Saidi@ARM.com } 13636757SAli.Saidi@ARM.com return NoFault; 13647404SAli.Saidi@ARM.com} 13656757SAli.Saidi@ARM.com 13667404SAli.Saidi@ARM.comFault 136710037SARM gem5 DevelopersTLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 136810037SARM gem5 Developers Translation *translation, bool timing, bool functional, 136910037SARM gem5 Developers TlbEntry *mergeTe) 13707404SAli.Saidi@ARM.com{ 13717404SAli.Saidi@ARM.com Fault fault; 137210037SARM gem5 Developers TlbEntry *s1Te = NULL; 137310037SARM gem5 Developers 137410037SARM gem5 Developers Addr vaddr_tainted = req->getVaddr(); 137510037SARM gem5 Developers 137610037SARM gem5 Developers // Get the stage 1 table entry 137710037SARM gem5 Developers fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 137810037SARM gem5 Developers isSecure, curTranType); 137910037SARM gem5 Developers // only proceed if we have a valid table entry 138010037SARM gem5 Developers if ((s1Te != NULL) && (fault == NoFault)) { 138110037SARM gem5 Developers // Check stage 1 permissions before checking stage 2 138210037SARM gem5 Developers if (aarch64) 138310037SARM gem5 Developers fault = checkPermissions64(s1Te, req, mode, tc); 138410037SARM gem5 Developers else 138510037SARM gem5 Developers fault = checkPermissions(s1Te, req, mode); 138610037SARM gem5 Developers if (stage2Req & (fault == NoFault)) { 138710037SARM gem5 Developers Stage2LookUp *s2Lookup = new Stage2LookUp(this, stage2Tlb, *s1Te, 138810037SARM gem5 Developers req, translation, mode, timing, functional, curTranType); 138910037SARM gem5 Developers fault = s2Lookup->getTe(tc, mergeTe); 139010037SARM gem5 Developers if (s2Lookup->isComplete()) { 139110037SARM gem5 Developers *te = mergeTe; 139210037SARM gem5 Developers // We've finished with the lookup so delete it 139310037SARM gem5 Developers delete s2Lookup; 139410037SARM gem5 Developers } else { 139510037SARM gem5 Developers // The lookup hasn't completed, so we can't delete it now. We 139610037SARM gem5 Developers // get round this by asking the object to self delete when the 139710037SARM gem5 Developers // translation is complete. 139810037SARM gem5 Developers s2Lookup->setSelfDelete(); 139910037SARM gem5 Developers } 140010037SARM gem5 Developers } else { 140110037SARM gem5 Developers // This case deals with an S1 hit (or bypass), followed by 140210037SARM gem5 Developers // an S2 hit-but-perms issue 140310037SARM gem5 Developers if (isStage2) { 140410037SARM gem5 Developers DPRINTF(TLBVerbose, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n", 140510037SARM gem5 Developers vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0, fault); 140610037SARM gem5 Developers if (fault != NoFault) { 140710037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 140810037SARM gem5 Developers armFault->annotate(ArmFault::S1PTW, false); 140910037SARM gem5 Developers armFault->annotate(ArmFault::OVA, vaddr_tainted); 141010037SARM gem5 Developers } 141110037SARM gem5 Developers } 141210037SARM gem5 Developers *te = s1Te; 141310037SARM gem5 Developers } 141410037SARM gem5 Developers } 14157404SAli.Saidi@ARM.com return fault; 14166019Shines@cs.fsu.edu} 14176019Shines@cs.fsu.edu 14186116Snate@binkert.orgArmISA::TLB * 14196116Snate@binkert.orgArmTLBParams::create() 14206019Shines@cs.fsu.edu{ 14216116Snate@binkert.org return new ArmISA::TLB(this); 14226019Shines@cs.fsu.edu} 1423