tlb.cc revision 10418
17404SAli.Saidi@ARM.com/* 29015Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 157404SAli.Saidi@ARM.com * All rights reserved. 167404SAli.Saidi@ARM.com * 177404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 187404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 197404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 207404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 217404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 227404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 237404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 247404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 257404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 267404SAli.Saidi@ARM.com * this software without specific prior written permission. 277404SAli.Saidi@ARM.com * 287404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397404SAli.Saidi@ARM.com * 407404SAli.Saidi@ARM.com * Authors: Ali Saidi 417404SAli.Saidi@ARM.com * Nathan Binkert 427404SAli.Saidi@ARM.com * Steve Reinhardt 437578Sdam.sunwoo@arm.com */ 447578Sdam.sunwoo@arm.com 457404SAli.Saidi@ARM.com#include <string> 467404SAli.Saidi@ARM.com#include <vector> 479016Sandreas.hansson@arm.com 487404SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 497404SAli.Saidi@ARM.com#include "arch/arm/pagetable.hh" 507404SAli.Saidi@ARM.com#include "arch/arm/system.hh" 517404SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 527878Sgblack@eecs.umich.edu#include "arch/arm/stage2_lookup.hh" 537404SAli.Saidi@ARM.com#include "arch/arm/stage2_mmu.hh" 547404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 557404SAli.Saidi@ARM.com#include "arch/arm/utility.hh" 567404SAli.Saidi@ARM.com#include "base/inifile.hh" 577404SAli.Saidi@ARM.com#include "base/str.hh" 587404SAli.Saidi@ARM.com#include "base/trace.hh" 597404SAli.Saidi@ARM.com#include "cpu/base.hh" 607404SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 617404SAli.Saidi@ARM.com#include "debug/Checkpoint.hh" 627694SAli.Saidi@ARM.com#include "debug/TLB.hh" 637404SAli.Saidi@ARM.com#include "debug/TLBVerbose.hh" 647404SAli.Saidi@ARM.com#include "mem/page_table.hh" 657404SAli.Saidi@ARM.com#include "params/ArmTLB.hh" 667404SAli.Saidi@ARM.com#include "sim/full_system.hh" 677404SAli.Saidi@ARM.com#include "sim/process.hh" 687404SAli.Saidi@ARM.com 697404SAli.Saidi@ARM.comusing namespace std; 707404SAli.Saidi@ARM.comusing namespace ArmISA; 717404SAli.Saidi@ARM.com 727436Sdam.sunwoo@arm.comTLB::TLB(const ArmTLBParams *p) 737404SAli.Saidi@ARM.com : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), 747404SAli.Saidi@ARM.com isStage2(p->is_stage2), stage2Req(false), _attr(0), 757436Sdam.sunwoo@arm.com directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), 767436Sdam.sunwoo@arm.com stage2Mmu(NULL), rangeMRU(1), bootUncacheability(false), 777436Sdam.sunwoo@arm.com miscRegValid(false), curTranType(NormalTran) 787436Sdam.sunwoo@arm.com{ 797404SAli.Saidi@ARM.com tableWalker->setTlb(this); 807404SAli.Saidi@ARM.com 817404SAli.Saidi@ARM.com // Cache system-level properties 827404SAli.Saidi@ARM.com haveLPAE = tableWalker->haveLPAE(); 837404SAli.Saidi@ARM.com haveVirtualization = tableWalker->haveVirtualization(); 847404SAli.Saidi@ARM.com haveLargeAsid64 = tableWalker->haveLargeAsid64(); 857404SAli.Saidi@ARM.com} 867404SAli.Saidi@ARM.com 877404SAli.Saidi@ARM.comTLB::~TLB() 887404SAli.Saidi@ARM.com{ 897404SAli.Saidi@ARM.com delete[] table; 907404SAli.Saidi@ARM.com} 917404SAli.Saidi@ARM.com 927404SAli.Saidi@ARM.comvoid 937404SAli.Saidi@ARM.comTLB::init() 947404SAli.Saidi@ARM.com{ 957946SGiacomo.Gabrielli@arm.com if (stage2Mmu && !isStage2) 967404SAli.Saidi@ARM.com stage2Tlb = stage2Mmu->stage2Tlb(); 977694SAli.Saidi@ARM.com} 987694SAli.Saidi@ARM.com 997694SAli.Saidi@ARM.comvoid 1007694SAli.Saidi@ARM.comTLB::setMMU(Stage2MMU *m) 1017694SAli.Saidi@ARM.com{ 1027946SGiacomo.Gabrielli@arm.com stage2Mmu = m; 1037694SAli.Saidi@ARM.com tableWalker->setMMU(m); 1047694SAli.Saidi@ARM.com} 1057404SAli.Saidi@ARM.com 1067404SAli.Saidi@ARM.combool 1077404SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 1087404SAli.Saidi@ARM.com{ 1097404SAli.Saidi@ARM.com updateMiscReg(tc); 1107404SAli.Saidi@ARM.com 1117946SGiacomo.Gabrielli@arm.com if (directToStage2) { 1127404SAli.Saidi@ARM.com assert(stage2Tlb); 1137404SAli.Saidi@ARM.com return stage2Tlb->translateFunctional(tc, va, pa); 1147404SAli.Saidi@ARM.com } 1157404SAli.Saidi@ARM.com 1167404SAli.Saidi@ARM.com TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false, 1177608SGene.Wu@arm.com aarch64 ? aarch64EL : EL1); 1187404SAli.Saidi@ARM.com if (!e) 1197404SAli.Saidi@ARM.com return false; 1207404SAli.Saidi@ARM.com pa = e->pAddr(va); 1217404SAli.Saidi@ARM.com return true; 1227404SAli.Saidi@ARM.com} 1237608SGene.Wu@arm.com 1247404SAli.Saidi@ARM.comFault 1257404SAli.Saidi@ARM.comTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 1267404SAli.Saidi@ARM.com{ 1277404SAli.Saidi@ARM.com return NoFault; 1287404SAli.Saidi@ARM.com} 1297946SGiacomo.Gabrielli@arm.com 1307404SAli.Saidi@ARM.comTlbEntry* 1317404SAli.Saidi@ARM.comTLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, 1327404SAli.Saidi@ARM.com bool functional, bool ignore_asn, uint8_t target_el) 1337404SAli.Saidi@ARM.com{ 1347404SAli.Saidi@ARM.com 1357946SGiacomo.Gabrielli@arm.com TlbEntry *retval = NULL; 1367404SAli.Saidi@ARM.com 1377404SAli.Saidi@ARM.com // Maintaining LRU array 1387404SAli.Saidi@ARM.com int x = 0; 1397404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 1407404SAli.Saidi@ARM.com if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false, 1417946SGiacomo.Gabrielli@arm.com target_el)) || 1427404SAli.Saidi@ARM.com (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) { 1437404SAli.Saidi@ARM.com // We only move the hit entry ahead when the position is higher 1447436Sdam.sunwoo@arm.com // than rangeMRU 1457436Sdam.sunwoo@arm.com if (x > rangeMRU && !functional) { 1467436Sdam.sunwoo@arm.com TlbEntry tmp_entry = table[x]; 1477436Sdam.sunwoo@arm.com for(int i = x; i > 0; i--) 1487436Sdam.sunwoo@arm.com table[i] = table[i - 1]; 1497404SAli.Saidi@ARM.com table[0] = tmp_entry; 1507404SAli.Saidi@ARM.com retval = &table[0]; 1517946SGiacomo.Gabrielli@arm.com } else { 1527404SAli.Saidi@ARM.com retval = &table[x]; 1537404SAli.Saidi@ARM.com } 1547436Sdam.sunwoo@arm.com break; 1557436Sdam.sunwoo@arm.com } 1567436Sdam.sunwoo@arm.com ++x; 1577436Sdam.sunwoo@arm.com } 1587436Sdam.sunwoo@arm.com 1597436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d " 1607436Sdam.sunwoo@arm.com "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " 1617436Sdam.sunwoo@arm.com "el: %d\n", 1627436Sdam.sunwoo@arm.com va, asn, retval ? "hit" : "miss", vmid, hyp, secure, 1637436Sdam.sunwoo@arm.com retval ? retval->pfn : 0, retval ? retval->size : 0, 1647436Sdam.sunwoo@arm.com retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0, 1657436Sdam.sunwoo@arm.com retval ? retval->ns : 0, retval ? retval->nstid : 0, 1667436Sdam.sunwoo@arm.com retval ? retval->global : 0, retval ? retval->asid : 0, 1677436Sdam.sunwoo@arm.com retval ? retval->el : 0); 1687436Sdam.sunwoo@arm.com 1697436Sdam.sunwoo@arm.com return retval; 1707436Sdam.sunwoo@arm.com} 1717436Sdam.sunwoo@arm.com 1727436Sdam.sunwoo@arm.com// insert a new TLB entry 1737436Sdam.sunwoo@arm.comvoid 1747404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1757404SAli.Saidi@ARM.com{ 1767404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1777404SAli.Saidi@ARM.com " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" 1787404SAli.Saidi@ARM.com " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn, 1797436Sdam.sunwoo@arm.com entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, 1807404SAli.Saidi@ARM.com entry.global, entry.valid, entry.nonCacheable, entry.xn, 1817404SAli.Saidi@ARM.com entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid, 1827436Sdam.sunwoo@arm.com entry.isHyp); 1837436Sdam.sunwoo@arm.com 1847436Sdam.sunwoo@arm.com if (table[size - 1].valid) 1857436Sdam.sunwoo@arm.com DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x " 1867404SAli.Saidi@ARM.com "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n", 1877404SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 1887404SAli.Saidi@ARM.com table[size-1].vmid, table[size-1].pfn << table[size-1].N, 1897946SGiacomo.Gabrielli@arm.com table[size-1].size, table[size-1].ap, table[size-1].ns, 1907404SAli.Saidi@ARM.com table[size-1].nstid, table[size-1].global, table[size-1].isHyp, 1917404SAli.Saidi@ARM.com table[size-1].el); 1927404SAli.Saidi@ARM.com 1937404SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1947404SAli.Saidi@ARM.com 1957404SAli.Saidi@ARM.com for (int i = size - 1; i > 0; --i) 1967404SAli.Saidi@ARM.com table[i] = table[i-1]; 1977404SAli.Saidi@ARM.com table[0] = entry; 1987404SAli.Saidi@ARM.com 1997404SAli.Saidi@ARM.com inserts++; 2007404SAli.Saidi@ARM.com} 2017404SAli.Saidi@ARM.com 2027404SAli.Saidi@ARM.comvoid 2037404SAli.Saidi@ARM.comTLB::printTlb() const 2047404SAli.Saidi@ARM.com{ 2057404SAli.Saidi@ARM.com int x = 0; 2067404SAli.Saidi@ARM.com TlbEntry *te; 2077404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 2087404SAli.Saidi@ARM.com while (x < size) { 2097404SAli.Saidi@ARM.com te = &table[x]; 2107404SAli.Saidi@ARM.com if (te->valid) 2117404SAli.Saidi@ARM.com DPRINTF(TLB, " * %s\n", te->print()); 2127404SAli.Saidi@ARM.com ++x; 2137404SAli.Saidi@ARM.com } 2147404SAli.Saidi@ARM.com} 2157404SAli.Saidi@ARM.com 2167404SAli.Saidi@ARM.comvoid 2177404SAli.Saidi@ARM.comTLB::flushAllSecurity(bool secure_lookup, uint8_t target_el, bool ignore_el) 2187404SAli.Saidi@ARM.com{ 2197404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n", 2207946SGiacomo.Gabrielli@arm.com (secure_lookup ? "secure" : "non-secure")); 2217946SGiacomo.Gabrielli@arm.com int x = 0; 2227404SAli.Saidi@ARM.com TlbEntry *te; 2237404SAli.Saidi@ARM.com while (x < size) { 2247404SAli.Saidi@ARM.com te = &table[x]; 2257404SAli.Saidi@ARM.com if (te->valid && secure_lookup == !te->nstid && 2267404SAli.Saidi@ARM.com (te->vmid == vmid || secure_lookup) && 2277404SAli.Saidi@ARM.com checkELMatch(target_el, te->el, ignore_el)) { 2287404SAli.Saidi@ARM.com 2297404SAli.Saidi@ARM.com DPRINTF(TLB, " - %s\n", te->print()); 2307694SAli.Saidi@ARM.com te->valid = false; 2317694SAli.Saidi@ARM.com flushedEntries++; 2327694SAli.Saidi@ARM.com } 2337694SAli.Saidi@ARM.com ++x; 2347694SAli.Saidi@ARM.com } 2357694SAli.Saidi@ARM.com 2367694SAli.Saidi@ARM.com flushTlb++; 2377694SAli.Saidi@ARM.com 2387694SAli.Saidi@ARM.com // If there's a second stage TLB (and we're not it) then flush it as well 2397436Sdam.sunwoo@arm.com // if we're currently in hyp mode 2407436Sdam.sunwoo@arm.com if (!isStage2 && isHyp) { 2417436Sdam.sunwoo@arm.com stage2Tlb->flushAllSecurity(secure_lookup, true); 2427436Sdam.sunwoo@arm.com } 2437436Sdam.sunwoo@arm.com} 2447436Sdam.sunwoo@arm.com 2457436Sdam.sunwoo@arm.comvoid 2467436Sdam.sunwoo@arm.comTLB::flushAllNs(bool hyp, uint8_t target_el, bool ignore_el) 2477436Sdam.sunwoo@arm.com{ 2487436Sdam.sunwoo@arm.com DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n", 2497436Sdam.sunwoo@arm.com (hyp ? "hyp" : "non-hyp")); 2507436Sdam.sunwoo@arm.com int x = 0; 2517436Sdam.sunwoo@arm.com TlbEntry *te; 2527436Sdam.sunwoo@arm.com while (x < size) { 2537436Sdam.sunwoo@arm.com te = &table[x]; 2547436Sdam.sunwoo@arm.com if (te->valid && te->nstid && te->isHyp == hyp && 2557436Sdam.sunwoo@arm.com checkELMatch(target_el, te->el, ignore_el)) { 2567436Sdam.sunwoo@arm.com 2577436Sdam.sunwoo@arm.com DPRINTF(TLB, " - %s\n", te->print()); 2587436Sdam.sunwoo@arm.com flushedEntries++; 2597436Sdam.sunwoo@arm.com te->valid = false; 2607404SAli.Saidi@ARM.com } 2617404SAli.Saidi@ARM.com ++x; 2629015Sandreas.hansson@arm.com } 2639015Sandreas.hansson@arm.com 2649015Sandreas.hansson@arm.com flushTlb++; 2659015Sandreas.hansson@arm.com 2669015Sandreas.hansson@arm.com // If there's a second stage TLB (and we're not it) then flush it as well 2679015Sandreas.hansson@arm.com if (!isStage2 && !hyp) { 2689015Sandreas.hansson@arm.com stage2Tlb->flushAllNs(false, true); 2699015Sandreas.hansson@arm.com } 2709015Sandreas.hansson@arm.com} 2719015Sandreas.hansson@arm.com 2729015Sandreas.hansson@arm.comvoid 2739015Sandreas.hansson@arm.comTLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el) 2749015Sandreas.hansson@arm.com{ 2759015Sandreas.hansson@arm.com DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x " 2769015Sandreas.hansson@arm.com "(%s lookup)\n", mva, asn, (secure_lookup ? 2779015Sandreas.hansson@arm.com "secure" : "non-secure")); 2789015Sandreas.hansson@arm.com _flushMva(mva, asn, secure_lookup, false, false, target_el); 2799015Sandreas.hansson@arm.com flushTlbMvaAsid++; 2809015Sandreas.hansson@arm.com} 2819015Sandreas.hansson@arm.com 2829015Sandreas.hansson@arm.comvoid 2839015Sandreas.hansson@arm.comTLB::flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el) 2849015Sandreas.hansson@arm.com{ 2859015Sandreas.hansson@arm.com DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn, 2869015Sandreas.hansson@arm.com (secure_lookup ? "secure" : "non-secure")); 2879015Sandreas.hansson@arm.com 2889015Sandreas.hansson@arm.com int x = 0 ; 2899015Sandreas.hansson@arm.com TlbEntry *te; 2909165Sandreas.hansson@arm.com 2919165Sandreas.hansson@arm.com while (x < size) { 2929015Sandreas.hansson@arm.com te = &table[x]; 2939015Sandreas.hansson@arm.com if (te->valid && te->asid == asn && secure_lookup == !te->nstid && 2949015Sandreas.hansson@arm.com (te->vmid == vmid || secure_lookup) && 2957439Sdam.sunwoo@arm.com checkELMatch(target_el, te->el, false)) { 2967439Sdam.sunwoo@arm.com 2977439Sdam.sunwoo@arm.com te->valid = false; 2987439Sdam.sunwoo@arm.com DPRINTF(TLB, " - %s\n", te->print()); 2997439Sdam.sunwoo@arm.com flushedEntries++; 3007439Sdam.sunwoo@arm.com } 3017439Sdam.sunwoo@arm.com ++x; 3027439Sdam.sunwoo@arm.com } 3037439Sdam.sunwoo@arm.com flushTlbAsid++; 3047439Sdam.sunwoo@arm.com} 3057439Sdam.sunwoo@arm.com 3067439Sdam.sunwoo@arm.comvoid 3077439Sdam.sunwoo@arm.comTLB::flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el) 3087439Sdam.sunwoo@arm.com{ 3097439Sdam.sunwoo@arm.com DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva, 3107439Sdam.sunwoo@arm.com (secure_lookup ? "secure" : "non-secure")); 3117439Sdam.sunwoo@arm.com _flushMva(mva, 0xbeef, secure_lookup, hyp, true, target_el); 3127439Sdam.sunwoo@arm.com flushTlbMva++; 3137439Sdam.sunwoo@arm.com} 3147439Sdam.sunwoo@arm.com 3157439Sdam.sunwoo@arm.comvoid 3167439Sdam.sunwoo@arm.comTLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp, 3177439Sdam.sunwoo@arm.com bool ignore_asn, uint8_t target_el) 3187439Sdam.sunwoo@arm.com{ 3197439Sdam.sunwoo@arm.com TlbEntry *te; 3207439Sdam.sunwoo@arm.com // D5.7.2: Sign-extend address to 64 bits 3217439Sdam.sunwoo@arm.com mva = sext<56>(mva); 3227439Sdam.sunwoo@arm.com te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 3237439Sdam.sunwoo@arm.com target_el); 3247439Sdam.sunwoo@arm.com while (te != NULL) { 3257439Sdam.sunwoo@arm.com if (secure_lookup == !te->nstid) { 3267439Sdam.sunwoo@arm.com DPRINTF(TLB, " - %s\n", te->print()); 3277439Sdam.sunwoo@arm.com te->valid = false; 3287439Sdam.sunwoo@arm.com flushedEntries++; 3297439Sdam.sunwoo@arm.com } 3308733Sgeoffrey.blake@arm.com te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 3318733Sgeoffrey.blake@arm.com target_el); 3328733Sgeoffrey.blake@arm.com } 3337439Sdam.sunwoo@arm.com} 3347439Sdam.sunwoo@arm.com 3357439Sdam.sunwoo@arm.combool 3367439Sdam.sunwoo@arm.comTLB::checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el) 3377439Sdam.sunwoo@arm.com{ 3387439Sdam.sunwoo@arm.com bool elMatch = true; 3397439Sdam.sunwoo@arm.com if (!ignore_el) { 3407439Sdam.sunwoo@arm.com if (target_el == 2 || target_el == 3) { 3417439Sdam.sunwoo@arm.com elMatch = (tentry_el == target_el); 3427439Sdam.sunwoo@arm.com } else { 3437439Sdam.sunwoo@arm.com elMatch = (tentry_el == 0) || (tentry_el == 1); 3447439Sdam.sunwoo@arm.com } 3457439Sdam.sunwoo@arm.com } 3467439Sdam.sunwoo@arm.com return elMatch; 3477439Sdam.sunwoo@arm.com} 3487439Sdam.sunwoo@arm.com 3497439Sdam.sunwoo@arm.comvoid 3507439Sdam.sunwoo@arm.comTLB::drainResume() 3517653Sgene.wu@arm.com{ 3527653Sgene.wu@arm.com // We might have unserialized something or switched CPUs, so make 3537653Sgene.wu@arm.com // sure to re-read the misc regs. 3547653Sgene.wu@arm.com miscRegValid = false; 3557653Sgene.wu@arm.com} 3567653Sgene.wu@arm.com 3577439Sdam.sunwoo@arm.comvoid 3587728SAli.Saidi@ARM.comTLB::takeOverFrom(BaseTLB *_otlb) 3597728SAli.Saidi@ARM.com{ 3608902Sandreas.hansson@arm.com TLB *otlb = dynamic_cast<TLB*>(_otlb); 3617728SAli.Saidi@ARM.com /* Make sure we actually have a valid type */ 3627728SAli.Saidi@ARM.com if (otlb) { 3637404SAli.Saidi@ARM.com _attr = otlb->_attr; 3649015Sandreas.hansson@arm.com haveLPAE = otlb->haveLPAE; 3657404SAli.Saidi@ARM.com directToStage2 = otlb->directToStage2; 3669152Satgutier@umich.edu stage2Req = otlb->stage2Req; 3679152Satgutier@umich.edu bootUncacheability = otlb->bootUncacheability; 3689152Satgutier@umich.edu 3697404SAli.Saidi@ARM.com /* Sync the stage2 MMU if they exist in both 3707404SAli.Saidi@ARM.com * the old CPU and the new 3717404SAli.Saidi@ARM.com */ 3727404SAli.Saidi@ARM.com if (!isStage2 && 3737404SAli.Saidi@ARM.com stage2Tlb && otlb->stage2Tlb) { 3747404SAli.Saidi@ARM.com stage2Tlb->takeOverFrom(otlb->stage2Tlb); 3757439Sdam.sunwoo@arm.com } 3767437Sdam.sunwoo@arm.com } else { 3777728SAli.Saidi@ARM.com panic("Incompatible TLB type!"); 3787728SAli.Saidi@ARM.com } 3797728SAli.Saidi@ARM.com} 3808832SAli.Saidi@ARM.com 3818832SAli.Saidi@ARM.comvoid 3828832SAli.Saidi@ARM.comTLB::serialize(ostream &os) 3837404SAli.Saidi@ARM.com{ 3847404SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 3857404SAli.Saidi@ARM.com 3867404SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 3877404SAli.Saidi@ARM.com SERIALIZE_SCALAR(haveLPAE); 3887404SAli.Saidi@ARM.com SERIALIZE_SCALAR(directToStage2); 3897404SAli.Saidi@ARM.com SERIALIZE_SCALAR(stage2Req); 3907404SAli.Saidi@ARM.com SERIALIZE_SCALAR(bootUncacheability); 3917404SAli.Saidi@ARM.com 3927404SAli.Saidi@ARM.com int num_entries = size; 3937404SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 3949152Satgutier@umich.edu for(int i = 0; i < size; i++){ 3959152Satgutier@umich.edu nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 3967733SAli.Saidi@ARM.com table[i].serialize(os); 3977748SAli.Saidi@ARM.com } 3988922Swilliam.wang@arm.com} 3998922Swilliam.wang@arm.com 4007404SAli.Saidi@ARM.comvoid 4017404SAli.Saidi@ARM.comTLB::unserialize(Checkpoint *cp, const string §ion) 4028733Sgeoffrey.blake@arm.com{ 4037404SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 4047404SAli.Saidi@ARM.com 4057439Sdam.sunwoo@arm.com UNSERIALIZE_SCALAR(_attr); 4067439Sdam.sunwoo@arm.com UNSERIALIZE_SCALAR(haveLPAE); 4077404SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(directToStage2); 4087404SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(stage2Req); 4097404SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(bootUncacheability); 4107404SAli.Saidi@ARM.com 4117437Sdam.sunwoo@arm.com int num_entries; 4127437Sdam.sunwoo@arm.com UNSERIALIZE_SCALAR(num_entries); 4137404SAli.Saidi@ARM.com for(int i = 0; i < min(size, num_entries); i++){ 4147404SAli.Saidi@ARM.com table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 4157437Sdam.sunwoo@arm.com } 4167437Sdam.sunwoo@arm.com} 4177404SAli.Saidi@ARM.com 4187728SAli.Saidi@ARM.comvoid 4197728SAli.Saidi@ARM.comTLB::regStats() 4207728SAli.Saidi@ARM.com{ 4217404SAli.Saidi@ARM.com instHits 4227728SAli.Saidi@ARM.com .name(name() + ".inst_hits") 4237404SAli.Saidi@ARM.com .desc("ITB inst hits") 4247404SAli.Saidi@ARM.com ; 4257404SAli.Saidi@ARM.com 4267404SAli.Saidi@ARM.com instMisses 4277404SAli.Saidi@ARM.com .name(name() + ".inst_misses") 4287404SAli.Saidi@ARM.com .desc("ITB inst misses") 4297404SAli.Saidi@ARM.com ; 430 431 instAccesses 432 .name(name() + ".inst_accesses") 433 .desc("ITB inst accesses") 434 ; 435 436 readHits 437 .name(name() + ".read_hits") 438 .desc("DTB read hits") 439 ; 440 441 readMisses 442 .name(name() + ".read_misses") 443 .desc("DTB read misses") 444 ; 445 446 readAccesses 447 .name(name() + ".read_accesses") 448 .desc("DTB read accesses") 449 ; 450 451 writeHits 452 .name(name() + ".write_hits") 453 .desc("DTB write hits") 454 ; 455 456 writeMisses 457 .name(name() + ".write_misses") 458 .desc("DTB write misses") 459 ; 460 461 writeAccesses 462 .name(name() + ".write_accesses") 463 .desc("DTB write accesses") 464 ; 465 466 hits 467 .name(name() + ".hits") 468 .desc("DTB hits") 469 ; 470 471 misses 472 .name(name() + ".misses") 473 .desc("DTB misses") 474 ; 475 476 accesses 477 .name(name() + ".accesses") 478 .desc("DTB accesses") 479 ; 480 481 flushTlb 482 .name(name() + ".flush_tlb") 483 .desc("Number of times complete TLB was flushed") 484 ; 485 486 flushTlbMva 487 .name(name() + ".flush_tlb_mva") 488 .desc("Number of times TLB was flushed by MVA") 489 ; 490 491 flushTlbMvaAsid 492 .name(name() + ".flush_tlb_mva_asid") 493 .desc("Number of times TLB was flushed by MVA & ASID") 494 ; 495 496 flushTlbAsid 497 .name(name() + ".flush_tlb_asid") 498 .desc("Number of times TLB was flushed by ASID") 499 ; 500 501 flushedEntries 502 .name(name() + ".flush_entries") 503 .desc("Number of entries that have been flushed from TLB") 504 ; 505 506 alignFaults 507 .name(name() + ".align_faults") 508 .desc("Number of TLB faults due to alignment restrictions") 509 ; 510 511 prefetchFaults 512 .name(name() + ".prefetch_faults") 513 .desc("Number of TLB faults due to prefetch") 514 ; 515 516 domainFaults 517 .name(name() + ".domain_faults") 518 .desc("Number of TLB faults due to domain restrictions") 519 ; 520 521 permsFaults 522 .name(name() + ".perms_faults") 523 .desc("Number of TLB faults due to permissions restrictions") 524 ; 525 526 instAccesses = instHits + instMisses; 527 readAccesses = readHits + readMisses; 528 writeAccesses = writeHits + writeMisses; 529 hits = readHits + writeHits + instHits; 530 misses = readMisses + writeMisses + instMisses; 531 accesses = readAccesses + writeAccesses + instAccesses; 532} 533 534Fault 535TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 536 Translation *translation, bool &delay, bool timing) 537{ 538 updateMiscReg(tc); 539 Addr vaddr_tainted = req->getVaddr(); 540 Addr vaddr = 0; 541 if (aarch64) 542 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 543 else 544 vaddr = vaddr_tainted; 545 uint32_t flags = req->getFlags(); 546 547 bool is_fetch = (mode == Execute); 548 bool is_write = (mode == Write); 549 550 if (!is_fetch) { 551 assert(flags & MustBeOne); 552 if (sctlr.a || !(flags & AllowUnaligned)) { 553 if (vaddr & mask(flags & AlignmentMask)) { 554 // LPAE is always disabled in SE mode 555 return new DataAbort(vaddr_tainted, 556 TlbEntry::DomainType::NoAccess, is_write, 557 ArmFault::AlignmentFault, isStage2, 558 ArmFault::VmsaTran); 559 } 560 } 561 } 562 563 Addr paddr; 564 Process *p = tc->getProcessPtr(); 565 566 if (!p->pTable->translate(vaddr, paddr)) 567 return Fault(new GenericPageTableFault(vaddr_tainted)); 568 req->setPaddr(paddr); 569 570 return NoFault; 571} 572 573Fault 574TLB::trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain) 575{ 576 return NoFault; 577} 578 579Fault 580TLB::walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 581 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level) 582{ 583 return NoFault; 584} 585 586Fault 587TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 588{ 589 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 590 uint32_t flags = req->getFlags(); 591 bool is_fetch = (mode == Execute); 592 bool is_write = (mode == Write); 593 bool is_priv = isPriv && !(flags & UserMode); 594 595 // Get the translation type from the actuall table entry 596 ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran 597 : ArmFault::VmsaTran; 598 599 // If this is the second stage of translation and the request is for a 600 // stage 1 page table walk then we need to check the HCR.PTW bit. This 601 // allows us to generate a fault if the request targets an area marked 602 // as a device or strongly ordered. 603 if (isStage2 && req->isPTWalk() && hcr.ptw && 604 (te->mtype != TlbEntry::MemoryType::Normal)) { 605 return new DataAbort(vaddr, te->domain, is_write, 606 ArmFault::PermissionLL + te->lookupLevel, 607 isStage2, tranMethod); 608 } 609 610 // Generate an alignment fault for unaligned data accesses to device or 611 // strongly ordered memory 612 if (!is_fetch) { 613 if (te->mtype != TlbEntry::MemoryType::Normal) { 614 if (vaddr & mask(flags & AlignmentMask)) { 615 alignFaults++; 616 return new DataAbort(vaddr, TlbEntry::DomainType::NoAccess, is_write, 617 ArmFault::AlignmentFault, isStage2, 618 tranMethod); 619 } 620 } 621 } 622 623 if (te->nonCacheable) { 624 // Prevent prefetching from I/O devices. 625 if (req->isPrefetch()) { 626 // Here we can safely use the fault status for the short 627 // desc. format in all cases 628 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable, 629 isStage2, tranMethod); 630 } 631 } 632 633 if (!te->longDescFormat) { 634 switch ((dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) { 635 case 0: 636 domainFaults++; 637 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x" 638 " domain: %#x write:%d\n", dacr, 639 static_cast<uint8_t>(te->domain), is_write); 640 if (is_fetch) 641 return new PrefetchAbort(vaddr, 642 ArmFault::DomainLL + te->lookupLevel, 643 isStage2, tranMethod); 644 else 645 return new DataAbort(vaddr, te->domain, is_write, 646 ArmFault::DomainLL + te->lookupLevel, 647 isStage2, tranMethod); 648 case 1: 649 // Continue with permissions check 650 break; 651 case 2: 652 panic("UNPRED domain\n"); 653 case 3: 654 return NoFault; 655 } 656 } 657 658 // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits 659 uint8_t ap = te->longDescFormat ? te->ap << 1 : te->ap; 660 uint8_t hap = te->hap; 661 662 if (sctlr.afe == 1 || te->longDescFormat) 663 ap |= 1; 664 665 bool abt; 666 bool isWritable = true; 667 // If this is a stage 2 access (eg for reading stage 1 page table entries) 668 // then don't perform the AP permissions check, we stil do the HAP check 669 // below. 670 if (isStage2) { 671 abt = false; 672 } else { 673 switch (ap) { 674 case 0: 675 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", 676 (int)sctlr.rs); 677 if (!sctlr.xp) { 678 switch ((int)sctlr.rs) { 679 case 2: 680 abt = is_write; 681 break; 682 case 1: 683 abt = is_write || !is_priv; 684 break; 685 case 0: 686 case 3: 687 default: 688 abt = true; 689 break; 690 } 691 } else { 692 abt = true; 693 } 694 break; 695 case 1: 696 abt = !is_priv; 697 break; 698 case 2: 699 abt = !is_priv && is_write; 700 isWritable = is_priv; 701 break; 702 case 3: 703 abt = false; 704 break; 705 case 4: 706 panic("UNPRED premissions\n"); 707 case 5: 708 abt = !is_priv || is_write; 709 isWritable = false; 710 break; 711 case 6: 712 case 7: 713 abt = is_write; 714 isWritable = false; 715 break; 716 default: 717 panic("Unknown permissions %#x\n", ap); 718 } 719 } 720 721 bool hapAbt = is_write ? !(hap & 2) : !(hap & 1); 722 bool xn = te->xn || (isWritable && sctlr.wxn) || 723 (ap == 3 && sctlr.uwxn && is_priv); 724 if (is_fetch && (abt || xn || 725 (te->longDescFormat && te->pxn && !is_priv) || 726 (isSecure && te->ns && scr.sif))) { 727 permsFaults++; 728 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " 729 "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n", 730 ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe); 731 return new PrefetchAbort(vaddr, 732 ArmFault::PermissionLL + te->lookupLevel, 733 isStage2, tranMethod); 734 } else if (abt | hapAbt) { 735 permsFaults++; 736 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 737 " write:%d\n", ap, is_priv, is_write); 738 return new DataAbort(vaddr, te->domain, is_write, 739 ArmFault::PermissionLL + te->lookupLevel, 740 isStage2 | !abt, tranMethod); 741 } 742 return NoFault; 743} 744 745 746Fault 747TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 748 ThreadContext *tc) 749{ 750 assert(aarch64); 751 752 Addr vaddr_tainted = req->getVaddr(); 753 Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 754 755 uint32_t flags = req->getFlags(); 756 bool is_fetch = (mode == Execute); 757 bool is_write = (mode == Write); 758 bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 759 760 updateMiscReg(tc, curTranType); 761 762 // If this is the second stage of translation and the request is for a 763 // stage 1 page table walk then we need to check the HCR.PTW bit. This 764 // allows us to generate a fault if the request targets an area marked 765 // as a device or strongly ordered. 766 if (isStage2 && req->isPTWalk() && hcr.ptw && 767 (te->mtype != TlbEntry::MemoryType::Normal)) { 768 return new DataAbort(vaddr_tainted, te->domain, is_write, 769 ArmFault::PermissionLL + te->lookupLevel, 770 isStage2, ArmFault::LpaeTran); 771 } 772 773 // Generate an alignment fault for unaligned accesses to device or 774 // strongly ordered memory 775 if (!is_fetch) { 776 if (te->mtype != TlbEntry::MemoryType::Normal) { 777 if (vaddr & mask(flags & AlignmentMask)) { 778 alignFaults++; 779 return new DataAbort(vaddr_tainted, 780 TlbEntry::DomainType::NoAccess, is_write, 781 ArmFault::AlignmentFault, isStage2, 782 ArmFault::LpaeTran); 783 } 784 } 785 } 786 787 if (te->nonCacheable) { 788 // Prevent prefetching from I/O devices. 789 if (req->isPrefetch()) { 790 // Here we can safely use the fault status for the short 791 // desc. format in all cases 792 return new PrefetchAbort(vaddr_tainted, 793 ArmFault::PrefetchUncacheable, 794 isStage2, ArmFault::LpaeTran); 795 } 796 } 797 798 uint8_t ap = 0x3 & (te->ap); // 2-bit access protection field 799 bool grant = false; 800 801 uint8_t xn = te->xn; 802 uint8_t pxn = te->pxn; 803 bool r = !is_write && !is_fetch; 804 bool w = is_write; 805 bool x = is_fetch; 806 DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 807 "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 808 809 if (isStage2) { 810 panic("Virtualization in AArch64 state is not supported yet"); 811 } else { 812 switch (aarch64EL) { 813 case EL0: 814 { 815 uint8_t perm = (ap << 2) | (xn << 1) | pxn; 816 switch (perm) { 817 case 0: 818 case 1: 819 case 8: 820 case 9: 821 grant = x; 822 break; 823 case 4: 824 case 5: 825 grant = r || w || (x && !sctlr.wxn); 826 break; 827 case 6: 828 case 7: 829 grant = r || w; 830 break; 831 case 12: 832 case 13: 833 grant = r || x; 834 break; 835 case 14: 836 case 15: 837 grant = r; 838 break; 839 default: 840 grant = false; 841 } 842 } 843 break; 844 case EL1: 845 { 846 uint8_t perm = (ap << 2) | (xn << 1) | pxn; 847 switch (perm) { 848 case 0: 849 case 2: 850 grant = r || w || (x && !sctlr.wxn); 851 break; 852 case 1: 853 case 3: 854 case 4: 855 case 5: 856 case 6: 857 case 7: 858 // regions that are writeable at EL0 should not be 859 // executable at EL1 860 grant = r || w; 861 break; 862 case 8: 863 case 10: 864 case 12: 865 case 14: 866 grant = r || x; 867 break; 868 case 9: 869 case 11: 870 case 13: 871 case 15: 872 grant = r; 873 break; 874 default: 875 grant = false; 876 } 877 } 878 break; 879 case EL2: 880 case EL3: 881 { 882 uint8_t perm = (ap & 0x2) | xn; 883 switch (perm) { 884 case 0: 885 grant = r || w || (x && !sctlr.wxn) ; 886 break; 887 case 1: 888 grant = r || w; 889 break; 890 case 2: 891 grant = r || x; 892 break; 893 case 3: 894 grant = r; 895 break; 896 default: 897 grant = false; 898 } 899 } 900 break; 901 } 902 } 903 904 if (!grant) { 905 if (is_fetch) { 906 permsFaults++; 907 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. " 908 "AP:%d priv:%d write:%d ns:%d sif:%d " 909 "sctlr.afe: %d\n", 910 ap, is_priv, is_write, te->ns, scr.sif, sctlr.afe); 911 // Use PC value instead of vaddr because vaddr might be aligned to 912 // cache line and should not be the address reported in FAR 913 return new PrefetchAbort(req->getPC(), 914 ArmFault::PermissionLL + te->lookupLevel, 915 isStage2, ArmFault::LpaeTran); 916 } else { 917 permsFaults++; 918 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d " 919 "priv:%d write:%d\n", ap, is_priv, is_write); 920 return new DataAbort(vaddr_tainted, te->domain, is_write, 921 ArmFault::PermissionLL + te->lookupLevel, 922 isStage2, ArmFault::LpaeTran); 923 } 924 } 925 926 return NoFault; 927} 928 929Fault 930TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 931 Translation *translation, bool &delay, bool timing, 932 TLB::ArmTranslationType tranType, bool functional) 933{ 934 // No such thing as a functional timing access 935 assert(!(timing && functional)); 936 937 updateMiscReg(tc, tranType); 938 939 Addr vaddr_tainted = req->getVaddr(); 940 Addr vaddr = 0; 941 if (aarch64) 942 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 943 else 944 vaddr = vaddr_tainted; 945 uint32_t flags = req->getFlags(); 946 947 bool is_fetch = (mode == Execute); 948 bool is_write = (mode == Write); 949 bool long_desc_format = aarch64 || (haveLPAE && ttbcr.eae); 950 ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran 951 : ArmFault::VmsaTran; 952 953 req->setAsid(asid); 954 955 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", 956 isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 957 958 DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 959 "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2, 960 scr, sctlr, flags, tranType); 961 962 // Generate an alignment fault for unaligned PC 963 if (aarch64 && is_fetch && (req->getPC() & mask(2))) { 964 return new PCAlignmentFault(req->getPC()); 965 } 966 967 // If this is a clrex instruction, provide a PA of 0 with no fault 968 // This will force the monitor to set the tracked address to 0 969 // a bit of a hack but this effectively clrears this processors monitor 970 if (flags & Request::CLEAR_LL){ 971 // @todo: check implications of security extensions 972 req->setPaddr(0); 973 req->setFlags(Request::UNCACHEABLE); 974 req->setFlags(Request::CLEAR_LL); 975 return NoFault; 976 } 977 if ((req->isInstFetch() && (!sctlr.i)) || 978 ((!req->isInstFetch()) && (!sctlr.c))){ 979 req->setFlags(Request::UNCACHEABLE); 980 } 981 if (!is_fetch) { 982 assert(flags & MustBeOne); 983 if (sctlr.a || !(flags & AllowUnaligned)) { 984 if (vaddr & mask(flags & AlignmentMask)) { 985 alignFaults++; 986 return new DataAbort(vaddr_tainted, 987 TlbEntry::DomainType::NoAccess, is_write, 988 ArmFault::AlignmentFault, isStage2, 989 tranMethod); 990 } 991 } 992 } 993 994 // If guest MMU is off or hcr.vm=0 go straight to stage2 995 if ((isStage2 && !hcr.vm) || (!isStage2 && !sctlr.m)) { 996 997 req->setPaddr(vaddr); 998 // When the MMU is off the security attribute corresponds to the 999 // security state of the processor 1000 if (isSecure) 1001 req->setFlags(Request::SECURE); 1002 1003 // @todo: double check this (ARM ARM issue C B3.2.1) 1004 if (long_desc_format || sctlr.tre == 0) { 1005 req->setFlags(Request::UNCACHEABLE); 1006 } else { 1007 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 1008 req->setFlags(Request::UNCACHEABLE); 1009 } 1010 1011 // Set memory attributes 1012 TlbEntry temp_te; 1013 temp_te.ns = !isSecure; 1014 if (isStage2 || hcr.dc == 0 || isSecure || 1015 (isHyp && !(tranType & S1CTran))) { 1016 1017 temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal 1018 : TlbEntry::MemoryType::StronglyOrdered; 1019 temp_te.innerAttrs = 0x0; 1020 temp_te.outerAttrs = 0x0; 1021 temp_te.shareable = true; 1022 temp_te.outerShareable = true; 1023 } else { 1024 temp_te.mtype = TlbEntry::MemoryType::Normal; 1025 temp_te.innerAttrs = 0x3; 1026 temp_te.outerAttrs = 0x3; 1027 temp_te.shareable = false; 1028 temp_te.outerShareable = false; 1029 } 1030 temp_te.setAttributes(long_desc_format); 1031 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: " 1032 "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", 1033 temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs, 1034 isStage2); 1035 setAttr(temp_te.attributes); 1036 1037 return trickBoxCheck(req, mode, TlbEntry::DomainType::NoAccess); 1038 } 1039 1040 DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n", 1041 isStage2 ? "IPA" : "VA", vaddr_tainted, asid); 1042 // Translation enabled 1043 1044 TlbEntry *te = NULL; 1045 TlbEntry mergeTe; 1046 Fault fault = getResultTe(&te, req, tc, mode, translation, timing, 1047 functional, &mergeTe); 1048 // only proceed if we have a valid table entry 1049 if ((te == NULL) && (fault == NoFault)) delay = true; 1050 1051 // If we have the table entry transfer some of the attributes to the 1052 // request that triggered the translation 1053 if (te != NULL) { 1054 // Set memory attributes 1055 DPRINTF(TLBVerbose, 1056 "Setting memory attributes: shareable: %d, innerAttrs: %d, " 1057 "outerAttrs: %d, mtype: %d, isStage2: %d\n", 1058 te->shareable, te->innerAttrs, te->outerAttrs, 1059 static_cast<uint8_t>(te->mtype), isStage2); 1060 setAttr(te->attributes); 1061 if (te->nonCacheable) { 1062 req->setFlags(Request::UNCACHEABLE); 1063 } 1064 1065 if (!bootUncacheability && 1066 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) { 1067 req->setFlags(Request::UNCACHEABLE); 1068 } 1069 1070 req->setPaddr(te->pAddr(vaddr)); 1071 if (isSecure && !te->ns) { 1072 req->setFlags(Request::SECURE); 1073 } 1074 if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 1075 (te->mtype != TlbEntry::MemoryType::Normal)) { 1076 // Unaligned accesses to Device memory should always cause an 1077 // abort regardless of sctlr.a 1078 alignFaults++; 1079 return new DataAbort(vaddr_tainted, 1080 TlbEntry::DomainType::NoAccess, is_write, 1081 ArmFault::AlignmentFault, isStage2, 1082 tranMethod); 1083 } 1084 1085 // Check for a trickbox generated address fault 1086 if (fault == NoFault) { 1087 fault = trickBoxCheck(req, mode, te->domain); 1088 } 1089 } 1090 1091 // Generate Illegal Inst Set State fault if IL bit is set in CPSR 1092 if (fault == NoFault) { 1093 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1094 if (aarch64 && is_fetch && cpsr.il == 1) { 1095 return new IllegalInstSetStateFault(); 1096 } 1097 } 1098 1099 return fault; 1100} 1101 1102Fault 1103TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 1104 TLB::ArmTranslationType tranType) 1105{ 1106 updateMiscReg(tc, tranType); 1107 1108 if (directToStage2) { 1109 assert(stage2Tlb); 1110 return stage2Tlb->translateAtomic(req, tc, mode, tranType); 1111 } 1112 1113 bool delay = false; 1114 Fault fault; 1115 if (FullSystem) 1116 fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 1117 else 1118 fault = translateSe(req, tc, mode, NULL, delay, false); 1119 assert(!delay); 1120 return fault; 1121} 1122 1123Fault 1124TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 1125 TLB::ArmTranslationType tranType) 1126{ 1127 updateMiscReg(tc, tranType); 1128 1129 if (directToStage2) { 1130 assert(stage2Tlb); 1131 return stage2Tlb->translateFunctional(req, tc, mode, tranType); 1132 } 1133 1134 bool delay = false; 1135 Fault fault; 1136 if (FullSystem) 1137 fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 1138 else 1139 fault = translateSe(req, tc, mode, NULL, delay, false); 1140 assert(!delay); 1141 return fault; 1142} 1143 1144Fault 1145TLB::translateTiming(RequestPtr req, ThreadContext *tc, 1146 Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 1147{ 1148 updateMiscReg(tc, tranType); 1149 1150 if (directToStage2) { 1151 assert(stage2Tlb); 1152 return stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 1153 } 1154 1155 assert(translation); 1156 1157 return translateComplete(req, tc, translation, mode, tranType, isStage2); 1158} 1159 1160Fault 1161TLB::translateComplete(RequestPtr req, ThreadContext *tc, 1162 Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 1163 bool callFromS2) 1164{ 1165 bool delay = false; 1166 Fault fault; 1167 if (FullSystem) 1168 fault = translateFs(req, tc, mode, translation, delay, true, tranType); 1169 else 1170 fault = translateSe(req, tc, mode, translation, delay, true); 1171 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 1172 NoFault); 1173 // If we have a translation, and we're not in the middle of doing a stage 1174 // 2 translation tell the translation that we've either finished or its 1175 // going to take a while. By not doing this when we're in the middle of a 1176 // stage 2 translation we prevent marking the translation as delayed twice, 1177 // one when the translation starts and again when the stage 1 translation 1178 // completes. 1179 if (translation && (callFromS2 || !stage2Req || req->hasPaddr() || fault != NoFault)) { 1180 if (!delay) 1181 translation->finish(fault, req, tc, mode); 1182 else 1183 translation->markDelayed(); 1184 } 1185 return fault; 1186} 1187 1188BaseMasterPort* 1189TLB::getMasterPort() 1190{ 1191 return &tableWalker->getMasterPort("port"); 1192} 1193 1194DmaPort& 1195TLB::getWalkerPort() 1196{ 1197 return tableWalker->getWalkerPort(); 1198} 1199 1200void 1201TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) 1202{ 1203 // check if the regs have changed, or the translation mode is different. 1204 // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle 1205 // one type of translation anyway 1206 if (miscRegValid && ((tranType == curTranType) || isStage2)) { 1207 return; 1208 } 1209 1210 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 1211 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1212 // Dependencies: SCR/SCR_EL3, CPSR 1213 isSecure = inSecureState(tc); 1214 isSecure &= (tranType & HypMode) == 0; 1215 isSecure &= (tranType & S1S2NsTran) == 0; 1216 aarch64 = !cpsr.width; 1217 if (aarch64) { // AArch64 1218 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; 1219 switch (aarch64EL) { 1220 case EL0: 1221 case EL1: 1222 { 1223 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1224 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 1225 uint64_t ttbr_asid = ttbcr.a1 ? 1226 tc->readMiscReg(MISCREG_TTBR1_EL1) : 1227 tc->readMiscReg(MISCREG_TTBR0_EL1); 1228 asid = bits(ttbr_asid, 1229 (haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48); 1230 } 1231 break; 1232 case EL2: 1233 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); 1234 ttbcr = tc->readMiscReg(MISCREG_TCR_EL2); 1235 asid = -1; 1236 break; 1237 case EL3: 1238 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 1239 ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 1240 asid = -1; 1241 break; 1242 } 1243 scr = tc->readMiscReg(MISCREG_SCR_EL3); 1244 isPriv = aarch64EL != EL0; 1245 // @todo: modify this behaviour to support Virtualization in 1246 // AArch64 1247 vmid = 0; 1248 isHyp = false; 1249 directToStage2 = false; 1250 stage2Req = false; 1251 } else { // AArch32 1252 sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc, 1253 !isSecure)); 1254 ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc, 1255 !isSecure)); 1256 scr = tc->readMiscReg(MISCREG_SCR); 1257 isPriv = cpsr.mode != MODE_USER; 1258 if (haveLPAE && ttbcr.eae) { 1259 // Long-descriptor translation table format in use 1260 uint64_t ttbr_asid = tc->readMiscReg( 1261 flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1 1262 : MISCREG_TTBR0, 1263 tc, !isSecure)); 1264 asid = bits(ttbr_asid, 55, 48); 1265 } else { 1266 // Short-descriptor translation table format in use 1267 CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked( 1268 MISCREG_CONTEXTIDR, tc,!isSecure)); 1269 asid = context_id.asid; 1270 } 1271 prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc, 1272 !isSecure)); 1273 nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc, 1274 !isSecure)); 1275 dacr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_DACR, tc, 1276 !isSecure)); 1277 hcr = tc->readMiscReg(MISCREG_HCR); 1278 1279 if (haveVirtualization) { 1280 vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); 1281 isHyp = cpsr.mode == MODE_HYP; 1282 isHyp |= tranType & HypMode; 1283 isHyp &= (tranType & S1S2NsTran) == 0; 1284 isHyp &= (tranType & S1CTran) == 0; 1285 if (isHyp) { 1286 sctlr = tc->readMiscReg(MISCREG_HSCTLR); 1287 } 1288 // Work out if we should skip the first stage of translation and go 1289 // directly to stage 2. This value is cached so we don't have to 1290 // compute it for every translation. 1291 stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure && 1292 !(tranType & S1CTran); 1293 directToStage2 = stage2Req && !sctlr.m; 1294 } else { 1295 vmid = 0; 1296 stage2Req = false; 1297 isHyp = false; 1298 directToStage2 = false; 1299 } 1300 } 1301 miscRegValid = true; 1302 curTranType = tranType; 1303} 1304 1305Fault 1306TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1307 Translation *translation, bool timing, bool functional, 1308 bool is_secure, TLB::ArmTranslationType tranType) 1309{ 1310 bool is_fetch = (mode == Execute); 1311 bool is_write = (mode == Write); 1312 1313 Addr vaddr_tainted = req->getVaddr(); 1314 Addr vaddr = 0; 1315 ExceptionLevel target_el = aarch64 ? aarch64EL : EL1; 1316 if (aarch64) { 1317 vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el); 1318 } else { 1319 vaddr = vaddr_tainted; 1320 } 1321 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 1322 if (*te == NULL) { 1323 if (req->isPrefetch()) { 1324 // if the request is a prefetch don't attempt to fill the TLB or go 1325 // any further with the memory access (here we can safely use the 1326 // fault status for the short desc. format in all cases) 1327 prefetchFaults++; 1328 return new PrefetchAbort(vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); 1329 } 1330 1331 if (is_fetch) 1332 instMisses++; 1333 else if (is_write) 1334 writeMisses++; 1335 else 1336 readMisses++; 1337 1338 // start translation table walk, pass variables rather than 1339 // re-retreaving in table walker for speed 1340 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n", 1341 vaddr_tainted, asid, vmid); 1342 Fault fault; 1343 fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode, 1344 translation, timing, functional, is_secure, 1345 tranType); 1346 // for timing mode, return and wait for table walk, 1347 if (timing || fault != NoFault) { 1348 return fault; 1349 } 1350 1351 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 1352 if (!*te) 1353 printTlb(); 1354 assert(*te); 1355 } else { 1356 if (is_fetch) 1357 instHits++; 1358 else if (is_write) 1359 writeHits++; 1360 else 1361 readHits++; 1362 } 1363 return NoFault; 1364} 1365 1366Fault 1367TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1368 Translation *translation, bool timing, bool functional, 1369 TlbEntry *mergeTe) 1370{ 1371 Fault fault; 1372 TlbEntry *s1Te = NULL; 1373 1374 Addr vaddr_tainted = req->getVaddr(); 1375 1376 // Get the stage 1 table entry 1377 fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 1378 isSecure, curTranType); 1379 // only proceed if we have a valid table entry 1380 if ((s1Te != NULL) && (fault == NoFault)) { 1381 // Check stage 1 permissions before checking stage 2 1382 if (aarch64) 1383 fault = checkPermissions64(s1Te, req, mode, tc); 1384 else 1385 fault = checkPermissions(s1Te, req, mode); 1386 if (stage2Req & (fault == NoFault)) { 1387 Stage2LookUp *s2Lookup = new Stage2LookUp(this, stage2Tlb, *s1Te, 1388 req, translation, mode, timing, functional, curTranType); 1389 fault = s2Lookup->getTe(tc, mergeTe); 1390 if (s2Lookup->isComplete()) { 1391 *te = mergeTe; 1392 // We've finished with the lookup so delete it 1393 delete s2Lookup; 1394 } else { 1395 // The lookup hasn't completed, so we can't delete it now. We 1396 // get round this by asking the object to self delete when the 1397 // translation is complete. 1398 s2Lookup->setSelfDelete(); 1399 } 1400 } else { 1401 // This case deals with an S1 hit (or bypass), followed by 1402 // an S2 hit-but-perms issue 1403 if (isStage2) { 1404 DPRINTF(TLBVerbose, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n", 1405 vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0, fault); 1406 if (fault != NoFault) { 1407 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1408 armFault->annotate(ArmFault::S1PTW, false); 1409 armFault->annotate(ArmFault::OVA, vaddr_tainted); 1410 } 1411 } 1412 *te = s1Te; 1413 } 1414 } 1415 return fault; 1416} 1417 1418ArmISA::TLB * 1419ArmTLBParams::create() 1420{ 1421 return new ArmISA::TLB(this); 1422} 1423