system.cc revision 8885:52bbd95b31ed
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#include <iostream> 44 45#include "arch/arm/system.hh" 46#include "base/loader/object_file.hh" 47#include "base/loader/symtab.hh" 48#include "cpu/thread_context.hh" 49#include "mem/physical.hh" 50#include "mem/fs_translating_port_proxy.hh" 51 52using namespace std; 53using namespace Linux; 54 55ArmSystem::ArmSystem(Params *p) 56 : System(p), bootldr(NULL) 57{ 58 if ((p->boot_loader == "") != (p->boot_loader_mem == NULL)) 59 fatal("If boot_loader is specifed, memory to load it must be also.\n"); 60 61 if (p->boot_loader != "") { 62 bootldr = createObjectFile(p->boot_loader); 63 64 if (!bootldr) 65 fatal("Could not read bootloader: %s\n", p->boot_loader); 66 67 bootldr->loadGlobalSymbols(debugSymbolTable); 68 69 } 70 debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk"); 71} 72 73void 74ArmSystem::initState() 75{ 76 // Moved from the constructor to here since it relies on the 77 // address map being resolved in the interconnect 78 79 // Call the initialisation of the super class 80 System::initState(); 81 82 const Params* p = params(); 83 84 if (bootldr) { 85 bootldr->loadSections(physProxy); 86 87 uint8_t jump_to_bl[] = 88 { 89 0x07, 0xf0, 0xa0, 0xe1 // branch to r7 90 }; 91 physProxy.writeBlob(0x0, jump_to_bl, sizeof(jump_to_bl)); 92 93 inform("Using bootloader at address %#x\n", bootldr->entryPoint()); 94 95 // Put the address of the boot loader into r7 so we know 96 // where to branch to after the reset fault 97 // All other values needed by the boot loader to know what to do 98 if (!p->gic_cpu_addr || !p->flags_addr) 99 fatal("gic_cpu_addr && flags_addr must be set with bootloader\n"); 100 101 for (int i = 0; i < threadContexts.size(); i++) { 102 threadContexts[i]->setIntReg(3, kernelEntry & loadAddrMask); 103 threadContexts[i]->setIntReg(4, params()->gic_cpu_addr); 104 threadContexts[i]->setIntReg(5, params()->flags_addr); 105 threadContexts[i]->setIntReg(7, bootldr->entryPoint()); 106 } 107 } else { 108 // Set the initial PC to be at start of the kernel code 109 threadContexts[0]->pcState(kernelEntry & loadAddrMask); 110 } 111 112 for (int i = 0; i < threadContexts.size(); i++) { 113 if (p->midr_regval) { 114 threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR, 115 p->midr_regval); 116 } 117 } 118} 119 120ArmSystem::~ArmSystem() 121{ 122 if (debugPrintkEvent) 123 delete debugPrintkEvent; 124} 125 126 127ArmSystem * 128ArmSystemParams::create() 129{ 130 return new ArmSystem(this); 131} 132