registers.hh revision 6328 
1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__
32#define __ARCH_ARM_REGFILE_REGFILE_HH__
33
34#include "arch/arm/types.hh"
35#include "arch/arm/misc_regfile.hh"
36#include "sim/faults.hh"
37
38class Checkpoint;
39class EventManager;
40class ThreadContext;
41
42namespace ArmISA
43{
44    enum FPControlRegNums {
45       FIR = NumFloatArchRegs,
46       FCCR,
47       FEXR,
48       FENR,
49       FCSR
50    };
51
52    enum FCSRBits {
53        Inexact = 1,
54        Underflow,
55        Overflow,
56        DivideByZero,
57        Invalid,
58        Unimplemented
59    };
60
61    enum FCSRFields {
62        Flag_Field = 1,
63        Enable_Field = 6,
64        Cause_Field = 11
65    };
66
67    enum MiscIntRegNums {
68        zero_reg = NumIntArchRegs,
69        addr_reg,
70
71        rhi,
72        rlo,
73
74        r8_fiq,    /* FIQ mode register bank */
75        r9_fiq,
76        r10_fiq,
77        r11_fiq,
78        r12_fiq,
79
80        r13_fiq,   /* FIQ mode SP and LR */
81        r14_fiq,
82
83        r13_irq,   /* IRQ mode SP and LR */
84        r14_irq,
85
86        r13_svc,   /* SVC mode SP and LR */
87        r14_svc,
88
89        r13_undef, /* UNDEF mode SP and LR */
90        r14_undef,
91
92        r13_abt,   /* ABT mode SP and LR */
93        r14_abt
94    };
95
96    void copyRegs(ThreadContext *src, ThreadContext *dest);
97
98    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
99
100} // namespace ArmISA
101
102#endif
103