registers.hh revision 6328
16019SN/A/* 26019SN/A * Copyright (c) 2007-2008 The Florida State University 37102SN/A * All rights reserved. 47102SN/A * 57102SN/A * Redistribution and use in source and binary forms, with or without 67102SN/A * modification, are permitted provided that the following conditions are 77102SN/A * met: redistributions of source code must retain the above copyright 87102SN/A * notice, this list of conditions and the following disclaimer; 97102SN/A * redistributions in binary form must reproduce the above copyright 107102SN/A * notice, this list of conditions and the following disclaimer in the 117102SN/A * documentation and/or other materials provided with the distribution; 127102SN/A * neither the name of the copyright holders nor the names of its 137102SN/A * contributors may be used to endorse or promote products derived from 147102SN/A * this software without specific prior written permission. 157102SN/A * 166019SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019SN/A * 286019SN/A * Authors: Stephen Hines 296019SN/A */ 306019SN/A 316019SN/A#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__ 326019SN/A#define __ARCH_ARM_REGFILE_REGFILE_HH__ 336019SN/A 346019SN/A#include "arch/arm/types.hh" 356019SN/A#include "arch/arm/misc_regfile.hh" 366019SN/A#include "sim/faults.hh" 376019SN/A 386019SN/Aclass Checkpoint; 396019SN/Aclass EventManager; 406019SN/Aclass ThreadContext; 417102SN/A 426019SN/Anamespace ArmISA 437102SN/A{ 447104SN/A enum FPControlRegNums { 457104SN/A FIR = NumFloatArchRegs, 467141Sgblack@eecs.umich.edu FCCR, 477104SN/A FEXR, 487141Sgblack@eecs.umich.edu FENR, 497141Sgblack@eecs.umich.edu FCSR 507126Sgblack@eecs.umich.edu }; 517124Sgblack@eecs.umich.edu 527104SN/A enum FCSRBits { 537125Sgblack@eecs.umich.edu Inexact = 1, 547104SN/A Underflow, 557141Sgblack@eecs.umich.edu Overflow, 567141Sgblack@eecs.umich.edu DivideByZero, 577141Sgblack@eecs.umich.edu Invalid, 587104SN/A Unimplemented 597104SN/A }; 607135Sgblack@eecs.umich.edu 617154Sgblack@eecs.umich.edu enum FCSRFields { 627104SN/A Flag_Field = 1, 637104SN/A Enable_Field = 6, 647154Sgblack@eecs.umich.edu Cause_Field = 11 657104SN/A }; 667104SN/A 677107SN/A enum MiscIntRegNums { 687107SN/A zero_reg = NumIntArchRegs, 697107SN/A addr_reg, 707107SN/A 717107SN/A rhi, 727107SN/A rlo, 737107SN/A 747107SN/A r8_fiq, /* FIQ mode register bank */ 757107SN/A r9_fiq, 767107SN/A r10_fiq, 777107SN/A r11_fiq, 787107SN/A r12_fiq, 797107SN/A 807107SN/A r13_fiq, /* FIQ mode SP and LR */ 817107SN/A r14_fiq, 827107SN/A 837107SN/A r13_irq, /* IRQ mode SP and LR */ 847107SN/A r14_irq, 857136Sgblack@eecs.umich.edu 867136Sgblack@eecs.umich.edu r13_svc, /* SVC mode SP and LR */ 877107SN/A r14_svc, 887107SN/A 897107SN/A r13_undef, /* UNDEF mode SP and LR */ 907107SN/A r14_undef, 917107SN/A 927107SN/A r13_abt, /* ABT mode SP and LR */ 937107SN/A r14_abt 947107SN/A }; 957107SN/A 967107SN/A void copyRegs(ThreadContext *src, ThreadContext *dest); 977107SN/A 987107SN/A void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 997107SN/A 1007107SN/A} // namespace ArmISA 1017107SN/A 1027107SN/A#endif 1037107SN/A