miscregs.hh revision 7783
16242Sgblack@eecs.umich.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146242Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156242Sgblack@eecs.umich.edu * All rights reserved. 166242Sgblack@eecs.umich.edu * 176242Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186242Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196242Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216242Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236242Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246242Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256242Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266242Sgblack@eecs.umich.edu * this software without specific prior written permission. 276242Sgblack@eecs.umich.edu * 286242Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296242Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306242Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316242Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326242Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336242Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346242Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356242Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366242Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376242Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386242Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396242Sgblack@eecs.umich.edu * 406242Sgblack@eecs.umich.edu * Authors: Gabe Black 416242Sgblack@eecs.umich.edu */ 426242Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MISCREGS_HH__ 436242Sgblack@eecs.umich.edu#define __ARCH_ARM_MISCREGS_HH__ 446242Sgblack@eecs.umich.edu 456242Sgblack@eecs.umich.edu#include "base/bitunion.hh" 466242Sgblack@eecs.umich.edu 476242Sgblack@eecs.umich.edunamespace ArmISA 486242Sgblack@eecs.umich.edu{ 496242Sgblack@eecs.umich.edu enum ConditionCode { 506242Sgblack@eecs.umich.edu COND_EQ = 0, 516242Sgblack@eecs.umich.edu COND_NE, // 1 526242Sgblack@eecs.umich.edu COND_CS, // 2 536242Sgblack@eecs.umich.edu COND_CC, // 3 546242Sgblack@eecs.umich.edu COND_MI, // 4 556242Sgblack@eecs.umich.edu COND_PL, // 5 566242Sgblack@eecs.umich.edu COND_VS, // 6 576242Sgblack@eecs.umich.edu COND_VC, // 7 586242Sgblack@eecs.umich.edu COND_HI, // 8 596242Sgblack@eecs.umich.edu COND_LS, // 9 606242Sgblack@eecs.umich.edu COND_GE, // 10 616242Sgblack@eecs.umich.edu COND_LT, // 11 626242Sgblack@eecs.umich.edu COND_GT, // 12 636242Sgblack@eecs.umich.edu COND_LE, // 13 646242Sgblack@eecs.umich.edu COND_AL, // 14 657111Sgblack@eecs.umich.edu COND_UC // 15 666242Sgblack@eecs.umich.edu }; 676242Sgblack@eecs.umich.edu 686242Sgblack@eecs.umich.edu enum MiscRegIndex { 696242Sgblack@eecs.umich.edu MISCREG_CPSR = 0, 707408Sgblack@eecs.umich.edu MISCREG_ITSTATE, 716735Sgblack@eecs.umich.edu MISCREG_SPSR, 726242Sgblack@eecs.umich.edu MISCREG_SPSR_FIQ, 736242Sgblack@eecs.umich.edu MISCREG_SPSR_IRQ, 746242Sgblack@eecs.umich.edu MISCREG_SPSR_SVC, 756723Sgblack@eecs.umich.edu MISCREG_SPSR_MON, 766242Sgblack@eecs.umich.edu MISCREG_SPSR_UND, 776242Sgblack@eecs.umich.edu MISCREG_SPSR_ABT, 786261Sgblack@eecs.umich.edu MISCREG_FPSR, 796403Sgblack@eecs.umich.edu MISCREG_FPSID, 806403Sgblack@eecs.umich.edu MISCREG_FPSCR, 817783SGiacomo.Gabrielli@arm.com MISCREG_FPSCR_QC, // Cumulative saturation flag 827783SGiacomo.Gabrielli@arm.com MISCREG_FPSCR_EXC, // Cumulative FP exception flags 836403Sgblack@eecs.umich.edu MISCREG_FPEXC, 847325Sgblack@eecs.umich.edu MISCREG_MVFR0, 857325Sgblack@eecs.umich.edu MISCREG_MVFR1, 867400SAli.Saidi@ARM.com MISCREG_SCTLR_RST, 877350SAli.Saidi@ARM.com MISCREG_SEV_MAILBOX, 887259Sgblack@eecs.umich.edu 897259Sgblack@eecs.umich.edu // CP15 registers 907259Sgblack@eecs.umich.edu MISCREG_CP15_START, 917259Sgblack@eecs.umich.edu MISCREG_SCTLR = MISCREG_CP15_START, 927264Sgblack@eecs.umich.edu MISCREG_DCCISW, 937267Sgblack@eecs.umich.edu MISCREG_DCCIMVAC, 947285Sgblack@eecs.umich.edu MISCREG_DCCMVAC, 957265Sgblack@eecs.umich.edu MISCREG_CONTEXTIDR, 967266Sgblack@eecs.umich.edu MISCREG_TPIDRURW, 977266Sgblack@eecs.umich.edu MISCREG_TPIDRURO, 987266Sgblack@eecs.umich.edu MISCREG_TPIDRPRW, 997268Sgblack@eecs.umich.edu MISCREG_CP15ISB, 1007272Sgblack@eecs.umich.edu MISCREG_CP15DSB, 1017272Sgblack@eecs.umich.edu MISCREG_CP15DMB, 1027271Sgblack@eecs.umich.edu MISCREG_CPACR, 1037273Sgblack@eecs.umich.edu MISCREG_CLIDR, 1047287Sgblack@eecs.umich.edu MISCREG_CCSIDR, 1057287Sgblack@eecs.umich.edu MISCREG_CSSELR, 1067274Sgblack@eecs.umich.edu MISCREG_ICIALLUIS, 1077275Sgblack@eecs.umich.edu MISCREG_ICIALLU, 1087276Sgblack@eecs.umich.edu MISCREG_ICIMVAU, 1097286Sgblack@eecs.umich.edu MISCREG_BPIMVA, 1107297Sgblack@eecs.umich.edu MISCREG_BPIALLIS, 1117297Sgblack@eecs.umich.edu MISCREG_BPIALL, 1127298Sgblack@eecs.umich.edu MISCREG_MIDR, 1137352Sgblack@eecs.umich.edu MISCREG_TTBR0, 1147352Sgblack@eecs.umich.edu MISCREG_TTBR1, 1157354Sgblack@eecs.umich.edu MISCREG_TLBTR, 1167353Sgblack@eecs.umich.edu MISCREG_DACR, 1177355Sgblack@eecs.umich.edu MISCREG_TLBIALLIS, 1187355Sgblack@eecs.umich.edu MISCREG_TLBIMVAIS, 1197355Sgblack@eecs.umich.edu MISCREG_TLBIASIDIS, 1207355Sgblack@eecs.umich.edu MISCREG_TLBIMVAAIS, 1217355Sgblack@eecs.umich.edu MISCREG_ITLBIALL, 1227355Sgblack@eecs.umich.edu MISCREG_ITLBIMVA, 1237355Sgblack@eecs.umich.edu MISCREG_ITLBIASID, 1247355Sgblack@eecs.umich.edu MISCREG_DTLBIALL, 1257355Sgblack@eecs.umich.edu MISCREG_DTLBIMVA, 1267355Sgblack@eecs.umich.edu MISCREG_DTLBIASID, 1277355Sgblack@eecs.umich.edu MISCREG_TLBIALL, 1287355Sgblack@eecs.umich.edu MISCREG_TLBIMVA, 1297355Sgblack@eecs.umich.edu MISCREG_TLBIASID, 1307355Sgblack@eecs.umich.edu MISCREG_TLBIMVAA, 1317362Sgblack@eecs.umich.edu MISCREG_DFSR, 1327362Sgblack@eecs.umich.edu MISCREG_IFSR, 1337362Sgblack@eecs.umich.edu MISCREG_DFAR, 1347362Sgblack@eecs.umich.edu MISCREG_IFAR, 1357390Sgblack@eecs.umich.edu MISCREG_MPIDR, 1367404SAli.Saidi@ARM.com MISCREG_PRRR, 1377404SAli.Saidi@ARM.com MISCREG_NMRR, 1387404SAli.Saidi@ARM.com MISCREG_TTBCR, 1397404SAli.Saidi@ARM.com MISCREG_ID_PFR0, 1407406SAli.Saidi@ARM.com MISCREG_CTR, 1417406SAli.Saidi@ARM.com MISCREG_SCR, 1427406SAli.Saidi@ARM.com MISCREG_SDER, 1437436Sdam.sunwoo@arm.com MISCREG_PAR, 1447436Sdam.sunwoo@arm.com MISCREG_V2PCWPR, 1457436Sdam.sunwoo@arm.com MISCREG_V2PCWPW, 1467436Sdam.sunwoo@arm.com MISCREG_V2PCWUR, 1477436Sdam.sunwoo@arm.com MISCREG_V2PCWUW, 1487436Sdam.sunwoo@arm.com MISCREG_V2POWPR, 1497436Sdam.sunwoo@arm.com MISCREG_V2POWPW, 1507436Sdam.sunwoo@arm.com MISCREG_V2POWUR, 1517436Sdam.sunwoo@arm.com MISCREG_V2POWUW, 1527583SAli.Saidi@arm.com MISCREG_ID_MMFR0, 1537583SAli.Saidi@arm.com MISCREG_ACTLR, 1547583SAli.Saidi@arm.com MISCREG_PMCR, 1557583SAli.Saidi@arm.com MISCREG_PMCCNTR, 1567583SAli.Saidi@arm.com MISCREG_PMCNTENSET, 1577583SAli.Saidi@arm.com MISCREG_PMCNTENCLR, 1587583SAli.Saidi@arm.com MISCREG_PMOVSR, 1597583SAli.Saidi@arm.com MISCREG_PMSWINC, 1607583SAli.Saidi@arm.com MISCREG_PMSELR, 1617583SAli.Saidi@arm.com MISCREG_PMCEID0, 1627583SAli.Saidi@arm.com MISCREG_PMCEID1, 1637583SAli.Saidi@arm.com MISCREG_PMC_OTHER, 1647583SAli.Saidi@arm.com MISCREG_PMXEVCNTR, 1657583SAli.Saidi@arm.com MISCREG_PMUSERENR, 1667583SAli.Saidi@arm.com MISCREG_PMINTENSET, 1677583SAli.Saidi@arm.com MISCREG_PMINTENCLR, 1687259Sgblack@eecs.umich.edu MISCREG_CP15_UNIMP_START, 1697406SAli.Saidi@ARM.com MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 1707259Sgblack@eecs.umich.edu MISCREG_ID_PFR1, 1717259Sgblack@eecs.umich.edu MISCREG_ID_DFR0, 1727259Sgblack@eecs.umich.edu MISCREG_ID_AFR0, 1737259Sgblack@eecs.umich.edu MISCREG_ID_MMFR1, 1747259Sgblack@eecs.umich.edu MISCREG_ID_MMFR2, 1757259Sgblack@eecs.umich.edu MISCREG_ID_MMFR3, 1767259Sgblack@eecs.umich.edu MISCREG_ID_ISAR0, 1777259Sgblack@eecs.umich.edu MISCREG_ID_ISAR1, 1787259Sgblack@eecs.umich.edu MISCREG_ID_ISAR2, 1797259Sgblack@eecs.umich.edu MISCREG_ID_ISAR3, 1807259Sgblack@eecs.umich.edu MISCREG_ID_ISAR4, 1817259Sgblack@eecs.umich.edu MISCREG_ID_ISAR5, 1827259Sgblack@eecs.umich.edu MISCREG_AIDR, 1837259Sgblack@eecs.umich.edu MISCREG_ADFSR, 1847259Sgblack@eecs.umich.edu MISCREG_AIFSR, 1857259Sgblack@eecs.umich.edu MISCREG_DCIMVAC, 1867259Sgblack@eecs.umich.edu MISCREG_DCISW, 1877259Sgblack@eecs.umich.edu MISCREG_MCCSW, 1887259Sgblack@eecs.umich.edu MISCREG_DCCMVAU, 1897351Sgblack@eecs.umich.edu MISCREG_NSACR, 1907351Sgblack@eecs.umich.edu MISCREG_VBAR, 1917351Sgblack@eecs.umich.edu MISCREG_MVBAR, 1927351Sgblack@eecs.umich.edu MISCREG_ISR, 1937351Sgblack@eecs.umich.edu MISCREG_FCEIDR, 1947351Sgblack@eecs.umich.edu 1957259Sgblack@eecs.umich.edu 1967259Sgblack@eecs.umich.edu MISCREG_CP15_END, 1977259Sgblack@eecs.umich.edu 1987259Sgblack@eecs.umich.edu // Dummy indices 1997259Sgblack@eecs.umich.edu MISCREG_NOP = MISCREG_CP15_END, 2007259Sgblack@eecs.umich.edu MISCREG_RAZ, 2017259Sgblack@eecs.umich.edu 2026735Sgblack@eecs.umich.edu NUM_MISCREGS 2036261Sgblack@eecs.umich.edu }; 2046261Sgblack@eecs.umich.edu 2057259Sgblack@eecs.umich.edu MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 2067259Sgblack@eecs.umich.edu unsigned crm, unsigned opc2); 2077259Sgblack@eecs.umich.edu 2086261Sgblack@eecs.umich.edu const char * const miscRegName[NUM_MISCREGS] = { 2097408Sgblack@eecs.umich.edu "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 2107259Sgblack@eecs.umich.edu "spsr_mon", "spsr_und", "spsr_abt", 2117783SGiacomo.Gabrielli@arm.com "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 2127783SGiacomo.Gabrielli@arm.com "mvfr0", "mvfr1", 2137400SAli.Saidi@ARM.com "sctlr_rst", "sev_mailbox", 2147285Sgblack@eecs.umich.edu "sctlr", "dccisw", "dccimvac", "dccmvac", 2157267Sgblack@eecs.umich.edu "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 2167287Sgblack@eecs.umich.edu "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 2177287Sgblack@eecs.umich.edu "clidr", "ccsidr", "csselr", 2187297Sgblack@eecs.umich.edu "icialluis", "iciallu", "icimvau", 2197297Sgblack@eecs.umich.edu "bpimva", "bpiallis", "bpiall", 2207355Sgblack@eecs.umich.edu "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 2217355Sgblack@eecs.umich.edu "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 2227355Sgblack@eecs.umich.edu "itlbiall", "itlbimva", "itlbiasid", 2237355Sgblack@eecs.umich.edu "dtlbiall", "dtlbimva", "dtlbiasid", 2247355Sgblack@eecs.umich.edu "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 2257390Sgblack@eecs.umich.edu "dfsr", "ifsr", "dfar", "ifar", "mpidr", 2267436Sdam.sunwoo@arm.com "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 2277436Sdam.sunwoo@arm.com "scr", "sder", "par", 2287436Sdam.sunwoo@arm.com "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 2297436Sdam.sunwoo@arm.com "v2powpr", "v2powpw", "v2powur", "v2powuw", 2307583SAli.Saidi@arm.com "id_mmfr0","actlr", "pmcr", "pmcntr", 2317583SAli.Saidi@arm.com "pmcntenset", "pmcntenclr", "pmovsr", 2327583SAli.Saidi@arm.com "pmswinc", "pmselr", "pmceid0", 2337583SAli.Saidi@arm.com "pmceid1", "pmc_other", "pmxevcntr", 2347583SAli.Saidi@arm.com "pmuserenr", "pmintenset", "pmintenclr", 2357583SAli.Saidi@arm.com // Unimplemented below 2367406SAli.Saidi@ARM.com "tcmtr", 2377404SAli.Saidi@ARM.com "id_pfr1", "id_dfr0", "id_afr0", 2387583SAli.Saidi@arm.com "id_mmfr1", "id_mmfr2", "id_mmfr3", 2397259Sgblack@eecs.umich.edu "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 2407583SAli.Saidi@arm.com "aidr", 2417362Sgblack@eecs.umich.edu "adfsr", "aifsr", 2427297Sgblack@eecs.umich.edu "dcimvac", "dcisw", "mccsw", 2437272Sgblack@eecs.umich.edu "dccmvau", 2447406SAli.Saidi@ARM.com "nsacr", 2457404SAli.Saidi@ARM.com "vbar", "mvbar", "isr", "fceidr", 2467259Sgblack@eecs.umich.edu "nop", "raz" 2476242Sgblack@eecs.umich.edu }; 2486242Sgblack@eecs.umich.edu 2496242Sgblack@eecs.umich.edu BitUnion32(CPSR) 2506242Sgblack@eecs.umich.edu Bitfield<31> n; 2516242Sgblack@eecs.umich.edu Bitfield<30> z; 2526242Sgblack@eecs.umich.edu Bitfield<29> c; 2536242Sgblack@eecs.umich.edu Bitfield<28> v; 2546242Sgblack@eecs.umich.edu Bitfield<27> q; 2556735Sgblack@eecs.umich.edu Bitfield<26,25> it1; 2566242Sgblack@eecs.umich.edu Bitfield<24> j; 2576242Sgblack@eecs.umich.edu Bitfield<19, 16> ge; 2586735Sgblack@eecs.umich.edu Bitfield<15,10> it2; 2596242Sgblack@eecs.umich.edu Bitfield<9> e; 2606242Sgblack@eecs.umich.edu Bitfield<8> a; 2616242Sgblack@eecs.umich.edu Bitfield<7> i; 2626242Sgblack@eecs.umich.edu Bitfield<6> f; 2636242Sgblack@eecs.umich.edu Bitfield<5> t; 2646242Sgblack@eecs.umich.edu Bitfield<4, 0> mode; 2656242Sgblack@eecs.umich.edu EndBitUnion(CPSR) 2666735Sgblack@eecs.umich.edu 2677408Sgblack@eecs.umich.edu BitUnion8(ITSTATE) 2687762SAli.Saidi@ARM.com /* Note that the split (cond, mask) below is not as in ARM ARM. 2697762SAli.Saidi@ARM.com * But it is more convenient for simulation. The condition 2707762SAli.Saidi@ARM.com * is always the concatenation of the top 3 bits and the next bit, 2717762SAli.Saidi@ARM.com * which applies when one of the bottom 4 bits is set. 2727762SAli.Saidi@ARM.com * Refer to predecoder.cc for the use case. 2737762SAli.Saidi@ARM.com */ 2747408Sgblack@eecs.umich.edu Bitfield<7, 4> cond; 2757408Sgblack@eecs.umich.edu Bitfield<3, 0> mask; 2767408Sgblack@eecs.umich.edu // Bitfields for moving to/from CPSR 2777408Sgblack@eecs.umich.edu Bitfield<7, 2> top6; 2787408Sgblack@eecs.umich.edu Bitfield<1, 0> bottom2; 2797408Sgblack@eecs.umich.edu EndBitUnion(ITSTATE) 2807408Sgblack@eecs.umich.edu 2816750Sgblack@eecs.umich.edu // This mask selects bits of the CPSR that actually go in the CondCodes 2826750Sgblack@eecs.umich.edu // integer register to allow renaming. 2836750Sgblack@eecs.umich.edu static const uint32_t CondCodesMask = 0xF80F0000; 2846750Sgblack@eecs.umich.edu 2856735Sgblack@eecs.umich.edu BitUnion32(SCTLR) 2867360Sgblack@eecs.umich.edu Bitfield<31> ie; // Instruction endianness 2876735Sgblack@eecs.umich.edu Bitfield<30> te; // Thumb Exception Enable 2886735Sgblack@eecs.umich.edu Bitfield<29> afe; // Access flag enable 2896735Sgblack@eecs.umich.edu Bitfield<28> tre; // TEX Remap bit 2906735Sgblack@eecs.umich.edu Bitfield<27> nmfi;// Non-maskable fast interrupts enable 2916735Sgblack@eecs.umich.edu Bitfield<25> ee; // Exception Endianness bit 2926735Sgblack@eecs.umich.edu Bitfield<24> ve; // Interrupt vectors enable 2937406SAli.Saidi@ARM.com Bitfield<23> xp; // Extended page table enable bit 2946735Sgblack@eecs.umich.edu Bitfield<22> u; // Alignment (now unused) 2956735Sgblack@eecs.umich.edu Bitfield<21> fi; // Fast interrupts configuration enable 2967360Sgblack@eecs.umich.edu Bitfield<19> dz; // Divide by Zero fault enable bit 2976735Sgblack@eecs.umich.edu Bitfield<18> rao2;// Read as one 2987360Sgblack@eecs.umich.edu Bitfield<17> br; // Background region bit 2996735Sgblack@eecs.umich.edu Bitfield<16> rao3;// Read as one 3006735Sgblack@eecs.umich.edu Bitfield<14> rr; // Round robin cache replacement 3016735Sgblack@eecs.umich.edu Bitfield<13> v; // Base address for exception vectors 3026735Sgblack@eecs.umich.edu Bitfield<12> i; // instruction cache enable 3036735Sgblack@eecs.umich.edu Bitfield<11> z; // branch prediction enable bit 3046735Sgblack@eecs.umich.edu Bitfield<10> sw; // Enable swp/swpb 3057406SAli.Saidi@ARM.com Bitfield<9,8> rs; // deprecated protection bits 3066735Sgblack@eecs.umich.edu Bitfield<6,3> rao4;// Read as one 3076735Sgblack@eecs.umich.edu Bitfield<7> b; // Endianness support (unused) 3086735Sgblack@eecs.umich.edu Bitfield<2> c; // Cache enable bit 3096735Sgblack@eecs.umich.edu Bitfield<1> a; // Alignment fault checking 3106735Sgblack@eecs.umich.edu Bitfield<0> m; // MMU enable bit 3116735Sgblack@eecs.umich.edu EndBitUnion(SCTLR) 3127320Sgblack@eecs.umich.edu 3137320Sgblack@eecs.umich.edu BitUnion32(CPACR) 3147320Sgblack@eecs.umich.edu Bitfield<1, 0> cp0; 3157320Sgblack@eecs.umich.edu Bitfield<3, 2> cp1; 3167320Sgblack@eecs.umich.edu Bitfield<5, 4> cp2; 3177320Sgblack@eecs.umich.edu Bitfield<7, 6> cp3; 3187320Sgblack@eecs.umich.edu Bitfield<9, 8> cp4; 3197320Sgblack@eecs.umich.edu Bitfield<11, 10> cp5; 3207320Sgblack@eecs.umich.edu Bitfield<13, 12> cp6; 3217320Sgblack@eecs.umich.edu Bitfield<15, 14> cp7; 3227320Sgblack@eecs.umich.edu Bitfield<17, 16> cp8; 3237320Sgblack@eecs.umich.edu Bitfield<19, 18> cp9; 3247320Sgblack@eecs.umich.edu Bitfield<21, 20> cp10; 3257320Sgblack@eecs.umich.edu Bitfield<23, 22> cp11; 3267320Sgblack@eecs.umich.edu Bitfield<25, 24> cp12; 3277320Sgblack@eecs.umich.edu Bitfield<27, 26> cp13; 3287320Sgblack@eecs.umich.edu Bitfield<30> d32dis; 3297320Sgblack@eecs.umich.edu Bitfield<31> asedis; 3307320Sgblack@eecs.umich.edu EndBitUnion(CPACR) 3317362Sgblack@eecs.umich.edu 3327362Sgblack@eecs.umich.edu BitUnion32(FSR) 3337362Sgblack@eecs.umich.edu Bitfield<3, 0> fsLow; 3347362Sgblack@eecs.umich.edu Bitfield<7, 4> domain; 3357362Sgblack@eecs.umich.edu Bitfield<10> fsHigh; 3367362Sgblack@eecs.umich.edu Bitfield<11> wnr; 3377362Sgblack@eecs.umich.edu Bitfield<12> ext; 3387362Sgblack@eecs.umich.edu EndBitUnion(FSR) 3397376Sgblack@eecs.umich.edu 3407376Sgblack@eecs.umich.edu BitUnion32(FPSCR) 3417376Sgblack@eecs.umich.edu Bitfield<0> ioc; 3427376Sgblack@eecs.umich.edu Bitfield<1> dzc; 3437376Sgblack@eecs.umich.edu Bitfield<2> ofc; 3447376Sgblack@eecs.umich.edu Bitfield<3> ufc; 3457376Sgblack@eecs.umich.edu Bitfield<4> ixc; 3467376Sgblack@eecs.umich.edu Bitfield<7> idc; 3477376Sgblack@eecs.umich.edu Bitfield<8> ioe; 3487376Sgblack@eecs.umich.edu Bitfield<9> dze; 3497376Sgblack@eecs.umich.edu Bitfield<10> ofe; 3507376Sgblack@eecs.umich.edu Bitfield<11> ufe; 3517376Sgblack@eecs.umich.edu Bitfield<12> ixe; 3527376Sgblack@eecs.umich.edu Bitfield<15> ide; 3537376Sgblack@eecs.umich.edu Bitfield<18, 16> len; 3547376Sgblack@eecs.umich.edu Bitfield<21, 20> stride; 3557376Sgblack@eecs.umich.edu Bitfield<23, 22> rMode; 3567376Sgblack@eecs.umich.edu Bitfield<24> fz; 3577376Sgblack@eecs.umich.edu Bitfield<25> dn; 3587376Sgblack@eecs.umich.edu Bitfield<26> ahp; 3597376Sgblack@eecs.umich.edu Bitfield<27> qc; 3607376Sgblack@eecs.umich.edu Bitfield<28> v; 3617376Sgblack@eecs.umich.edu Bitfield<29> c; 3627376Sgblack@eecs.umich.edu Bitfield<30> z; 3637376Sgblack@eecs.umich.edu Bitfield<31> n; 3647376Sgblack@eecs.umich.edu EndBitUnion(FPSCR) 3657383Sgblack@eecs.umich.edu 3667643Sgblack@eecs.umich.edu // This mask selects bits of the FPSCR that actually go in the FpCondCodes 3677643Sgblack@eecs.umich.edu // integer register to allow renaming. 3687783SGiacomo.Gabrielli@arm.com static const uint32_t FpCondCodesMask = 0xF0000000; 3697783SGiacomo.Gabrielli@arm.com // This mask selects the cumulative FP exception flags of the FPSCR. 3707783SGiacomo.Gabrielli@arm.com static const uint32_t FpscrExcMask = 0x0000009F; 3717783SGiacomo.Gabrielli@arm.com // This mask selects the cumulative saturation flag of the FPSCR. 3727783SGiacomo.Gabrielli@arm.com static const uint32_t FpscrQcMask = 0x08000000; 3737643Sgblack@eecs.umich.edu 3747640Sgblack@eecs.umich.edu BitUnion32(FPEXC) 3757640Sgblack@eecs.umich.edu Bitfield<31> ex; 3767640Sgblack@eecs.umich.edu Bitfield<30> en; 3777640Sgblack@eecs.umich.edu Bitfield<29, 0> subArchDefined; 3787640Sgblack@eecs.umich.edu EndBitUnion(FPEXC) 3797640Sgblack@eecs.umich.edu 3807383Sgblack@eecs.umich.edu BitUnion32(MVFR0) 3817383Sgblack@eecs.umich.edu Bitfield<3, 0> advSimdRegisters; 3827383Sgblack@eecs.umich.edu Bitfield<7, 4> singlePrecision; 3837383Sgblack@eecs.umich.edu Bitfield<11, 8> doublePrecision; 3847383Sgblack@eecs.umich.edu Bitfield<15, 12> vfpExceptionTrapping; 3857383Sgblack@eecs.umich.edu Bitfield<19, 16> divide; 3867383Sgblack@eecs.umich.edu Bitfield<23, 20> squareRoot; 3877383Sgblack@eecs.umich.edu Bitfield<27, 24> shortVectors; 3887383Sgblack@eecs.umich.edu Bitfield<31, 28> roundingModes; 3897383Sgblack@eecs.umich.edu EndBitUnion(MVFR0) 3907383Sgblack@eecs.umich.edu 3917383Sgblack@eecs.umich.edu BitUnion32(MVFR1) 3927383Sgblack@eecs.umich.edu Bitfield<3, 0> flushToZero; 3937383Sgblack@eecs.umich.edu Bitfield<7, 4> defaultNaN; 3947383Sgblack@eecs.umich.edu Bitfield<11, 8> advSimdLoadStore; 3957383Sgblack@eecs.umich.edu Bitfield<15, 12> advSimdInteger; 3967383Sgblack@eecs.umich.edu Bitfield<19, 16> advSimdSinglePrecision; 3977383Sgblack@eecs.umich.edu Bitfield<23, 20> advSimdHalfPrecision; 3987383Sgblack@eecs.umich.edu Bitfield<27, 24> vfpHalfPrecision; 3997383Sgblack@eecs.umich.edu Bitfield<31, 28> raz; 4007383Sgblack@eecs.umich.edu EndBitUnion(MVFR1) 4017404SAli.Saidi@ARM.com 4027404SAli.Saidi@ARM.com BitUnion32(PRRR) 4037404SAli.Saidi@ARM.com Bitfield<1,0> tr0; 4047404SAli.Saidi@ARM.com Bitfield<3,2> tr1; 4057404SAli.Saidi@ARM.com Bitfield<5,4> tr2; 4067404SAli.Saidi@ARM.com Bitfield<7,6> tr3; 4077404SAli.Saidi@ARM.com Bitfield<9,8> tr4; 4087404SAli.Saidi@ARM.com Bitfield<11,10> tr5; 4097404SAli.Saidi@ARM.com Bitfield<13,12> tr6; 4107404SAli.Saidi@ARM.com Bitfield<15,14> tr7; 4117404SAli.Saidi@ARM.com Bitfield<16> ds0; 4127404SAli.Saidi@ARM.com Bitfield<17> ds1; 4137404SAli.Saidi@ARM.com Bitfield<18> ns0; 4147404SAli.Saidi@ARM.com Bitfield<19> ns1; 4157404SAli.Saidi@ARM.com Bitfield<24> nos0; 4167404SAli.Saidi@ARM.com Bitfield<25> nos1; 4177404SAli.Saidi@ARM.com Bitfield<26> nos2; 4187404SAli.Saidi@ARM.com Bitfield<27> nos3; 4197404SAli.Saidi@ARM.com Bitfield<28> nos4; 4207404SAli.Saidi@ARM.com Bitfield<29> nos5; 4217404SAli.Saidi@ARM.com Bitfield<30> nos6; 4227404SAli.Saidi@ARM.com Bitfield<31> nos7; 4237404SAli.Saidi@ARM.com EndBitUnion(PRRR) 4247404SAli.Saidi@ARM.com 4257404SAli.Saidi@ARM.com BitUnion32(NMRR) 4267404SAli.Saidi@ARM.com Bitfield<1,0> ir0; 4277404SAli.Saidi@ARM.com Bitfield<3,2> ir1; 4287404SAli.Saidi@ARM.com Bitfield<5,4> ir2; 4297404SAli.Saidi@ARM.com Bitfield<7,6> ir3; 4307404SAli.Saidi@ARM.com Bitfield<9,8> ir4; 4317404SAli.Saidi@ARM.com Bitfield<11,10> ir5; 4327404SAli.Saidi@ARM.com Bitfield<13,12> ir6; 4337404SAli.Saidi@ARM.com Bitfield<15,14> ir7; 4347404SAli.Saidi@ARM.com Bitfield<17,16> or0; 4357404SAli.Saidi@ARM.com Bitfield<19,18> or1; 4367404SAli.Saidi@ARM.com Bitfield<21,20> or2; 4377404SAli.Saidi@ARM.com Bitfield<23,22> or3; 4387404SAli.Saidi@ARM.com Bitfield<25,24> or4; 4397404SAli.Saidi@ARM.com Bitfield<27,26> or5; 4407404SAli.Saidi@ARM.com Bitfield<29,28> or6; 4417404SAli.Saidi@ARM.com Bitfield<31,30> or7; 4427404SAli.Saidi@ARM.com EndBitUnion(NMRR) 4437404SAli.Saidi@ARM.com 4446242Sgblack@eecs.umich.edu}; 4456242Sgblack@eecs.umich.edu 4466242Sgblack@eecs.umich.edu#endif // __ARCH_ARM_MISCREGS_HH__ 447