miscregs.hh revision 7783 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49    enum ConditionCode {
50        COND_EQ  =   0,
51        COND_NE, //  1
52        COND_CS, //  2
53        COND_CC, //  3
54        COND_MI, //  4
55        COND_PL, //  5
56        COND_VS, //  6
57        COND_VC, //  7
58        COND_HI, //  8
59        COND_LS, //  9
60        COND_GE, // 10
61        COND_LT, // 11
62        COND_GT, // 12
63        COND_LE, // 13
64        COND_AL, // 14
65        COND_UC  // 15
66    };
67
68    enum MiscRegIndex {
69        MISCREG_CPSR = 0,
70        MISCREG_ITSTATE,
71        MISCREG_SPSR,
72        MISCREG_SPSR_FIQ,
73        MISCREG_SPSR_IRQ,
74        MISCREG_SPSR_SVC,
75        MISCREG_SPSR_MON,
76        MISCREG_SPSR_UND,
77        MISCREG_SPSR_ABT,
78        MISCREG_FPSR,
79        MISCREG_FPSID,
80        MISCREG_FPSCR,
81        MISCREG_FPSCR_QC,  // Cumulative saturation flag
82        MISCREG_FPSCR_EXC,  // Cumulative FP exception flags
83        MISCREG_FPEXC,
84        MISCREG_MVFR0,
85        MISCREG_MVFR1,
86        MISCREG_SCTLR_RST,
87        MISCREG_SEV_MAILBOX,
88
89        // CP15 registers
90        MISCREG_CP15_START,
91        MISCREG_SCTLR = MISCREG_CP15_START,
92        MISCREG_DCCISW,
93        MISCREG_DCCIMVAC,
94        MISCREG_DCCMVAC,
95        MISCREG_CONTEXTIDR,
96        MISCREG_TPIDRURW,
97        MISCREG_TPIDRURO,
98        MISCREG_TPIDRPRW,
99        MISCREG_CP15ISB,
100        MISCREG_CP15DSB,
101        MISCREG_CP15DMB,
102        MISCREG_CPACR,
103        MISCREG_CLIDR,
104        MISCREG_CCSIDR,
105        MISCREG_CSSELR,
106        MISCREG_ICIALLUIS,
107        MISCREG_ICIALLU,
108        MISCREG_ICIMVAU,
109        MISCREG_BPIMVA,
110        MISCREG_BPIALLIS,
111        MISCREG_BPIALL,
112        MISCREG_MIDR,
113        MISCREG_TTBR0,
114        MISCREG_TTBR1,
115        MISCREG_TLBTR,
116        MISCREG_DACR,
117        MISCREG_TLBIALLIS,
118        MISCREG_TLBIMVAIS,
119        MISCREG_TLBIASIDIS,
120        MISCREG_TLBIMVAAIS,
121        MISCREG_ITLBIALL,
122        MISCREG_ITLBIMVA,
123        MISCREG_ITLBIASID,
124        MISCREG_DTLBIALL,
125        MISCREG_DTLBIMVA,
126        MISCREG_DTLBIASID,
127        MISCREG_TLBIALL,
128        MISCREG_TLBIMVA,
129        MISCREG_TLBIASID,
130        MISCREG_TLBIMVAA,
131        MISCREG_DFSR,
132        MISCREG_IFSR,
133        MISCREG_DFAR,
134        MISCREG_IFAR,
135        MISCREG_MPIDR,
136        MISCREG_PRRR,
137        MISCREG_NMRR,
138        MISCREG_TTBCR,
139        MISCREG_ID_PFR0,
140        MISCREG_CTR,
141        MISCREG_SCR,
142        MISCREG_SDER,
143        MISCREG_PAR,
144        MISCREG_V2PCWPR,
145        MISCREG_V2PCWPW,
146        MISCREG_V2PCWUR,
147        MISCREG_V2PCWUW,
148        MISCREG_V2POWPR,
149        MISCREG_V2POWPW,
150        MISCREG_V2POWUR,
151        MISCREG_V2POWUW,
152        MISCREG_ID_MMFR0,
153        MISCREG_ACTLR,
154        MISCREG_PMCR,
155        MISCREG_PMCCNTR,
156        MISCREG_PMCNTENSET,
157        MISCREG_PMCNTENCLR,
158        MISCREG_PMOVSR,
159        MISCREG_PMSWINC,
160        MISCREG_PMSELR,
161        MISCREG_PMCEID0,
162        MISCREG_PMCEID1,
163        MISCREG_PMC_OTHER,
164        MISCREG_PMXEVCNTR,
165        MISCREG_PMUSERENR,
166        MISCREG_PMINTENSET,
167        MISCREG_PMINTENCLR,
168        MISCREG_CP15_UNIMP_START,
169        MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
170        MISCREG_ID_PFR1,
171        MISCREG_ID_DFR0,
172        MISCREG_ID_AFR0,
173        MISCREG_ID_MMFR1,
174        MISCREG_ID_MMFR2,
175        MISCREG_ID_MMFR3,
176        MISCREG_ID_ISAR0,
177        MISCREG_ID_ISAR1,
178        MISCREG_ID_ISAR2,
179        MISCREG_ID_ISAR3,
180        MISCREG_ID_ISAR4,
181        MISCREG_ID_ISAR5,
182        MISCREG_AIDR,
183        MISCREG_ADFSR,
184        MISCREG_AIFSR,
185        MISCREG_DCIMVAC,
186        MISCREG_DCISW,
187        MISCREG_MCCSW,
188        MISCREG_DCCMVAU,
189        MISCREG_NSACR,
190        MISCREG_VBAR,
191        MISCREG_MVBAR,
192        MISCREG_ISR,
193        MISCREG_FCEIDR,
194
195
196        MISCREG_CP15_END,
197
198        // Dummy indices
199        MISCREG_NOP = MISCREG_CP15_END,
200        MISCREG_RAZ,
201
202        NUM_MISCREGS
203    };
204
205    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
206                               unsigned crm, unsigned opc2);
207
208    const char * const miscRegName[NUM_MISCREGS] = {
209        "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
210        "spsr_mon", "spsr_und", "spsr_abt",
211        "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
212        "mvfr0", "mvfr1",
213        "sctlr_rst", "sev_mailbox",
214        "sctlr", "dccisw", "dccimvac", "dccmvac",
215        "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
216        "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
217        "clidr", "ccsidr", "csselr",
218        "icialluis", "iciallu", "icimvau",
219        "bpimva", "bpiallis", "bpiall",
220        "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
221        "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
222        "itlbiall", "itlbimva", "itlbiasid",
223        "dtlbiall", "dtlbimva", "dtlbiasid",
224        "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
225        "dfsr", "ifsr", "dfar", "ifar", "mpidr",
226        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr",
227        "scr", "sder", "par",
228        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
229        "v2powpr", "v2powpw", "v2powur", "v2powuw",
230        "id_mmfr0","actlr", "pmcr", "pmcntr",
231        "pmcntenset", "pmcntenclr", "pmovsr",
232        "pmswinc", "pmselr", "pmceid0",
233        "pmceid1", "pmc_other", "pmxevcntr",
234        "pmuserenr", "pmintenset", "pmintenclr",
235         // Unimplemented below
236        "tcmtr",
237        "id_pfr1", "id_dfr0", "id_afr0",
238        "id_mmfr1", "id_mmfr2", "id_mmfr3",
239        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
240        "aidr",
241        "adfsr", "aifsr",
242        "dcimvac", "dcisw", "mccsw",
243        "dccmvau",
244        "nsacr",
245        "vbar", "mvbar", "isr", "fceidr",
246        "nop", "raz"
247    };
248
249    BitUnion32(CPSR)
250        Bitfield<31> n;
251        Bitfield<30> z;
252        Bitfield<29> c;
253        Bitfield<28> v;
254        Bitfield<27> q;
255        Bitfield<26,25> it1;
256        Bitfield<24> j;
257        Bitfield<19, 16> ge;
258        Bitfield<15,10> it2;
259        Bitfield<9> e;
260        Bitfield<8> a;
261        Bitfield<7> i;
262        Bitfield<6> f;
263        Bitfield<5> t;
264        Bitfield<4, 0> mode;
265    EndBitUnion(CPSR)
266
267    BitUnion8(ITSTATE)
268        /* Note that the split (cond, mask) below is not as in ARM ARM.
269         * But it is more convenient for simulation. The condition
270         * is always the concatenation of the top 3 bits and the next bit,
271         * which applies when one of the bottom 4 bits is set.
272         * Refer to predecoder.cc for the use case.
273         */
274        Bitfield<7, 4> cond;
275        Bitfield<3, 0> mask;
276        // Bitfields for moving to/from CPSR
277        Bitfield<7, 2> top6;
278        Bitfield<1, 0> bottom2;
279    EndBitUnion(ITSTATE)
280
281    // This mask selects bits of the CPSR that actually go in the CondCodes
282    // integer register to allow renaming.
283    static const uint32_t CondCodesMask = 0xF80F0000;
284
285    BitUnion32(SCTLR)
286        Bitfield<31> ie;  // Instruction endianness
287        Bitfield<30> te;  // Thumb Exception Enable
288        Bitfield<29> afe; // Access flag enable
289        Bitfield<28> tre; // TEX Remap bit
290        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
291        Bitfield<25> ee;  // Exception Endianness bit
292        Bitfield<24> ve;  // Interrupt vectors enable
293        Bitfield<23> xp; //  Extended page table enable bit
294        Bitfield<22> u;   // Alignment (now unused)
295        Bitfield<21> fi;  // Fast interrupts configuration enable
296        Bitfield<19> dz;  // Divide by Zero fault enable bit
297        Bitfield<18> rao2;// Read as one
298        Bitfield<17> br;  // Background region bit
299        Bitfield<16> rao3;// Read as one
300        Bitfield<14> rr;  // Round robin cache replacement
301        Bitfield<13> v;   // Base address for exception vectors
302        Bitfield<12> i;   // instruction cache enable
303        Bitfield<11> z;   // branch prediction enable bit
304        Bitfield<10> sw;  // Enable swp/swpb
305        Bitfield<9,8> rs;   // deprecated protection bits
306        Bitfield<6,3> rao4;// Read as one
307        Bitfield<7>  b;   // Endianness support (unused)
308        Bitfield<2>  c;   // Cache enable bit
309        Bitfield<1>  a;   // Alignment fault checking
310        Bitfield<0>  m;   // MMU enable bit
311    EndBitUnion(SCTLR)
312
313    BitUnion32(CPACR)
314        Bitfield<1, 0> cp0;
315        Bitfield<3, 2> cp1;
316        Bitfield<5, 4> cp2;
317        Bitfield<7, 6> cp3;
318        Bitfield<9, 8> cp4;
319        Bitfield<11, 10> cp5;
320        Bitfield<13, 12> cp6;
321        Bitfield<15, 14> cp7;
322        Bitfield<17, 16> cp8;
323        Bitfield<19, 18> cp9;
324        Bitfield<21, 20> cp10;
325        Bitfield<23, 22> cp11;
326        Bitfield<25, 24> cp12;
327        Bitfield<27, 26> cp13;
328        Bitfield<30> d32dis;
329        Bitfield<31> asedis;
330    EndBitUnion(CPACR)
331
332    BitUnion32(FSR)
333        Bitfield<3, 0> fsLow;
334        Bitfield<7, 4> domain;
335        Bitfield<10> fsHigh;
336        Bitfield<11> wnr;
337        Bitfield<12> ext;
338    EndBitUnion(FSR)
339
340    BitUnion32(FPSCR)
341        Bitfield<0> ioc;
342        Bitfield<1> dzc;
343        Bitfield<2> ofc;
344        Bitfield<3> ufc;
345        Bitfield<4> ixc;
346        Bitfield<7> idc;
347        Bitfield<8> ioe;
348        Bitfield<9> dze;
349        Bitfield<10> ofe;
350        Bitfield<11> ufe;
351        Bitfield<12> ixe;
352        Bitfield<15> ide;
353        Bitfield<18, 16> len;
354        Bitfield<21, 20> stride;
355        Bitfield<23, 22> rMode;
356        Bitfield<24> fz;
357        Bitfield<25> dn;
358        Bitfield<26> ahp;
359        Bitfield<27> qc;
360        Bitfield<28> v;
361        Bitfield<29> c;
362        Bitfield<30> z;
363        Bitfield<31> n;
364    EndBitUnion(FPSCR)
365
366    // This mask selects bits of the FPSCR that actually go in the FpCondCodes
367    // integer register to allow renaming.
368    static const uint32_t FpCondCodesMask = 0xF0000000;
369    // This mask selects the cumulative FP exception flags of the FPSCR.
370    static const uint32_t FpscrExcMask = 0x0000009F;
371    // This mask selects the cumulative saturation flag of the FPSCR.
372    static const uint32_t FpscrQcMask = 0x08000000;
373
374    BitUnion32(FPEXC)
375        Bitfield<31> ex;
376        Bitfield<30> en;
377        Bitfield<29, 0> subArchDefined;
378    EndBitUnion(FPEXC)
379
380    BitUnion32(MVFR0)
381        Bitfield<3, 0> advSimdRegisters;
382        Bitfield<7, 4> singlePrecision;
383        Bitfield<11, 8> doublePrecision;
384        Bitfield<15, 12> vfpExceptionTrapping;
385        Bitfield<19, 16> divide;
386        Bitfield<23, 20> squareRoot;
387        Bitfield<27, 24> shortVectors;
388        Bitfield<31, 28> roundingModes;
389    EndBitUnion(MVFR0)
390
391    BitUnion32(MVFR1)
392        Bitfield<3, 0> flushToZero;
393        Bitfield<7, 4> defaultNaN;
394        Bitfield<11, 8> advSimdLoadStore;
395        Bitfield<15, 12> advSimdInteger;
396        Bitfield<19, 16> advSimdSinglePrecision;
397        Bitfield<23, 20> advSimdHalfPrecision;
398        Bitfield<27, 24> vfpHalfPrecision;
399        Bitfield<31, 28> raz;
400    EndBitUnion(MVFR1)
401
402    BitUnion32(PRRR)
403       Bitfield<1,0> tr0;
404       Bitfield<3,2> tr1;
405       Bitfield<5,4> tr2;
406       Bitfield<7,6> tr3;
407       Bitfield<9,8> tr4;
408       Bitfield<11,10> tr5;
409       Bitfield<13,12> tr6;
410       Bitfield<15,14> tr7;
411       Bitfield<16> ds0;
412       Bitfield<17> ds1;
413       Bitfield<18> ns0;
414       Bitfield<19> ns1;
415       Bitfield<24> nos0;
416       Bitfield<25> nos1;
417       Bitfield<26> nos2;
418       Bitfield<27> nos3;
419       Bitfield<28> nos4;
420       Bitfield<29> nos5;
421       Bitfield<30> nos6;
422       Bitfield<31> nos7;
423   EndBitUnion(PRRR)
424
425   BitUnion32(NMRR)
426       Bitfield<1,0> ir0;
427       Bitfield<3,2> ir1;
428       Bitfield<5,4> ir2;
429       Bitfield<7,6> ir3;
430       Bitfield<9,8> ir4;
431       Bitfield<11,10> ir5;
432       Bitfield<13,12> ir6;
433       Bitfield<15,14> ir7;
434       Bitfield<17,16> or0;
435       Bitfield<19,18> or1;
436       Bitfield<21,20> or2;
437       Bitfield<23,22> or3;
438       Bitfield<25,24> or4;
439       Bitfield<27,26> or5;
440       Bitfield<29,28> or6;
441       Bitfield<31,30> or7;
442   EndBitUnion(NMRR)
443
444};
445
446#endif // __ARCH_ARM_MISCREGS_HH__
447