system.hh revision 8870:f95c4042f2d0
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_LINUX_SYSTEM_HH__ 44#define __ARCH_ARM_LINUX_SYSTEM_HH__ 45 46#include <string> 47#include <vector> 48 49#include "arch/arm/system.hh" 50#include "kern/linux/events.hh" 51#include "params/LinuxArmSystem.hh" 52 53class LinuxArmSystem : public ArmSystem 54{ 55 public: 56 /** Boilerplate params code */ 57 typedef LinuxArmSystemParams Params; 58 const Params * 59 params() const 60 { 61 return dynamic_cast<const Params *>(_params); 62 } 63 64 LinuxArmSystem(Params *p); 65 ~LinuxArmSystem(); 66 67 void initState(); 68 69 bool adderBootUncacheable(Addr a); 70 71 private: 72#ifndef NDEBUG 73 /** Event to halt the simulator if the kernel calls panic() */ 74 BreakPCEvent *kernelPanicEvent; 75#endif 76 /** 77 * PC based event to skip udelay(<time>) calls and quiesce the 78 * processor for the appropriate amount of time. This is not functionally 79 * required but does speed up simulation. 80 */ 81 Linux::UDelayEvent *uDelaySkipEvent; 82 83 /** Another PC based skip event for const_udelay(). Similar to the udelay 84 * skip, but this function precomputes the first multiply that is done 85 * in the generic case since the parameter is known at compile time. 86 * Thus we need to do some division to get back to us. 87 */ 88 Linux::UDelayEvent *constUDelaySkipEvent; 89 90 /** These variables store addresses of important data structures 91 * that are normaly kept coherent at boot with cache mainetence operations. 92 * Since these operations aren't supported in gem5, we keep them coherent 93 * by making them uncacheable until all processors in the system boot. 94 */ 95 Addr secDataPtrAddr; 96 Addr secDataAddr; 97 Addr penReleaseAddr; 98}; 99 100#endif // __ARCH_ARM_LINUX_SYSTEM_HH__ 101 102