vfp64.isa revision 10037
110037SARM gem5 Developers// -*- mode:c++ -*-
210037SARM gem5 Developers
310037SARM gem5 Developers// Copyright (c) 2012 ARM Limited
410037SARM gem5 Developers// All rights reserved
510037SARM gem5 Developers//
610037SARM gem5 Developers// The license below extends only to copyright in the software and shall
710037SARM gem5 Developers// not be construed as granting a license to any other intellectual
810037SARM gem5 Developers// property including but not limited to intellectual property relating
910037SARM gem5 Developers// to a hardware implementation of the functionality of the software
1010037SARM gem5 Developers// licensed hereunder.  You may use the software subject to the license
1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated
1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software,
1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form.
1410037SARM gem5 Developers//
1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without
1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are
1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright
1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer;
1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright
2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the
2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution;
2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its
2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from
2410037SARM gem5 Developers// this software without specific prior written permission.
2510037SARM gem5 Developers//
2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3710037SARM gem5 Developers//
3810037SARM gem5 Developers// Authors: Thomas Grocutt
3910037SARM gem5 Developers
4010037SARM gem5 Developersdef template AA64FpRegRegOpConstructor {{
4110037SARM gem5 Developers    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
4210037SARM gem5 Developers                                          IntRegIndex _dest, IntRegIndex _op1,
4310037SARM gem5 Developers                                          VfpMicroMode mode)
4410037SARM gem5 Developers        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
4510037SARM gem5 Developers                _dest, _op1, mode)
4610037SARM gem5 Developers    {
4710037SARM gem5 Developers        %(constructor)s;
4810037SARM gem5 Developers        for (int x = 0; x < _numDestRegs; x++) {
4910037SARM gem5 Developers            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
5010037SARM gem5 Developers        }
5110037SARM gem5 Developers    }
5210037SARM gem5 Developers}};
5310037SARM gem5 Developers
5410037SARM gem5 Developersdef template AA64FpRegRegOpConstructor {{
5510037SARM gem5 Developers    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
5610037SARM gem5 Developers                                          IntRegIndex _dest, IntRegIndex _op1,
5710037SARM gem5 Developers                                          VfpMicroMode mode)
5810037SARM gem5 Developers        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
5910037SARM gem5 Developers                _dest, _op1, mode)
6010037SARM gem5 Developers    {
6110037SARM gem5 Developers        %(constructor)s;
6210037SARM gem5 Developers        for (int x = 0; x < _numDestRegs; x++) {
6310037SARM gem5 Developers            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
6410037SARM gem5 Developers        }
6510037SARM gem5 Developers    }
6610037SARM gem5 Developers}};
6710037SARM gem5 Developers
6810037SARM gem5 Developersdef template AA64FpRegImmOpConstructor {{
6910037SARM gem5 Developers    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
7010037SARM gem5 Developers            IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
7110037SARM gem5 Developers        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
7210037SARM gem5 Developers                _dest, _imm, mode)
7310037SARM gem5 Developers    {
7410037SARM gem5 Developers        %(constructor)s;
7510037SARM gem5 Developers        for (int x = 0; x < _numDestRegs; x++) {
7610037SARM gem5 Developers            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
7710037SARM gem5 Developers        }
7810037SARM gem5 Developers    }
7910037SARM gem5 Developers}};
8010037SARM gem5 Developers
8110037SARM gem5 Developersdef template AA64FpRegRegImmOpConstructor {{
8210037SARM gem5 Developers    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
8310037SARM gem5 Developers                                          IntRegIndex _dest,
8410037SARM gem5 Developers                                          IntRegIndex _op1,
8510037SARM gem5 Developers                                          uint64_t _imm,
8610037SARM gem5 Developers                                          VfpMicroMode mode)
8710037SARM gem5 Developers        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
8810037SARM gem5 Developers                         _dest, _op1, _imm, mode)
8910037SARM gem5 Developers    {
9010037SARM gem5 Developers        %(constructor)s;
9110037SARM gem5 Developers        for (int x = 0; x < _numDestRegs; x++) {
9210037SARM gem5 Developers            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
9310037SARM gem5 Developers        }
9410037SARM gem5 Developers    }
9510037SARM gem5 Developers}};
9610037SARM gem5 Developers
9710037SARM gem5 Developersdef template AA64FpRegRegRegOpConstructor {{
9810037SARM gem5 Developers    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
9910037SARM gem5 Developers                                          IntRegIndex _dest,
10010037SARM gem5 Developers                                          IntRegIndex _op1,
10110037SARM gem5 Developers                                          IntRegIndex _op2,
10210037SARM gem5 Developers                                          VfpMicroMode mode)
10310037SARM gem5 Developers        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
10410037SARM gem5 Developers                         _dest, _op1, _op2, mode)
10510037SARM gem5 Developers    {
10610037SARM gem5 Developers        %(constructor)s;
10710037SARM gem5 Developers        for (int x = 0; x < _numDestRegs; x++) {
10810037SARM gem5 Developers            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
10910037SARM gem5 Developers        }
11010037SARM gem5 Developers    }
11110037SARM gem5 Developers}};
11210037SARM gem5 Developers
11310037SARM gem5 Developersdef template AA64FpRegRegRegRegOpDeclare {{
11410037SARM gem5 Developersclass %(class_name)s : public %(base_class)s
11510037SARM gem5 Developers{
11610037SARM gem5 Developers  public:
11710037SARM gem5 Developers    // Constructor
11810037SARM gem5 Developers    %(class_name)s(ExtMachInst machInst,
11910037SARM gem5 Developers                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
12010037SARM gem5 Developers                   IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop);
12110037SARM gem5 Developers    %(BasicExecDeclare)s
12210037SARM gem5 Developers};
12310037SARM gem5 Developers}};
12410037SARM gem5 Developers
12510037SARM gem5 Developersdef template AA64FpRegRegRegRegOpConstructor {{
12610037SARM gem5 Developers    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
12710037SARM gem5 Developers                                          IntRegIndex _dest,
12810037SARM gem5 Developers                                          IntRegIndex _op1,
12910037SARM gem5 Developers                                          IntRegIndex _op2,
13010037SARM gem5 Developers                                          IntRegIndex _op3,
13110037SARM gem5 Developers                                          VfpMicroMode mode)
13210037SARM gem5 Developers        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
13310037SARM gem5 Developers                         _dest, _op1, _op2, _op3, mode)
13410037SARM gem5 Developers    {
13510037SARM gem5 Developers        %(constructor)s;
13610037SARM gem5 Developers        for (int x = 0; x < _numDestRegs; x++) {
13710037SARM gem5 Developers                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
13810037SARM gem5 Developers        }
13910037SARM gem5 Developers    }
14010037SARM gem5 Developers}};
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