1// -*- mode:c++ -*- 2// Copyright (c) 2018 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software 9// licensed hereunder. You may use the software subject to the license 10// terms below provided that you ensure that this notice is replicated 11// unmodified and in its entirety in all distributions of the software, 12// modified or unmodified, in source code or in binary form. 13// 14// Redistribution and use in source and binary forms, with or without 15// modification, are permitted provided that the following conditions are 16// met: redistributions of source code must retain the above copyright 17// notice, this list of conditions and the following disclaimer; 18// redistributions in binary form must reproduce the above copyright 19// notice, this list of conditions and the following disclaimer in the 20// documentation and/or other materials provided with the distribution; 21// neither the name of the copyright holders nor the names of its 22// contributors may be used to endorse or promote products derived from 23// this software without specific prior written permission. 24// 25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36// 37// Authors: Giacomo Travaglini 38 39// 40// A new class of Semihosting constructor templates has been added. 41// Their main purpose is to check if the Exception Generation 42// Instructions (HLT, SVC) are actually a semihosting command. 43// If that is the case, the IsMemBarrier flag is raised, so that 44// in the O3 model we perform a coherent memory access during 45// the semihosting operation. 46// Please note: since we don't have a thread context pointer in the 47// constructor we cannot check if semihosting is enabled in the 48// system. This is not affecting functional correctness, it just 49// means O3 models will flush the LSQ even if semihosting is disabled 50// when a semihosting immediate is recognized. 51 52def template SemihostConstructor {{ 53 %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) 54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 55 { 56 %(constructor)s; 57 if (!(condCode == COND_AL || condCode == COND_UC)) { 58 for (int x = 0; x < _numDestRegs; x++) { 59 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 60 } 61 } 62 63 // In AArch32 semihosting commands can be issued by either 64 // SVC and HLT instructions. Another degree of freedom 65 // is added by the operating mode (Arm or Thumb) 66 auto semihost_imm = machInst.thumb? %(thumb_semihost)s : 67 %(arm_semihost)s; 68 if (_imm == semihost_imm) { 69 flags[IsMemBarrier] = true; 70 } 71 } 72}}; 73 74def template SemihostConstructor64 {{ 75 %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) 76 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 77 { 78 %(constructor)s; 79 80 // In AArch64 there is only one instruction for issuing 81 // semhosting commands: HLT #0xF000 82 if (_imm == 0xF000) { 83 flags[IsMemBarrier] = true; 84 } 85 } 86}}; 87