pred.isa revision 8142
16019SN/A// -*- mode:c++ -*-
26019SN/A
37110SN/A// Copyright (c) 2010 ARM Limited
47110SN/A// All rights reserved
57110SN/A//
67110SN/A// The license below extends only to copyright in the software and shall
77110SN/A// not be construed as granting a license to any other intellectual
87110SN/A// property including but not limited to intellectual property relating
97110SN/A// to a hardware implementation of the functionality of the software
107110SN/A// licensed hereunder.  You may use the software subject to the license
117110SN/A// terms below provided that you ensure that this notice is replicated
127110SN/A// unmodified and in its entirety in all distributions of the software,
137110SN/A// modified or unmodified, in source code or in binary form.
147110SN/A//
156019SN/A// Copyright (c) 2007-2008 The Florida State University
166019SN/A// All rights reserved.
176019SN/A//
186019SN/A// Redistribution and use in source and binary forms, with or without
196019SN/A// modification, are permitted provided that the following conditions are
206019SN/A// met: redistributions of source code must retain the above copyright
216019SN/A// notice, this list of conditions and the following disclaimer;
226019SN/A// redistributions in binary form must reproduce the above copyright
236019SN/A// notice, this list of conditions and the following disclaimer in the
246019SN/A// documentation and/or other materials provided with the distribution;
256019SN/A// neither the name of the copyright holders nor the names of its
266019SN/A// contributors may be used to endorse or promote products derived from
276019SN/A// this software without specific prior written permission.
286019SN/A//
296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406019SN/A//
416019SN/A// Authors: Stephen Hines
426019SN/A
436019SN/A////////////////////////////////////////////////////////////////////
446019SN/A//
456019SN/A// Predicated Instruction Execution
466019SN/A//
476019SN/A
486243SN/Alet {{
497422Sgblack@eecs.umich.edu    predicateTest = 'testPredicate(OptCondCodes, condCode)'
507422Sgblack@eecs.umich.edu    condPredicateTest = 'testPredicate(CondCodes, condCode)'
516243SN/A}};
526243SN/A
537138Sgblack@eecs.umich.edudef template DataImmDeclare {{
547138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s
557138Sgblack@eecs.umich.edu{
567138Sgblack@eecs.umich.edu    public:
577138Sgblack@eecs.umich.edu        // Constructor
587138Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
597138Sgblack@eecs.umich.edu                IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
607138Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
617138Sgblack@eecs.umich.edu};
627138Sgblack@eecs.umich.edu}};
637138Sgblack@eecs.umich.edu
647138Sgblack@eecs.umich.edudef template DataImmConstructor {{
657138Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
667138Sgblack@eecs.umich.edu                                          IntRegIndex _dest,
677138Sgblack@eecs.umich.edu                                          IntRegIndex _op1,
687138Sgblack@eecs.umich.edu                                          uint32_t _imm,
697138Sgblack@eecs.umich.edu                                          bool _rotC)
707138Sgblack@eecs.umich.edu        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
717138Sgblack@eecs.umich.edu                         _dest, _op1, _imm, _rotC)
727138Sgblack@eecs.umich.edu    {
737138Sgblack@eecs.umich.edu        %(constructor)s;
747848SAli.Saidi@ARM.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
757848SAli.Saidi@ARM.com            for (int x = 0; x < _numDestRegs; x++) {
767848SAli.Saidi@ARM.com                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
777848SAli.Saidi@ARM.com            }
787848SAli.Saidi@ARM.com        }
797138Sgblack@eecs.umich.edu    }
807138Sgblack@eecs.umich.edu}};
817138Sgblack@eecs.umich.edu
827138Sgblack@eecs.umich.edudef template DataRegDeclare {{
837138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s
847138Sgblack@eecs.umich.edu{
857138Sgblack@eecs.umich.edu    public:
867138Sgblack@eecs.umich.edu        // Constructor
877138Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
887138Sgblack@eecs.umich.edu                IntRegIndex _op1, IntRegIndex _op2,
897138Sgblack@eecs.umich.edu                int32_t _shiftAmt, ArmShiftType _shiftType);
907138Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
917138Sgblack@eecs.umich.edu};
927138Sgblack@eecs.umich.edu}};
937138Sgblack@eecs.umich.edu
947138Sgblack@eecs.umich.edudef template DataRegConstructor {{
957138Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
967138Sgblack@eecs.umich.edu                                          IntRegIndex _dest,
977138Sgblack@eecs.umich.edu                                          IntRegIndex _op1,
987138Sgblack@eecs.umich.edu                                          IntRegIndex _op2,
997138Sgblack@eecs.umich.edu                                          int32_t _shiftAmt,
1007138Sgblack@eecs.umich.edu                                          ArmShiftType _shiftType)
1017138Sgblack@eecs.umich.edu        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1027138Sgblack@eecs.umich.edu                         _dest, _op1, _op2, _shiftAmt, _shiftType)
1037138Sgblack@eecs.umich.edu    {
1047138Sgblack@eecs.umich.edu        %(constructor)s;
1057848SAli.Saidi@ARM.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
1067848SAli.Saidi@ARM.com            for (int x = 0; x < _numDestRegs; x++) {
1077848SAli.Saidi@ARM.com                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1087848SAli.Saidi@ARM.com            }
1097848SAli.Saidi@ARM.com        }
1107138Sgblack@eecs.umich.edu    }
1117138Sgblack@eecs.umich.edu}};
1127138Sgblack@eecs.umich.edu
1137138Sgblack@eecs.umich.edudef template DataRegRegDeclare {{
1147138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s
1157138Sgblack@eecs.umich.edu{
1167138Sgblack@eecs.umich.edu    public:
1177138Sgblack@eecs.umich.edu        // Constructor
1187138Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
1197138Sgblack@eecs.umich.edu                IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
1207138Sgblack@eecs.umich.edu                ArmShiftType _shiftType);
1217138Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
1227138Sgblack@eecs.umich.edu};
1237138Sgblack@eecs.umich.edu}};
1247138Sgblack@eecs.umich.edu
1257138Sgblack@eecs.umich.edudef template DataRegRegConstructor {{
1267138Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1277138Sgblack@eecs.umich.edu                                          IntRegIndex _dest,
1287138Sgblack@eecs.umich.edu                                          IntRegIndex _op1,
1297138Sgblack@eecs.umich.edu                                          IntRegIndex _op2,
1307138Sgblack@eecs.umich.edu                                          IntRegIndex _shift,
1317138Sgblack@eecs.umich.edu                                          ArmShiftType _shiftType)
1327138Sgblack@eecs.umich.edu        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1337138Sgblack@eecs.umich.edu                         _dest, _op1, _op2, _shift, _shiftType)
1347138Sgblack@eecs.umich.edu    {
1357138Sgblack@eecs.umich.edu        %(constructor)s;
1367848SAli.Saidi@ARM.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
1377848SAli.Saidi@ARM.com            for (int x = 0; x < _numDestRegs; x++) {
1387848SAli.Saidi@ARM.com                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1397848SAli.Saidi@ARM.com            }
1407848SAli.Saidi@ARM.com        }
1417138Sgblack@eecs.umich.edu    }
1427138Sgblack@eecs.umich.edu}};
1437138Sgblack@eecs.umich.edu
1446019SN/Adef template PredOpExecute {{
1456019SN/A    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
1466019SN/A    {
1476019SN/A        Fault fault = NoFault;
1486271SN/A        uint64_t resTemp = 0;
1496271SN/A        resTemp = resTemp;
1506019SN/A        %(op_decl)s;
1516019SN/A        %(op_rd)s;
1526019SN/A
1536243SN/A        if (%(predicate_test)s)
1546019SN/A        {
1556243SN/A            %(code)s;
1566019SN/A            if (fault == NoFault)
1576019SN/A            {
1586019SN/A                %(op_wb)s;
1596019SN/A            }
1607597Sminkyu.jeong@arm.com        } else {
1617597Sminkyu.jeong@arm.com            xc->setPredicate(false);
1626019SN/A        }
1636019SN/A
1647646Sgene.wu@arm.com        if (fault == NoFault && machInst.itstateMask != 0&&
1657646Sgene.wu@arm.com                (!isMicroop() || isLastMicroop())) {
1667408Sgblack@eecs.umich.edu            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
1677408Sgblack@eecs.umich.edu        }
1687408Sgblack@eecs.umich.edu
1696019SN/A        return fault;
1706019SN/A    }
1716019SN/A}};
1726019SN/A
1738142SAli.Saidi@ARM.comdef template QuiescePredOpExecute {{
1748142SAli.Saidi@ARM.com    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
1758142SAli.Saidi@ARM.com    {
1768142SAli.Saidi@ARM.com        Fault fault = NoFault;
1778142SAli.Saidi@ARM.com        uint64_t resTemp = 0;
1788142SAli.Saidi@ARM.com        resTemp = resTemp;
1798142SAli.Saidi@ARM.com        %(op_decl)s;
1808142SAli.Saidi@ARM.com        %(op_rd)s;
1818142SAli.Saidi@ARM.com
1828142SAli.Saidi@ARM.com        if (%(predicate_test)s)
1838142SAli.Saidi@ARM.com        {
1848142SAli.Saidi@ARM.com            %(code)s;
1858142SAli.Saidi@ARM.com            if (fault == NoFault)
1868142SAli.Saidi@ARM.com            {
1878142SAli.Saidi@ARM.com                %(op_wb)s;
1888142SAli.Saidi@ARM.com            }
1898142SAli.Saidi@ARM.com        } else {
1908142SAli.Saidi@ARM.com            xc->setPredicate(false);
1918142SAli.Saidi@ARM.com#if FULL_SYSTEM
1928142SAli.Saidi@ARM.com            PseudoInst::quiesceSkip(xc->tcBase());
1938142SAli.Saidi@ARM.com#endif
1948142SAli.Saidi@ARM.com        }
1958142SAli.Saidi@ARM.com
1968142SAli.Saidi@ARM.com        if (fault == NoFault && machInst.itstateMask != 0&&
1978142SAli.Saidi@ARM.com                (!isMicroop() || isLastMicroop())) {
1988142SAli.Saidi@ARM.com            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
1998142SAli.Saidi@ARM.com        }
2008142SAli.Saidi@ARM.com
2018142SAli.Saidi@ARM.com        return fault;
2028142SAli.Saidi@ARM.com    }
2038142SAli.Saidi@ARM.com}};
2048142SAli.Saidi@ARM.com
2056265SN/Adef template DataDecode {{
2066265SN/A    if (machInst.opcode4 == 0) {
2076265SN/A        if (machInst.sField == 0)
2086265SN/A            return new %(class_name)sImm(machInst);
2096265SN/A        else
2106265SN/A            return new %(class_name)sImmCc(machInst);
2116265SN/A    } else {
2126265SN/A        if (machInst.sField == 0)
2136265SN/A            return new %(class_name)s(machInst);
2146265SN/A        else
2156265SN/A            return new %(class_name)sCc(machInst);
2166265SN/A    }
2176265SN/A}};
2186265SN/A
2196270SN/Adef template DataImmDecode {{
2206270SN/A    if (machInst.sField == 0)
2216270SN/A        return new %(class_name)s(machInst);
2226270SN/A    else
2236270SN/A        return new %(class_name)sCc(machInst);
2246270SN/A}};
225