pred.isa revision 8142
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Predicated Instruction Execution 46// 47 48let {{ 49 predicateTest = 'testPredicate(OptCondCodes, condCode)' 50 condPredicateTest = 'testPredicate(CondCodes, condCode)' 51}}; 52 53def template DataImmDeclare {{ 54class %(class_name)s : public %(base_class)s 55{ 56 public: 57 // Constructor 58 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 59 IntRegIndex _op1, uint32_t _imm, bool _rotC=true); 60 %(BasicExecDeclare)s 61}; 62}}; 63 64def template DataImmConstructor {{ 65 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 66 IntRegIndex _dest, 67 IntRegIndex _op1, 68 uint32_t _imm, 69 bool _rotC) 70 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 71 _dest, _op1, _imm, _rotC) 72 { 73 %(constructor)s; 74 if (!(condCode == COND_AL || condCode == COND_UC)) { 75 for (int x = 0; x < _numDestRegs; x++) { 76 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 77 } 78 } 79 } 80}}; 81 82def template DataRegDeclare {{ 83class %(class_name)s : public %(base_class)s 84{ 85 public: 86 // Constructor 87 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 88 IntRegIndex _op1, IntRegIndex _op2, 89 int32_t _shiftAmt, ArmShiftType _shiftType); 90 %(BasicExecDeclare)s 91}; 92}}; 93 94def template DataRegConstructor {{ 95 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 96 IntRegIndex _dest, 97 IntRegIndex _op1, 98 IntRegIndex _op2, 99 int32_t _shiftAmt, 100 ArmShiftType _shiftType) 101 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 102 _dest, _op1, _op2, _shiftAmt, _shiftType) 103 { 104 %(constructor)s; 105 if (!(condCode == COND_AL || condCode == COND_UC)) { 106 for (int x = 0; x < _numDestRegs; x++) { 107 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 108 } 109 } 110 } 111}}; 112 113def template DataRegRegDeclare {{ 114class %(class_name)s : public %(base_class)s 115{ 116 public: 117 // Constructor 118 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 119 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, 120 ArmShiftType _shiftType); 121 %(BasicExecDeclare)s 122}; 123}}; 124 125def template DataRegRegConstructor {{ 126 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 127 IntRegIndex _dest, 128 IntRegIndex _op1, 129 IntRegIndex _op2, 130 IntRegIndex _shift, 131 ArmShiftType _shiftType) 132 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 133 _dest, _op1, _op2, _shift, _shiftType) 134 { 135 %(constructor)s; 136 if (!(condCode == COND_AL || condCode == COND_UC)) { 137 for (int x = 0; x < _numDestRegs; x++) { 138 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 139 } 140 } 141 } 142}}; 143 144def template PredOpExecute {{ 145 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 146 { 147 Fault fault = NoFault; 148 uint64_t resTemp = 0; 149 resTemp = resTemp; 150 %(op_decl)s; 151 %(op_rd)s; 152 153 if (%(predicate_test)s) 154 { 155 %(code)s; 156 if (fault == NoFault) 157 { 158 %(op_wb)s; 159 } 160 } else { 161 xc->setPredicate(false); 162 } 163 164 if (fault == NoFault && machInst.itstateMask != 0&& 165 (!isMicroop() || isLastMicroop())) { 166 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 167 } 168 169 return fault; 170 } 171}}; 172 173def template QuiescePredOpExecute {{ 174 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 175 { 176 Fault fault = NoFault; 177 uint64_t resTemp = 0; 178 resTemp = resTemp; 179 %(op_decl)s; 180 %(op_rd)s; 181 182 if (%(predicate_test)s) 183 { 184 %(code)s; 185 if (fault == NoFault) 186 { 187 %(op_wb)s; 188 } 189 } else { 190 xc->setPredicate(false); 191#if FULL_SYSTEM 192 PseudoInst::quiesceSkip(xc->tcBase()); 193#endif 194 } 195 196 if (fault == NoFault && machInst.itstateMask != 0&& 197 (!isMicroop() || isLastMicroop())) { 198 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 199 } 200 201 return fault; 202 } 203}}; 204 205def template DataDecode {{ 206 if (machInst.opcode4 == 0) { 207 if (machInst.sField == 0) 208 return new %(class_name)sImm(machInst); 209 else 210 return new %(class_name)sImmCc(machInst); 211 } else { 212 if (machInst.sField == 0) 213 return new %(class_name)s(machInst); 214 else 215 return new %(class_name)sCc(machInst); 216 } 217}}; 218 219def template DataImmDecode {{ 220 if (machInst.sField == 0) 221 return new %(class_name)s(machInst); 222 else 223 return new %(class_name)sCc(machInst); 224}}; 225