operands.isa revision 7186
12068SN/A// -*- mode:c++ -*- 22068SN/A// Copyright (c) 2010 ARM Limited 32068SN/A// All rights reserved 42068SN/A// 52068SN/A// The license below extends only to copyright in the software and shall 62068SN/A// not be construed as granting a license to any other intellectual 72068SN/A// property including but not limited to intellectual property relating 82068SN/A// to a hardware implementation of the functionality of the software 92068SN/A// licensed hereunder. You may use the software subject to the license 102068SN/A// terms below provided that you ensure that this notice is replicated 112068SN/A// unmodified and in its entirety in all distributions of the software, 122068SN/A// modified or unmodified, in source code or in binary form. 132068SN/A// 142068SN/A// Copyright (c) 2007-2008 The Florida State University 152068SN/A// All rights reserved. 162068SN/A// 172068SN/A// Redistribution and use in source and binary forms, with or without 182068SN/A// modification, are permitted provided that the following conditions are 192068SN/A// met: redistributions of source code must retain the above copyright 202068SN/A// notice, this list of conditions and the following disclaimer; 212068SN/A// redistributions in binary form must reproduce the above copyright 222068SN/A// notice, this list of conditions and the following disclaimer in the 232068SN/A// documentation and/or other materials provided with the distribution; 242068SN/A// neither the name of the copyright holders nor the names of its 252068SN/A// contributors may be used to endorse or promote products derived from 262068SN/A// this software without specific prior written permission. 272068SN/A// 282665Ssaidi@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322649Ssaidi@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332649Ssaidi@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342649Ssaidi@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352649Ssaidi@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362649Ssaidi@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392068SN/A// 402068SN/A// Authors: Stephen Hines 412068SN/A 422068SN/Adef operand_types {{ 432068SN/A 'sb' : ('signed int', 8), 442068SN/A 'ub' : ('unsigned int', 8), 452068SN/A 'sh' : ('signed int', 16), 462068SN/A 'uh' : ('unsigned int', 16), 472068SN/A 'sw' : ('signed int', 32), 482107SN/A 'uw' : ('unsigned int', 32), 492068SN/A 'ud' : ('unsigned int', 64), 502107SN/A 'sf' : ('float', 32), 512068SN/A 'df' : ('float', 64) 522068SN/A}}; 532227SN/A 542107SN/Alet {{ 552107SN/A maybePCRead = ''' 562068SN/A ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) : 572068SN/A xc->%(func)s(this, %(op_idx)s)) 582068SN/A ''' 592068SN/A maybeAlignedPCRead = ''' 602068SN/A ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) : 612068SN/A xc->%(func)s(this, %(op_idx)s)) 622068SN/A ''' 632068SN/A maybePCWrite = ''' 642068SN/A ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : 652068SN/A xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 662107SN/A ''' 672107SN/A maybeIWPCWrite = ''' 682068SN/A ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) : 692068SN/A xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 702068SN/A ''' 712068SN/A maybeAIWPCWrite = ''' 722068SN/A if (%(reg_idx)s == PCReg) { 732068SN/A if (xc->readPC() & (ULL(1) << PcTBitShift)) { 742068SN/A setIWNextPC(xc, %(final_val)s); 752068SN/A } else { 762068SN/A setNextPC(xc, %(final_val)s); 772068SN/A } 782068SN/A } else { 792068SN/A xc->%(func)s(this, %(op_idx)s, %(final_val)s); 802068SN/A } 812227SN/A ''' 822107SN/A 832107SN/A readNPC = 'xc->readNextPC() & ~PcModeMask' 842068SN/A writeNPC = 'setNextPC(xc, %(final_val)s)' 852068SN/A writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 862068SN/A forceNPC = 'xc->setNextPC(%(final_val)s)' 872068SN/A}}; 882068SN/A 892068SN/Adef operands {{ 902068SN/A #Abstracted integer reg operands 912068SN/A 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 922068SN/A maybePCRead, maybePCWrite), 932068SN/A 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 942068SN/A maybePCRead, maybeIWPCWrite), 952068SN/A 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 962068SN/A maybePCRead, maybeAIWPCWrite), 972068SN/A 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 982068SN/A maybeAlignedPCRead, maybePCWrite), 992068SN/A 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 1002227SN/A maybePCRead, maybePCWrite), 1012107SN/A 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 1022107SN/A maybePCRead, maybePCWrite), 1032068SN/A 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, 1042068SN/A maybePCRead, maybePCWrite), 1052068SN/A 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, 1062068SN/A maybePCRead, maybePCWrite), 1072068SN/A 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, 1082068SN/A maybePCRead, maybePCWrite), 1092068SN/A 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7, 1102068SN/A maybePCRead, maybePCWrite), 1112068SN/A 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8, 1122068SN/A maybePCRead, maybePCWrite), 1132068SN/A 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9, 1142068SN/A maybePCRead, maybePCWrite), 1152068SN/A #General Purpose Integer Reg Operands 1162068SN/A 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 1172068SN/A 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 1182068SN/A 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 1192068SN/A 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 1202068SN/A 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 1212068SN/A 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 1222068SN/A 1232068SN/A #Destination register for load/store double instructions 1242068SN/A 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 1252068SN/A 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 1262068SN/A 1272068SN/A 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 1282068SN/A 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 1292068SN/A 1302068SN/A #Register fields for microops 1312068SN/A 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 1322068SN/A 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 1332068SN/A 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 1342068SN/A 1352068SN/A #General Purpose Floating Point Reg Operands 1362068SN/A 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 1372068SN/A 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 1382068SN/A 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 1392068SN/A 1402068SN/A #Memory Operand 1412068SN/A 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 1422068SN/A 1432068SN/A 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 1442068SN/A 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 1452068SN/A 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 1462068SN/A 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 1472068SN/A 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 1482068SN/A 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), 1492068SN/A 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 1502068SN/A readNPC, writeNPC), 1512068SN/A 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 1522227SN/A readNPC, forceNPC), 1532068SN/A 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 1542068SN/A readNPC, writeIWNPC), 1552068SN/A}}; 1562068SN/A