operands.isa revision 7186
1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software 9// licensed hereunder. You may use the software subject to the license 10// terms below provided that you ensure that this notice is replicated 11// unmodified and in its entirety in all distributions of the software, 12// modified or unmodified, in source code or in binary form. 13// 14// Copyright (c) 2007-2008 The Florida State University 15// All rights reserved. 16// 17// Redistribution and use in source and binary forms, with or without 18// modification, are permitted provided that the following conditions are 19// met: redistributions of source code must retain the above copyright 20// notice, this list of conditions and the following disclaimer; 21// redistributions in binary form must reproduce the above copyright 22// notice, this list of conditions and the following disclaimer in the 23// documentation and/or other materials provided with the distribution; 24// neither the name of the copyright holders nor the names of its 25// contributors may be used to endorse or promote products derived from 26// this software without specific prior written permission. 27// 28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39// 40// Authors: Stephen Hines 41 42def operand_types {{ 43 'sb' : ('signed int', 8), 44 'ub' : ('unsigned int', 8), 45 'sh' : ('signed int', 16), 46 'uh' : ('unsigned int', 16), 47 'sw' : ('signed int', 32), 48 'uw' : ('unsigned int', 32), 49 'ud' : ('unsigned int', 64), 50 'sf' : ('float', 32), 51 'df' : ('float', 64) 52}}; 53 54let {{ 55 maybePCRead = ''' 56 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) : 57 xc->%(func)s(this, %(op_idx)s)) 58 ''' 59 maybeAlignedPCRead = ''' 60 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) : 61 xc->%(func)s(this, %(op_idx)s)) 62 ''' 63 maybePCWrite = ''' 64 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : 65 xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 66 ''' 67 maybeIWPCWrite = ''' 68 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) : 69 xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 70 ''' 71 maybeAIWPCWrite = ''' 72 if (%(reg_idx)s == PCReg) { 73 if (xc->readPC() & (ULL(1) << PcTBitShift)) { 74 setIWNextPC(xc, %(final_val)s); 75 } else { 76 setNextPC(xc, %(final_val)s); 77 } 78 } else { 79 xc->%(func)s(this, %(op_idx)s, %(final_val)s); 80 } 81 ''' 82 83 readNPC = 'xc->readNextPC() & ~PcModeMask' 84 writeNPC = 'setNextPC(xc, %(final_val)s)' 85 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 86 forceNPC = 'xc->setNextPC(%(final_val)s)' 87}}; 88 89def operands {{ 90 #Abstracted integer reg operands 91 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 92 maybePCRead, maybePCWrite), 93 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 94 maybePCRead, maybeIWPCWrite), 95 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 96 maybePCRead, maybeAIWPCWrite), 97 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 98 maybeAlignedPCRead, maybePCWrite), 99 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 100 maybePCRead, maybePCWrite), 101 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 102 maybePCRead, maybePCWrite), 103 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, 104 maybePCRead, maybePCWrite), 105 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, 106 maybePCRead, maybePCWrite), 107 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, 108 maybePCRead, maybePCWrite), 109 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7, 110 maybePCRead, maybePCWrite), 111 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8, 112 maybePCRead, maybePCWrite), 113 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9, 114 maybePCRead, maybePCWrite), 115 #General Purpose Integer Reg Operands 116 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 117 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 118 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 119 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 120 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 121 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 122 123 #Destination register for load/store double instructions 124 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 125 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 126 127 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 128 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 129 130 #Register fields for microops 131 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 132 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 133 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 134 135 #General Purpose Floating Point Reg Operands 136 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 137 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 138 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 139 140 #Memory Operand 141 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 142 143 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 144 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 145 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 146 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 147 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 148 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), 149 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 150 readNPC, writeNPC), 151 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 152 readNPC, forceNPC), 153 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 154 readNPC, writeIWNPC), 155}}; 156