xref: /gem5/src/arch/arm/isa/operands.isa

// -*- mode:c++ -*-
// Copyright (c) 2010-2014, 2016-2018 ARM Limited
// All rights reserved
//
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// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
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// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// Authors: Stephen Hines

def operand_types {{
    'sb' : 'int8_t',
    'ub' : 'uint8_t',
    'sh' : 'int16_t',
    'uh' : 'uint16_t',
    'sw' : 'int32_t',
    'uw' : 'uint32_t',
    'sd' : 'int64_t',
    'ud' : 'uint64_t',
    'sq' : '__int128_t',
    'uq' : '__uint128_t',
    'tud' : 'std::array<uint64_t, 2>',
    'sf' : 'float',
    'df' : 'double',
    'vc' : 'ArmISA::VecRegContainer',
    # For operations that are implemented as a template
    'x' : 'TPElem',
    'xs' : 'TPSElem',
    'xd' : 'TPDElem',
    'pc' : 'ArmISA::VecPredRegContainer',
    'pb' : 'uint8_t'
}};

let {{
    maybePCRead = '''
        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
    '''
    maybeAlignedPCRead = '''
        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
         xc->%(func)s(this, %(op_idx)s))
    '''
    maybePCWrite = '''
        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
    '''
    maybeIWPCWrite = '''
        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
    '''
    maybeAIWPCWrite = '''
        if (%(reg_idx)s == PCReg) {
            bool thumb = THUMB;
            if (thumb) {
                setNextPC(xc, %(final_val)s);
            } else {
                setIWNextPC(xc, %(final_val)s);
            }
        } else {
            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
        }
    '''
    aarch64Read = '''
        ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
    '''
    aarch64Write = '''
        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
    '''
    aarchX64Read = '''
        ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
    '''
    aarchX64Write = '''
        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
    '''
    aarchW64Read = '''
        ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
    '''
    aarchW64Write = '''
        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
    '''
    cntrlNsBankedWrite = '''
        xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
    '''

    cntrlNsBankedRead = '''
        xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
    '''

    #PCState operands need to have a sorting index (the number at the end)
    #less than all the integer registers which might update the PC. That way
    #if the flag bits of the pc state are updated and a branch happens through
    #R15, the updates are layered properly and the R15 update isn't lost.
    srtNormal = 5
    srtCpsr = 4
    srtBase = 3
    srtPC = 2
    srtMode = 1
    srtEPC = 0

    def vectorElem(idx, elem):
        return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)

    def vectorReg(idx, elems = None):
        return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)

    def vectorRegElem(elem, ext = 'sf', zeroing = False):
        return (elem, ext, zeroing)

    def vecPredReg(idx):
        return ('VecPredReg', 'pc', idx, None, srtNormal)

    def intReg(idx):
        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
                maybePCRead, maybePCWrite)

    def intReg64(idx):
        return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
                aarch64Read, aarch64Write)

    def intRegX64(idx, id = srtNormal):
        return ('IntReg', 'ud', idx, 'IsInteger', id,
                aarchX64Read, aarchX64Write)

    def intRegW64(idx, id = srtNormal):
        return ('IntReg', 'ud', idx, 'IsInteger', id,
                aarchW64Read, aarchW64Write)

    def intRegNPC(idx):
        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)

    def intRegAPC(idx, id = srtNormal):
        return ('IntReg', 'uw', idx, 'IsInteger', id,
                maybeAlignedPCRead, maybePCWrite)

    def intRegIWPC(idx):
        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
                maybePCRead, maybeIWPCWrite)

    def intRegAIWPC(idx):
        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
                maybePCRead, maybeAIWPCWrite)

    def ccReg(idx):
        return ('CCReg', 'uw', idx, None, srtNormal)

    def cntrlReg(idx, id = srtNormal, type = 'uw'):
        return ('ControlReg', type, idx, None, id)

    def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)

    def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)

    def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
        return ('ControlReg', type, idx, None, id)

    def pcStateReg(idx, id):
        return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
}};

def operands {{
    #Abstracted integer reg operands
    'Dest': intReg('dest'),
    'Dest64': intReg64('dest'),
    'XDest': intRegX64('dest'),
    'WDest': intRegW64('dest'),
    'IWDest': intRegIWPC('dest'),
    'AIWDest': intRegAIWPC('dest'),
    'Dest2': intReg('dest2'),
    'XDest2': intRegX64('dest2'),
    'IWDest2': intRegIWPC('dest2'),
    'Result': intReg('result'),
    'XResult': intRegX64('result'),
    'XBase': intRegX64('base', id = srtBase),
    'Base': intRegAPC('base', id = srtBase),
    'XOffset': intRegX64('offset'),
    'Index': intReg('index'),
    'Shift': intReg('shift'),
    'Op1': intReg('op1'),
    'Op2': intReg('op2'),
    'Op3': intReg('op3'),
    'Op164': intReg64('op1'),
    'Op264': intReg64('op2'),
    'Op364': intReg64('op3'),
    'XOp1': intRegX64('op1'),
    'XOp2': intRegX64('op2'),
    'XOp3': intRegX64('op3'),
    'WOp1': intRegW64('op1'),
    'WOp2': intRegW64('op2'),
    'WOp3': intRegW64('op3'),
    'Reg0': intReg('reg0'),
    'Reg1': intReg('reg1'),
    'Reg2': intReg('reg2'),
    'Reg3': intReg('reg3'),

    #Fixed index integer reg operands
    'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
    'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
    'LR': intRegNPC('INTREG_LR'),
    'XLR': intRegX64('INTREG_X30'),
    'R7': intRegNPC('7'),
    # First four arguments are passed in registers
    'R0': intRegNPC('0'),
    'R1': intRegNPC('1'),
    'R2': intRegNPC('2'),
    'R3': intRegNPC('3'),
    'X0': intRegX64('0'),
    'X1': intRegX64('1'),
    'X2': intRegX64('2'),
    'X3': intRegX64('3'),

    # Condition code registers
    'CondCodesNZ': ccReg('CCREG_NZ'),
    'CondCodesC': ccReg('CCREG_C'),
    'CondCodesV': ccReg('CCREG_V'),
    'CondCodesGE': ccReg('CCREG_GE'),
    'OptCondCodesNZ': ccReg(
            '''((condCode == COND_AL || condCode == COND_UC ||
                 condCode == COND_CC || condCode == COND_CS ||
                 condCode == COND_VS || condCode == COND_VC) ?
                CCREG_ZERO : CCREG_NZ)'''),
    'OptCondCodesC': ccReg(
             '''((condCode == COND_HI || condCode == COND_LS ||
                condCode == COND_CS || condCode == COND_CC) ?
               CCREG_C : CCREG_ZERO)'''),
    'OptShiftRmCondCodesC': ccReg(
            '''((condCode == COND_HI || condCode == COND_LS ||
                 condCode == COND_CS || condCode == COND_CC ||
                 shiftType == ROR) ?
                CCREG_C : CCREG_ZERO)'''),
    'OptCondCodesV': ccReg(
            '''((condCode == COND_VS || condCode == COND_VC ||
                 condCode == COND_GE || condCode == COND_LT ||
                 condCode == COND_GT || condCode == COND_LE) ?
                CCREG_V : CCREG_ZERO)'''),
    'FpCondCodes': ccReg('CCREG_FP'),

    #Abstracted floating point reg operands
    'FpDest': vectorElem('dest / 4', 'dest % 4'),
    'FpDestP0': vectorElem('(dest + 0) / 4', '(dest + 0) % 4'),
    'FpDestP1': vectorElem('(dest + 1) / 4', '(dest + 1) % 4'),
    'FpDestP2': vectorElem('(dest + 2) / 4', '(dest + 2) % 4'),
    'FpDestP3': vectorElem('(dest + 3) / 4', '(dest + 3) % 4'),
    'FpDestP4': vectorElem('(dest + 4) / 4', '(dest + 4) % 4'),
    'FpDestP5': vectorElem('(dest + 5) / 4', '(dest + 5) % 4'),
    'FpDestP6': vectorElem('(dest + 6) / 4', '(dest + 6) % 4'),
    'FpDestP7': vectorElem('(dest + 7) / 4', '(dest + 7) % 4'),

    'FpDestS0P0': vectorElem(
        '(dest + step * 0 + 0) / 4', '(dest + step * 0 + 0) % 4'),
    'FpDestS0P1': vectorElem(
        '(dest + step * 0 + 1) / 4', '(dest + step * 0 + 1) % 4'),
    'FpDestS1P0': vectorElem(
        '(dest + step * 1 + 0) / 4', '(dest + step * 1 + 0) % 4'),
    'FpDestS1P1': vectorElem(
        '(dest + step * 1 + 1) / 4', '(dest + step * 1 + 1) % 4'),
    'FpDestS2P0': vectorElem(
        '(dest + step * 2 + 0) / 4', '(dest + step * 2 + 0) % 4'),
    'FpDestS2P1': vectorElem(
        '(dest + step * 2 + 1) / 4', '(dest + step * 2 + 1) % 4'),
    'FpDestS3P0': vectorElem(
        '(dest + step * 3 + 0) / 4', '(dest + step * 3 + 0) % 4'),
    'FpDestS3P1': vectorElem(
        '(dest + step * 3 + 1) / 4', '(dest + step * 3 + 1) % 4'),

    'FpDest2': vectorElem('dest2 / 4', 'dest2 % 4'),
    'FpDest2P0': vectorElem('(dest2 + 0) / 4', '(dest2 + 0) % 4'),
    'FpDest2P1': vectorElem('(dest2 + 1) / 4', '(dest2 + 1) % 4'),
    'FpDest2P2': vectorElem('(dest2 + 2) / 4', '(dest2 + 2) % 4'),
    'FpDest2P3': vectorElem('(dest2 + 3) / 4', '(dest2 + 3) % 4'),

    'FpOp1': vectorElem('op1 / 4', 'op1 % 4'),
    'FpOp1P0': vectorElem('(op1 + 0) / 4', '(op1 + 0) % 4'),
    'FpOp1P1': vectorElem('(op1 + 1) / 4', '(op1 + 1) % 4'),
    'FpOp1P2': vectorElem('(op1 + 2) / 4', '(op1 + 2) % 4'),
    'FpOp1P3': vectorElem('(op1 + 3) / 4', '(op1 + 3) % 4'),
    'FpOp1P4': vectorElem('(op1 + 4) / 4', '(op1 + 4) % 4'),
    'FpOp1P5': vectorElem('(op1 + 5) / 4', '(op1 + 5) % 4'),
    'FpOp1P6': vectorElem('(op1 + 6) / 4', '(op1 + 6) % 4'),
    'FpOp1P7': vectorElem('(op1 + 7) / 4', '(op1 + 7) % 4'),

    'FpOp1S0P0': vectorElem(
        '(op1 + step * 0 + 0) / 4', '(op1 + step * 0 + 0) % 4'),
    'FpOp1S0P1': vectorElem(
        '(op1 + step * 0 + 1) / 4', '(op1 + step * 0 + 1) % 4'),
    'FpOp1S1P0': vectorElem(
        '(op1 + step * 1 + 0) / 4', '(op1 + step * 1 + 0) % 4'),
    'FpOp1S1P1': vectorElem(
        '(op1 + step * 1 + 1) / 4', '(op1 + step * 1 + 1) % 4'),
    'FpOp1S2P0': vectorElem(
        '(op1 + step * 2 + 0) / 4', '(op1 + step * 2 + 0) % 4'),
    'FpOp1S2P1': vectorElem(
        '(op1 + step * 2 + 1) / 4', '(op1 + step * 2 + 1) % 4'),
    'FpOp1S3P0': vectorElem(
        '(op1 + step * 3 + 0) / 4', '(op1 + step * 3 + 0) % 4'),
    'FpOp1S3P1': vectorElem(
        '(op1 + step * 3 + 1) / 4', '(op1 + step * 3 + 1) % 4'),

    'FpOp2': vectorElem('op2 / 4', 'op2 % 4'),
    'FpOp2P0': vectorElem('(op2 + 0) / 4', '(op2 + 0) % 4'),
    'FpOp2P1': vectorElem('(op2 + 1) / 4', '(op2 + 1) % 4'),
    'FpOp2P2': vectorElem('(op2 + 2) / 4', '(op2 + 2) % 4'),
    'FpOp2P3': vectorElem('(op2 + 3) / 4', '(op2 + 3) % 4'),

    # Create AArch64 unpacked view of the FP registers
    # Name   ::= 'AA64Vec' OpSpec [LaneSpec]
    # OpSpec ::= IOSpec [Index] [Plus]
    # IOSpec ::= 'S' | 'D'
    # Index  ::= '0' | ... | '9'
    # Plus  ::= [PlusAmount] ['l']
    # PlusAmount ::= 'p' [PlusAmount]
    # LaneSpec ::= 'L' Index
    #
    # All the constituents are hierarchically defined as part of the Vector
    # Register they belong to

    'AA64FpOp1':       vectorReg('op1',
    {
        'AA64FpOp1P0': vectorRegElem('0'),
        'AA64FpOp1P1': vectorRegElem('1'),
        'AA64FpOp1P2': vectorRegElem('2'),
        'AA64FpOp1P3': vectorRegElem('3'),
        'AA64FpOp1S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp2':       vectorReg('op2',
    {
        'AA64FpOp2P0': vectorRegElem('0'),
        'AA64FpOp2P1': vectorRegElem('1'),
        'AA64FpOp2P2': vectorRegElem('2'),
        'AA64FpOp2P3': vectorRegElem('3'),
        'AA64FpOp2S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp2D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp2Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp3':       vectorReg('op3',
    {
        'AA64FpOp3P0': vectorRegElem('0'),
        'AA64FpOp3P1': vectorRegElem('1'),
        'AA64FpOp3P2': vectorRegElem('2'),
        'AA64FpOp3P3': vectorRegElem('3'),
        'AA64FpOp3S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp3D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp3Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpDest':       vectorReg('dest',
    {
        'AA64FpDestP0': vectorRegElem('0'),
        'AA64FpDestP1': vectorRegElem('1'),
        'AA64FpDestP2': vectorRegElem('2'),
        'AA64FpDestP3': vectorRegElem('3'),
        'AA64FpDestS':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpDestD':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpDestQ':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpDest2':       vectorReg('dest2',
    {
        'AA64FpDest2P0': vectorRegElem('0'),
        'AA64FpDest2P1': vectorRegElem('1'),
        'AA64FpDest2P2': vectorRegElem('2'),
        'AA64FpDest2P3': vectorRegElem('3'),
        'AA64FpDest2S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpDest2D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpDest2Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp1V0':       vectorReg('op1',
    {
        'AA64FpOp1P0V0': vectorRegElem('0'),
        'AA64FpOp1P1V0': vectorRegElem('1'),
        'AA64FpOp1P2V0': vectorRegElem('2'),
        'AA64FpOp1P3V0': vectorRegElem('3'),
        'AA64FpOp1SV0':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1DV0':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1QV0':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp1V1':       vectorReg('op1+1',
    {
        'AA64FpOp1P0V1': vectorRegElem('0'),
        'AA64FpOp1P1V1': vectorRegElem('1'),
        'AA64FpOp1P2V1': vectorRegElem('2'),
        'AA64FpOp1P3V1': vectorRegElem('3'),
        'AA64FpOp1SV1':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1DV1':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1QV1':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp1V2':       vectorReg('op1+2',
    {
        'AA64FpOp1P0V2': vectorRegElem('0'),
        'AA64FpOp1P1V2': vectorRegElem('1'),
        'AA64FpOp1P2V2': vectorRegElem('2'),
        'AA64FpOp1P3V2': vectorRegElem('3'),
        'AA64FpOp1SV2':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1DV2':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1QV2':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp1V3':       vectorReg('op1+3',
    {
        'AA64FpOp1P0V3': vectorRegElem('0'),
        'AA64FpOp1P1V3': vectorRegElem('1'),
        'AA64FpOp1P2V3': vectorRegElem('2'),
        'AA64FpOp1P3V3': vectorRegElem('3'),
        'AA64FpOp1SV3':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1DV3':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1QV3':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp1V0S':       vectorReg('(op1+0)%32',
    {
        'AA64FpOp1P0V0S': vectorRegElem('0'),
        'AA64FpOp1P1V0S': vectorRegElem('1'),
        'AA64FpOp1P2V0S': vectorRegElem('2'),
        'AA64FpOp1P3V0S': vectorRegElem('3'),
        'AA64FpOp1SV0S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1DV0S':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1QV0S':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp1V1S':       vectorReg('(op1+1)%32',
    {
        'AA64FpOp1P0V1S': vectorRegElem('0'),
        'AA64FpOp1P1V1S': vectorRegElem('1'),
        'AA64FpOp1P2V1S': vectorRegElem('2'),
        'AA64FpOp1P3V1S': vectorRegElem('3'),
        'AA64FpOp1SV1S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1DV1S':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1QV1S':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp1V2S':       vectorReg('(op1+2)%32',
    {
        'AA64FpOp1P0V2S': vectorRegElem('0'),
        'AA64FpOp1P1V2S': vectorRegElem('1'),
        'AA64FpOp1P2V2S': vectorRegElem('2'),
        'AA64FpOp1P3V2S': vectorRegElem('3'),
        'AA64FpOp1SV2S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1DV2S':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1QV2S':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOp1V3S':       vectorReg('(op1+3)%32',
    {
        'AA64FpOp1P0V3S': vectorRegElem('0'),
        'AA64FpOp1P1V3S': vectorRegElem('1'),
        'AA64FpOp1P2V3S': vectorRegElem('2'),
        'AA64FpOp1P3V3S': vectorRegElem('3'),
        'AA64FpOp1SV3S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOp1DV3S':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOp1QV3S':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpDestV0':       vectorReg('(dest+0)',
    {
        'AA64FpDestP0V0': vectorRegElem('0'),
        'AA64FpDestP1V0': vectorRegElem('1'),
        'AA64FpDestP2V0': vectorRegElem('2'),
        'AA64FpDestP3V0': vectorRegElem('3'),
        'AA64FpDestSV0':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpDestDV0':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpDestQV0':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpDestV1':       vectorReg('(dest+1)',
    {
        'AA64FpDestP0V1': vectorRegElem('0'),
        'AA64FpDestP1V1': vectorRegElem('1'),
        'AA64FpDestP2V1': vectorRegElem('2'),
        'AA64FpDestP3V1': vectorRegElem('3'),
        'AA64FpDestSV1':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpDestDV1':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpDestQV1':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpDestV0L':       vectorReg('(dest+0)%32',
    {
        'AA64FpDestP0V0L': vectorRegElem('0'),
        'AA64FpDestP1V0L': vectorRegElem('1'),
        'AA64FpDestP2V0L': vectorRegElem('2'),
        'AA64FpDestP3V0L': vectorRegElem('3'),
        'AA64FpDestSV0L':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpDestDV0L':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpDestQV0L':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpDestV1L':       vectorReg('(dest+1)%32',
    {
        'AA64FpDestP0V1L': vectorRegElem('0'),
        'AA64FpDestP1V1L': vectorRegElem('1'),
        'AA64FpDestP2V1L': vectorRegElem('2'),
        'AA64FpDestP3V1L': vectorRegElem('3'),
        'AA64FpDestSV1L':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpDestDV1L':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpDestQV1L':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    # Temporary registers for SVE interleaving
    'AA64IntrlvReg0': vectorReg('INTRLVREG0',
    {
        'AA64IntrlvReg0P0': vectorRegElem('0'),
        'AA64IntrlvReg0P1': vectorRegElem('1'),
        'AA64IntrlvReg0P2': vectorRegElem('2'),
        'AA64IntrlvReg0P3': vectorRegElem('3'),
        'AA64IntrlvReg0S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64IntrlvReg0D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64IntrlvReg0Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64IntrlvReg1': vectorReg('INTRLVREG1',
    {
        'AA64IntrlvReg1P0': vectorRegElem('0'),
        'AA64IntrlvReg1P1': vectorRegElem('1'),
        'AA64IntrlvReg1P2': vectorRegElem('2'),
        'AA64IntrlvReg1P3': vectorRegElem('3'),
        'AA64IntrlvReg1S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64IntrlvReg1D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64IntrlvReg1Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64IntrlvReg2': vectorReg('INTRLVREG2',
    {
        'AA64IntrlvReg2P0': vectorRegElem('0'),
        'AA64IntrlvReg2P1': vectorRegElem('1'),
        'AA64IntrlvReg2P2': vectorRegElem('2'),
        'AA64IntrlvReg2P3': vectorRegElem('3'),
        'AA64IntrlvReg2S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64IntrlvReg2D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64IntrlvReg2Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64IntrlvReg3': vectorReg('INTRLVREG3',
    {
        'AA64IntrlvReg3P0': vectorRegElem('0'),
        'AA64IntrlvReg3P1': vectorRegElem('1'),
        'AA64IntrlvReg3P2': vectorRegElem('2'),
        'AA64IntrlvReg3P3': vectorRegElem('3'),
        'AA64IntrlvReg3S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64IntrlvReg3D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64IntrlvReg3Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpDestMerge':       vectorReg('dest',
    {
        'AA64FpDestMergeP0': vectorRegElem('0'),
        'AA64FpDestMergeP1': vectorRegElem('1'),
        'AA64FpDestMergeP2': vectorRegElem('2'),
        'AA64FpDestMergeP3': vectorRegElem('3'),
        'AA64FpDestMergeS':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpDestMergeD':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpDestMergeQ':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpBase': vectorReg('base',
    {
        'AA64FpBaseP0': vectorRegElem('0'),
        'AA64FpBaseP1': vectorRegElem('1'),
        'AA64FpBaseP2': vectorRegElem('2'),
        'AA64FpBaseP3': vectorRegElem('3'),
        'AA64FpBaseS':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpBaseD':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpBaseQ':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpOffset': vectorReg('offset',
    {
        'AA64FpOffsetP0': vectorRegElem('0'),
        'AA64FpOffsetP1': vectorRegElem('1'),
        'AA64FpOffsetP2': vectorRegElem('2'),
        'AA64FpOffsetP3': vectorRegElem('3'),
        'AA64FpOffsetS':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpOffsetD':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpOffsetQ':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    'AA64FpUreg0': vectorReg('VECREG_UREG0',
    {
        'AA64FpUreg0P0': vectorRegElem('0'),
        'AA64FpUreg0P1': vectorRegElem('1'),
        'AA64FpUreg0P2': vectorRegElem('2'),
        'AA64FpUreg0P3': vectorRegElem('3'),
        'AA64FpUreg0S':  vectorRegElem('0', 'sf', zeroing = True),
        'AA64FpUreg0D':  vectorRegElem('0', 'df', zeroing = True),
        'AA64FpUreg0Q':  vectorRegElem('0', 'tud', zeroing = True)
    }),

    # Predicate register operands
    'GpOp': vecPredReg('gp'),
    'POp1': vecPredReg('op1'),
    'POp2': vecPredReg('op2'),
    'PDest': vecPredReg('dest'),
    'PDestMerge': vecPredReg('dest'),
    'Ffr': vecPredReg('PREDREG_FFR'),
    'FfrAux': vecPredReg('PREDREG_FFR'),
    'PUreg0': vecPredReg('PREDREG_UREG0'),

    #Abstracted control reg operands
    'MiscDest': cntrlReg('dest'),
    'MiscOp1': cntrlReg('op1'),
    'MiscNsBankedDest': cntrlNsBankedReg('dest'),
    'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
    'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
    'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),

    #Fixed index control regs
    'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
    'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
    'Spsr': cntrlRegNC('MISCREG_SPSR'),
    'Fpsr': cntrlRegNC('MISCREG_FPSR'),
    'Fpsid': cntrlRegNC('MISCREG_FPSID'),
    'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
    'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
    'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
    'Cpacr': cntrlReg('MISCREG_CPACR'),
    'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
    'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
    'Nsacr': cntrlReg('MISCREG_NSACR'),
    'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
    'Hcr': cntrlReg('MISCREG_HCR'),
    'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
    'Hdcr': cntrlReg('MISCREG_HDCR'),
    'Hcptr': cntrlReg('MISCREG_HCPTR'),
    'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
    'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
    'Hstr': cntrlReg('MISCREG_HSTR'),
    'Scr': cntrlReg('MISCREG_SCR'),
    'Scr64': cntrlReg('MISCREG_SCR_EL3'),
    'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
    'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
    'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
    'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),

    #Register fields for microops
    'URa' : intReg('ura'),
    'XURa' : intRegX64('ura'),
    'WURa' : intRegW64('ura'),
    'IWRa' : intRegIWPC('ura'),
    'Fa' : vectorElem('ura / 4', 'ura % 4'),
    'URb' : intReg('urb'),
    'XURb' : intRegX64('urb'),
    'URc' : intReg('urc'),
    'XURc' : intRegX64('urc'),

    #Memory Operand
    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),

    #PCState fields
    'RawPC': pcStateReg('pc', srtPC),
    'PC': pcStateReg('instPC', srtPC),
    'NPC': pcStateReg('instNPC', srtPC),
    'pNPC': pcStateReg('instNPC', srtEPC),
    'IWNPC': pcStateReg('instIWNPC', srtPC),
    'Thumb': pcStateReg('thumb', srtPC),
    'NextThumb': pcStateReg('nextThumb', srtMode),
    'NextJazelle': pcStateReg('nextJazelle', srtMode),
    'NextItState': pcStateReg('nextItstate', srtMode),
    'Itstate': pcStateReg('itstate', srtMode),
    'NextAArch64': pcStateReg('nextAArch64', srtMode),

    #Register operands depending on a field in the instruction encoding. These
    #should be avoided since they may not be portable across different
    #encodings of the same instruction.
    'Rd': intReg('RD'),
    'Rm': intReg('RM'),
    'Rs': intReg('RS'),
    'Rn': intReg('RN'),
    'Rt': intReg('RT')
}};