operands.isa revision 14108 
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39//
40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : 'int8_t',
44    'ub' : 'uint8_t',
45    'sh' : 'int16_t',
46    'uh' : 'uint16_t',
47    'sw' : 'int32_t',
48    'uw' : 'uint32_t',
49    'sd' : 'int64_t',
50    'ud' : 'uint64_t',
51    'sq' : '__int128_t',
52    'uq' : '__uint128_t',
53    'tud' : 'std::array<uint64_t, 2>',
54    'sf' : 'float',
55    'df' : 'double',
56    'vc' : 'ArmISA::VecRegContainer',
57    # For operations that are implemented as a template
58    'x' : 'TPElem',
59    'xs' : 'TPSElem',
60    'xd' : 'TPDElem',
61    'pc' : 'ArmISA::VecPredRegContainer',
62    'pb' : 'uint8_t'
63}};
64
65let {{
66    maybePCRead = '''
67        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
68    '''
69    maybeAlignedPCRead = '''
70        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
71         xc->%(func)s(this, %(op_idx)s))
72    '''
73    maybePCWrite = '''
74        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
75         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
76    '''
77    maybeIWPCWrite = '''
78        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
79         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
80    '''
81    maybeAIWPCWrite = '''
82        if (%(reg_idx)s == PCReg) {
83            bool thumb = THUMB;
84            if (thumb) {
85                setNextPC(xc, %(final_val)s);
86            } else {
87                setIWNextPC(xc, %(final_val)s);
88            }
89        } else {
90            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
91        }
92    '''
93    aarch64Read = '''
94        ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
95    '''
96    aarch64Write = '''
97        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
98    '''
99    aarchX64Read = '''
100        ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
101    '''
102    aarchX64Write = '''
103        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
104    '''
105    aarchW64Read = '''
106        ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
107    '''
108    aarchW64Write = '''
109        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
110    '''
111    cntrlNsBankedWrite = '''
112        xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
113    '''
114
115    cntrlNsBankedRead = '''
116        xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
117    '''
118
119    #PCState operands need to have a sorting index (the number at the end)
120    #less than all the integer registers which might update the PC. That way
121    #if the flag bits of the pc state are updated and a branch happens through
122    #R15, the updates are layered properly and the R15 update isn't lost.
123    srtNormal = 5
124    srtCpsr = 4
125    srtBase = 3
126    srtPC = 2
127    srtMode = 1
128    srtEPC = 0
129
130    def vectorElem(idx, elem):
131        return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
132
133    def vectorReg(idx, elems = None):
134        return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
135
136    def vectorRegElem(elem, ext = 'sf', zeroing = False):
137        return (elem, ext, zeroing)
138
139    def vecPredReg(idx):
140        return ('VecPredReg', 'pc', idx, None, srtNormal)
141
142    def intReg(idx):
143        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
144                maybePCRead, maybePCWrite)
145
146    def intReg64(idx):
147        return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
148                aarch64Read, aarch64Write)
149
150    def intRegX64(idx, id = srtNormal):
151        return ('IntReg', 'ud', idx, 'IsInteger', id,
152                aarchX64Read, aarchX64Write)
153
154    def intRegW64(idx, id = srtNormal):
155        return ('IntReg', 'ud', idx, 'IsInteger', id,
156                aarchW64Read, aarchW64Write)
157
158    def intRegNPC(idx):
159        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
160
161    def intRegAPC(idx, id = srtNormal):
162        return ('IntReg', 'uw', idx, 'IsInteger', id,
163                maybeAlignedPCRead, maybePCWrite)
164
165    def intRegIWPC(idx):
166        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
167                maybePCRead, maybeIWPCWrite)
168
169    def intRegAIWPC(idx):
170        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
171                maybePCRead, maybeAIWPCWrite)
172
173    def ccReg(idx):
174        return ('CCReg', 'uw', idx, None, srtNormal)
175
176    def cntrlReg(idx, id = srtNormal, type = 'uw'):
177        return ('ControlReg', type, idx, None, id)
178
179    def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
180        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
181
182    def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
183        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
184
185    def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
186        return ('ControlReg', type, idx, None, id)
187
188    def pcStateReg(idx, id):
189        return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
190}};
191
192def operands {{
193    #Abstracted integer reg operands
194    'Dest': intReg('dest'),
195    'Dest64': intReg64('dest'),
196    'XDest': intRegX64('dest'),
197    'WDest': intRegW64('dest'),
198    'IWDest': intRegIWPC('dest'),
199    'AIWDest': intRegAIWPC('dest'),
200    'Dest2': intReg('dest2'),
201    'XDest2': intRegX64('dest2'),
202    'IWDest2': intRegIWPC('dest2'),
203    'Result': intReg('result'),
204    'XResult': intRegX64('result'),
205    'XBase': intRegX64('base', id = srtBase),
206    'Base': intRegAPC('base', id = srtBase),
207    'XOffset': intRegX64('offset'),
208    'Index': intReg('index'),
209    'Shift': intReg('shift'),
210    'Op1': intReg('op1'),
211    'Op2': intReg('op2'),
212    'Op3': intReg('op3'),
213    'Op164': intReg64('op1'),
214    'Op264': intReg64('op2'),
215    'Op364': intReg64('op3'),
216    'XOp1': intRegX64('op1'),
217    'XOp2': intRegX64('op2'),
218    'XOp3': intRegX64('op3'),
219    'WOp1': intRegW64('op1'),
220    'WOp2': intRegW64('op2'),
221    'WOp3': intRegW64('op3'),
222    'Reg0': intReg('reg0'),
223    'Reg1': intReg('reg1'),
224    'Reg2': intReg('reg2'),
225    'Reg3': intReg('reg3'),
226
227    #Fixed index integer reg operands
228    'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
229    'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
230    'LR': intRegNPC('INTREG_LR'),
231    'XLR': intRegX64('INTREG_X30'),
232    'R7': intRegNPC('7'),
233    # First four arguments are passed in registers
234    'R0': intRegNPC('0'),
235    'R1': intRegNPC('1'),
236    'R2': intRegNPC('2'),
237    'R3': intRegNPC('3'),
238    'X0': intRegX64('0'),
239    'X1': intRegX64('1'),
240    'X2': intRegX64('2'),
241    'X3': intRegX64('3'),
242
243    # Condition code registers
244    'CondCodesNZ': ccReg('CCREG_NZ'),
245    'CondCodesC': ccReg('CCREG_C'),
246    'CondCodesV': ccReg('CCREG_V'),
247    'CondCodesGE': ccReg('CCREG_GE'),
248    'OptCondCodesNZ': ccReg(
249            '''((condCode == COND_AL || condCode == COND_UC ||
250                 condCode == COND_CC || condCode == COND_CS ||
251                 condCode == COND_VS || condCode == COND_VC) ?
252                CCREG_ZERO : CCREG_NZ)'''),
253    'OptCondCodesC': ccReg(
254             '''((condCode == COND_HI || condCode == COND_LS ||
255                condCode == COND_CS || condCode == COND_CC) ?
256               CCREG_C : CCREG_ZERO)'''),
257    'OptShiftRmCondCodesC': ccReg(
258            '''((condCode == COND_HI || condCode == COND_LS ||
259                 condCode == COND_CS || condCode == COND_CC ||
260                 shiftType == ROR) ?
261                CCREG_C : CCREG_ZERO)'''),
262    'OptCondCodesV': ccReg(
263            '''((condCode == COND_VS || condCode == COND_VC ||
264                 condCode == COND_GE || condCode == COND_LT ||
265                 condCode == COND_GT || condCode == COND_LE) ?
266                CCREG_V : CCREG_ZERO)'''),
267    'FpCondCodes': ccReg('CCREG_FP'),
268
269    #Abstracted floating point reg operands
270    'FpDest': vectorElem('dest / 4', 'dest % 4'),
271    'FpDestP0': vectorElem('(dest + 0) / 4', '(dest + 0) % 4'),
272    'FpDestP1': vectorElem('(dest + 1) / 4', '(dest + 1) % 4'),
273    'FpDestP2': vectorElem('(dest + 2) / 4', '(dest + 2) % 4'),
274    'FpDestP3': vectorElem('(dest + 3) / 4', '(dest + 3) % 4'),
275    'FpDestP4': vectorElem('(dest + 4) / 4', '(dest + 4) % 4'),
276    'FpDestP5': vectorElem('(dest + 5) / 4', '(dest + 5) % 4'),
277    'FpDestP6': vectorElem('(dest + 6) / 4', '(dest + 6) % 4'),
278    'FpDestP7': vectorElem('(dest + 7) / 4', '(dest + 7) % 4'),
279
280    'FpDestS0P0': vectorElem(
281        '(dest + step * 0 + 0) / 4', '(dest + step * 0 + 0) % 4'),
282    'FpDestS0P1': vectorElem(
283        '(dest + step * 0 + 1) / 4', '(dest + step * 0 + 1) % 4'),
284    'FpDestS1P0': vectorElem(
285        '(dest + step * 1 + 0) / 4', '(dest + step * 1 + 0) % 4'),
286    'FpDestS1P1': vectorElem(
287        '(dest + step * 1 + 1) / 4', '(dest + step * 1 + 1) % 4'),
288    'FpDestS2P0': vectorElem(
289        '(dest + step * 2 + 0) / 4', '(dest + step * 2 + 0) % 4'),
290    'FpDestS2P1': vectorElem(
291        '(dest + step * 2 + 1) / 4', '(dest + step * 2 + 1) % 4'),
292    'FpDestS3P0': vectorElem(
293        '(dest + step * 3 + 0) / 4', '(dest + step * 3 + 0) % 4'),
294    'FpDestS3P1': vectorElem(
295        '(dest + step * 3 + 1) / 4', '(dest + step * 3 + 1) % 4'),
296
297    'FpDest2': vectorElem('dest2 / 4', 'dest2 % 4'),
298    'FpDest2P0': vectorElem('(dest2 + 0) / 4', '(dest2 + 0) % 4'),
299    'FpDest2P1': vectorElem('(dest2 + 1) / 4', '(dest2 + 1) % 4'),
300    'FpDest2P2': vectorElem('(dest2 + 2) / 4', '(dest2 + 2) % 4'),
301    'FpDest2P3': vectorElem('(dest2 + 3) / 4', '(dest2 + 3) % 4'),
302
303    'FpOp1': vectorElem('op1 / 4', 'op1 % 4'),
304    'FpOp1P0': vectorElem('(op1 + 0) / 4', '(op1 + 0) % 4'),
305    'FpOp1P1': vectorElem('(op1 + 1) / 4', '(op1 + 1) % 4'),
306    'FpOp1P2': vectorElem('(op1 + 2) / 4', '(op1 + 2) % 4'),
307    'FpOp1P3': vectorElem('(op1 + 3) / 4', '(op1 + 3) % 4'),
308    'FpOp1P4': vectorElem('(op1 + 4) / 4', '(op1 + 4) % 4'),
309    'FpOp1P5': vectorElem('(op1 + 5) / 4', '(op1 + 5) % 4'),
310    'FpOp1P6': vectorElem('(op1 + 6) / 4', '(op1 + 6) % 4'),
311    'FpOp1P7': vectorElem('(op1 + 7) / 4', '(op1 + 7) % 4'),
312
313    'FpOp1S0P0': vectorElem(
314        '(op1 + step * 0 + 0) / 4', '(op1 + step * 0 + 0) % 4'),
315    'FpOp1S0P1': vectorElem(
316        '(op1 + step * 0 + 1) / 4', '(op1 + step * 0 + 1) % 4'),
317    'FpOp1S1P0': vectorElem(
318        '(op1 + step * 1 + 0) / 4', '(op1 + step * 1 + 0) % 4'),
319    'FpOp1S1P1': vectorElem(
320        '(op1 + step * 1 + 1) / 4', '(op1 + step * 1 + 1) % 4'),
321    'FpOp1S2P0': vectorElem(
322        '(op1 + step * 2 + 0) / 4', '(op1 + step * 2 + 0) % 4'),
323    'FpOp1S2P1': vectorElem(
324        '(op1 + step * 2 + 1) / 4', '(op1 + step * 2 + 1) % 4'),
325    'FpOp1S3P0': vectorElem(
326        '(op1 + step * 3 + 0) / 4', '(op1 + step * 3 + 0) % 4'),
327    'FpOp1S3P1': vectorElem(
328        '(op1 + step * 3 + 1) / 4', '(op1 + step * 3 + 1) % 4'),
329
330    'FpOp2': vectorElem('op2 / 4', 'op2 % 4'),
331    'FpOp2P0': vectorElem('(op2 + 0) / 4', '(op2 + 0) % 4'),
332    'FpOp2P1': vectorElem('(op2 + 1) / 4', '(op2 + 1) % 4'),
333    'FpOp2P2': vectorElem('(op2 + 2) / 4', '(op2 + 2) % 4'),
334    'FpOp2P3': vectorElem('(op2 + 3) / 4', '(op2 + 3) % 4'),
335
336    # Create AArch64 unpacked view of the FP registers
337    # Name   ::= 'AA64Vec' OpSpec [LaneSpec]
338    # OpSpec ::= IOSpec [Index] [Plus]
339    # IOSpec ::= 'S' | 'D'
340    # Index  ::= '0' | ... | '9'
341    # Plus  ::= [PlusAmount] ['l']
342    # PlusAmount ::= 'p' [PlusAmount]
343    # LaneSpec ::= 'L' Index
344    #
345    # All the constituents are hierarchically defined as part of the Vector
346    # Register they belong to
347
348    'AA64FpOp1':       vectorReg('op1',
349    {
350        'AA64FpOp1P0': vectorRegElem('0'),
351        'AA64FpOp1P1': vectorRegElem('1'),
352        'AA64FpOp1P2': vectorRegElem('2'),
353        'AA64FpOp1P3': vectorRegElem('3'),
354        'AA64FpOp1S':  vectorRegElem('0', 'sf', zeroing = True),
355        'AA64FpOp1D':  vectorRegElem('0', 'df', zeroing = True),
356        'AA64FpOp1Q':  vectorRegElem('0', 'tud', zeroing = True)
357    }),
358
359    'AA64FpOp2':       vectorReg('op2',
360    {
361        'AA64FpOp2P0': vectorRegElem('0'),
362        'AA64FpOp2P1': vectorRegElem('1'),
363        'AA64FpOp2P2': vectorRegElem('2'),
364        'AA64FpOp2P3': vectorRegElem('3'),
365        'AA64FpOp2S':  vectorRegElem('0', 'sf', zeroing = True),
366        'AA64FpOp2D':  vectorRegElem('0', 'df', zeroing = True),
367        'AA64FpOp2Q':  vectorRegElem('0', 'tud', zeroing = True)
368    }),
369
370    'AA64FpOp3':       vectorReg('op3',
371    {
372        'AA64FpOp3P0': vectorRegElem('0'),
373        'AA64FpOp3P1': vectorRegElem('1'),
374        'AA64FpOp3P2': vectorRegElem('2'),
375        'AA64FpOp3P3': vectorRegElem('3'),
376        'AA64FpOp3S':  vectorRegElem('0', 'sf', zeroing = True),
377        'AA64FpOp3D':  vectorRegElem('0', 'df', zeroing = True),
378        'AA64FpOp3Q':  vectorRegElem('0', 'tud', zeroing = True)
379    }),
380
381    'AA64FpDest':       vectorReg('dest',
382    {
383        'AA64FpDestP0': vectorRegElem('0'),
384        'AA64FpDestP1': vectorRegElem('1'),
385        'AA64FpDestP2': vectorRegElem('2'),
386        'AA64FpDestP3': vectorRegElem('3'),
387        'AA64FpDestS':  vectorRegElem('0', 'sf', zeroing = True),
388        'AA64FpDestD':  vectorRegElem('0', 'df', zeroing = True),
389        'AA64FpDestQ':  vectorRegElem('0', 'tud', zeroing = True)
390    }),
391
392    'AA64FpDest2':       vectorReg('dest2',
393    {
394        'AA64FpDest2P0': vectorRegElem('0'),
395        'AA64FpDest2P1': vectorRegElem('1'),
396        'AA64FpDest2P2': vectorRegElem('2'),
397        'AA64FpDest2P3': vectorRegElem('3'),
398        'AA64FpDest2S':  vectorRegElem('0', 'sf', zeroing = True),
399        'AA64FpDest2D':  vectorRegElem('0', 'df', zeroing = True),
400        'AA64FpDest2Q':  vectorRegElem('0', 'tud', zeroing = True)
401    }),
402
403    'AA64FpOp1V0':       vectorReg('op1',
404    {
405        'AA64FpOp1P0V0': vectorRegElem('0'),
406        'AA64FpOp1P1V0': vectorRegElem('1'),
407        'AA64FpOp1P2V0': vectorRegElem('2'),
408        'AA64FpOp1P3V0': vectorRegElem('3'),
409        'AA64FpOp1SV0':  vectorRegElem('0', 'sf', zeroing = True),
410        'AA64FpOp1DV0':  vectorRegElem('0', 'df', zeroing = True),
411        'AA64FpOp1QV0':  vectorRegElem('0', 'tud', zeroing = True)
412    }),
413
414    'AA64FpOp1V1':       vectorReg('op1+1',
415    {
416        'AA64FpOp1P0V1': vectorRegElem('0'),
417        'AA64FpOp1P1V1': vectorRegElem('1'),
418        'AA64FpOp1P2V1': vectorRegElem('2'),
419        'AA64FpOp1P3V1': vectorRegElem('3'),
420        'AA64FpOp1SV1':  vectorRegElem('0', 'sf', zeroing = True),
421        'AA64FpOp1DV1':  vectorRegElem('0', 'df', zeroing = True),
422        'AA64FpOp1QV1':  vectorRegElem('0', 'tud', zeroing = True)
423    }),
424
425    'AA64FpOp1V2':       vectorReg('op1+2',
426    {
427        'AA64FpOp1P0V2': vectorRegElem('0'),
428        'AA64FpOp1P1V2': vectorRegElem('1'),
429        'AA64FpOp1P2V2': vectorRegElem('2'),
430        'AA64FpOp1P3V2': vectorRegElem('3'),
431        'AA64FpOp1SV2':  vectorRegElem('0', 'sf', zeroing = True),
432        'AA64FpOp1DV2':  vectorRegElem('0', 'df', zeroing = True),
433        'AA64FpOp1QV2':  vectorRegElem('0', 'tud', zeroing = True)
434    }),
435
436    'AA64FpOp1V3':       vectorReg('op1+3',
437    {
438        'AA64FpOp1P0V3': vectorRegElem('0'),
439        'AA64FpOp1P1V3': vectorRegElem('1'),
440        'AA64FpOp1P2V3': vectorRegElem('2'),
441        'AA64FpOp1P3V3': vectorRegElem('3'),
442        'AA64FpOp1SV3':  vectorRegElem('0', 'sf', zeroing = True),
443        'AA64FpOp1DV3':  vectorRegElem('0', 'df', zeroing = True),
444        'AA64FpOp1QV3':  vectorRegElem('0', 'tud', zeroing = True)
445    }),
446
447    'AA64FpOp1V0S':       vectorReg('(op1+0)%32',
448    {
449        'AA64FpOp1P0V0S': vectorRegElem('0'),
450        'AA64FpOp1P1V0S': vectorRegElem('1'),
451        'AA64FpOp1P2V0S': vectorRegElem('2'),
452        'AA64FpOp1P3V0S': vectorRegElem('3'),
453        'AA64FpOp1SV0S':  vectorRegElem('0', 'sf', zeroing = True),
454        'AA64FpOp1DV0S':  vectorRegElem('0', 'df', zeroing = True),
455        'AA64FpOp1QV0S':  vectorRegElem('0', 'tud', zeroing = True)
456    }),
457
458    'AA64FpOp1V1S':       vectorReg('(op1+1)%32',
459    {
460        'AA64FpOp1P0V1S': vectorRegElem('0'),
461        'AA64FpOp1P1V1S': vectorRegElem('1'),
462        'AA64FpOp1P2V1S': vectorRegElem('2'),
463        'AA64FpOp1P3V1S': vectorRegElem('3'),
464        'AA64FpOp1SV1S':  vectorRegElem('0', 'sf', zeroing = True),
465        'AA64FpOp1DV1S':  vectorRegElem('0', 'df', zeroing = True),
466        'AA64FpOp1QV1S':  vectorRegElem('0', 'tud', zeroing = True)
467    }),
468
469    'AA64FpOp1V2S':       vectorReg('(op1+2)%32',
470    {
471        'AA64FpOp1P0V2S': vectorRegElem('0'),
472        'AA64FpOp1P1V2S': vectorRegElem('1'),
473        'AA64FpOp1P2V2S': vectorRegElem('2'),
474        'AA64FpOp1P3V2S': vectorRegElem('3'),
475        'AA64FpOp1SV2S':  vectorRegElem('0', 'sf', zeroing = True),
476        'AA64FpOp1DV2S':  vectorRegElem('0', 'df', zeroing = True),
477        'AA64FpOp1QV2S':  vectorRegElem('0', 'tud', zeroing = True)
478    }),
479
480    'AA64FpOp1V3S':       vectorReg('(op1+3)%32',
481    {
482        'AA64FpOp1P0V3S': vectorRegElem('0'),
483        'AA64FpOp1P1V3S': vectorRegElem('1'),
484        'AA64FpOp1P2V3S': vectorRegElem('2'),
485        'AA64FpOp1P3V3S': vectorRegElem('3'),
486        'AA64FpOp1SV3S':  vectorRegElem('0', 'sf', zeroing = True),
487        'AA64FpOp1DV3S':  vectorRegElem('0', 'df', zeroing = True),
488        'AA64FpOp1QV3S':  vectorRegElem('0', 'tud', zeroing = True)
489    }),
490
491    'AA64FpDestV0':       vectorReg('(dest+0)',
492    {
493        'AA64FpDestP0V0': vectorRegElem('0'),
494        'AA64FpDestP1V0': vectorRegElem('1'),
495        'AA64FpDestP2V0': vectorRegElem('2'),
496        'AA64FpDestP3V0': vectorRegElem('3'),
497        'AA64FpDestSV0':  vectorRegElem('0', 'sf', zeroing = True),
498        'AA64FpDestDV0':  vectorRegElem('0', 'df', zeroing = True),
499        'AA64FpDestQV0':  vectorRegElem('0', 'tud', zeroing = True)
500    }),
501
502    'AA64FpDestV1':       vectorReg('(dest+1)',
503    {
504        'AA64FpDestP0V1': vectorRegElem('0'),
505        'AA64FpDestP1V1': vectorRegElem('1'),
506        'AA64FpDestP2V1': vectorRegElem('2'),
507        'AA64FpDestP3V1': vectorRegElem('3'),
508        'AA64FpDestSV1':  vectorRegElem('0', 'sf', zeroing = True),
509        'AA64FpDestDV1':  vectorRegElem('0', 'df', zeroing = True),
510        'AA64FpDestQV1':  vectorRegElem('0', 'tud', zeroing = True)
511    }),
512
513    'AA64FpDestV0L':       vectorReg('(dest+0)%32',
514    {
515        'AA64FpDestP0V0L': vectorRegElem('0'),
516        'AA64FpDestP1V0L': vectorRegElem('1'),
517        'AA64FpDestP2V0L': vectorRegElem('2'),
518        'AA64FpDestP3V0L': vectorRegElem('3'),
519        'AA64FpDestSV0L':  vectorRegElem('0', 'sf', zeroing = True),
520        'AA64FpDestDV0L':  vectorRegElem('0', 'df', zeroing = True),
521        'AA64FpDestQV0L':  vectorRegElem('0', 'tud', zeroing = True)
522    }),
523
524    'AA64FpDestV1L':       vectorReg('(dest+1)%32',
525    {
526        'AA64FpDestP0V1L': vectorRegElem('0'),
527        'AA64FpDestP1V1L': vectorRegElem('1'),
528        'AA64FpDestP2V1L': vectorRegElem('2'),
529        'AA64FpDestP3V1L': vectorRegElem('3'),
530        'AA64FpDestSV1L':  vectorRegElem('0', 'sf', zeroing = True),
531        'AA64FpDestDV1L':  vectorRegElem('0', 'df', zeroing = True),
532        'AA64FpDestQV1L':  vectorRegElem('0', 'tud', zeroing = True)
533    }),
534
535    # Temporary registers for SVE interleaving
536    'AA64IntrlvReg0': vectorReg('INTRLVREG0',
537    {
538        'AA64IntrlvReg0P0': vectorRegElem('0'),
539        'AA64IntrlvReg0P1': vectorRegElem('1'),
540        'AA64IntrlvReg0P2': vectorRegElem('2'),
541        'AA64IntrlvReg0P3': vectorRegElem('3'),
542        'AA64IntrlvReg0S':  vectorRegElem('0', 'sf', zeroing = True),
543        'AA64IntrlvReg0D':  vectorRegElem('0', 'df', zeroing = True),
544        'AA64IntrlvReg0Q':  vectorRegElem('0', 'tud', zeroing = True)
545    }),
546
547    'AA64IntrlvReg1': vectorReg('INTRLVREG1',
548    {
549        'AA64IntrlvReg1P0': vectorRegElem('0'),
550        'AA64IntrlvReg1P1': vectorRegElem('1'),
551        'AA64IntrlvReg1P2': vectorRegElem('2'),
552        'AA64IntrlvReg1P3': vectorRegElem('3'),
553        'AA64IntrlvReg1S':  vectorRegElem('0', 'sf', zeroing = True),
554        'AA64IntrlvReg1D':  vectorRegElem('0', 'df', zeroing = True),
555        'AA64IntrlvReg1Q':  vectorRegElem('0', 'tud', zeroing = True)
556    }),
557
558    'AA64IntrlvReg2': vectorReg('INTRLVREG2',
559    {
560        'AA64IntrlvReg2P0': vectorRegElem('0'),
561        'AA64IntrlvReg2P1': vectorRegElem('1'),
562        'AA64IntrlvReg2P2': vectorRegElem('2'),
563        'AA64IntrlvReg2P3': vectorRegElem('3'),
564        'AA64IntrlvReg2S':  vectorRegElem('0', 'sf', zeroing = True),
565        'AA64IntrlvReg2D':  vectorRegElem('0', 'df', zeroing = True),
566        'AA64IntrlvReg2Q':  vectorRegElem('0', 'tud', zeroing = True)
567    }),
568
569    'AA64IntrlvReg3': vectorReg('INTRLVREG3',
570    {
571        'AA64IntrlvReg3P0': vectorRegElem('0'),
572        'AA64IntrlvReg3P1': vectorRegElem('1'),
573        'AA64IntrlvReg3P2': vectorRegElem('2'),
574        'AA64IntrlvReg3P3': vectorRegElem('3'),
575        'AA64IntrlvReg3S':  vectorRegElem('0', 'sf', zeroing = True),
576        'AA64IntrlvReg3D':  vectorRegElem('0', 'df', zeroing = True),
577        'AA64IntrlvReg3Q':  vectorRegElem('0', 'tud', zeroing = True)
578    }),
579
580    'AA64FpDestMerge':       vectorReg('dest',
581    {
582        'AA64FpDestMergeP0': vectorRegElem('0'),
583        'AA64FpDestMergeP1': vectorRegElem('1'),
584        'AA64FpDestMergeP2': vectorRegElem('2'),
585        'AA64FpDestMergeP3': vectorRegElem('3'),
586        'AA64FpDestMergeS':  vectorRegElem('0', 'sf', zeroing = True),
587        'AA64FpDestMergeD':  vectorRegElem('0', 'df', zeroing = True),
588        'AA64FpDestMergeQ':  vectorRegElem('0', 'tud', zeroing = True)
589    }),
590
591    'AA64FpBase': vectorReg('base',
592    {
593        'AA64FpBaseP0': vectorRegElem('0'),
594        'AA64FpBaseP1': vectorRegElem('1'),
595        'AA64FpBaseP2': vectorRegElem('2'),
596        'AA64FpBaseP3': vectorRegElem('3'),
597        'AA64FpBaseS':  vectorRegElem('0', 'sf', zeroing = True),
598        'AA64FpBaseD':  vectorRegElem('0', 'df', zeroing = True),
599        'AA64FpBaseQ':  vectorRegElem('0', 'tud', zeroing = True)
600    }),
601
602    'AA64FpOffset': vectorReg('offset',
603    {
604        'AA64FpOffsetP0': vectorRegElem('0'),
605        'AA64FpOffsetP1': vectorRegElem('1'),
606        'AA64FpOffsetP2': vectorRegElem('2'),
607        'AA64FpOffsetP3': vectorRegElem('3'),
608        'AA64FpOffsetS':  vectorRegElem('0', 'sf', zeroing = True),
609        'AA64FpOffsetD':  vectorRegElem('0', 'df', zeroing = True),
610        'AA64FpOffsetQ':  vectorRegElem('0', 'tud', zeroing = True)
611    }),
612
613    'AA64FpUreg0': vectorReg('VECREG_UREG0',
614    {
615        'AA64FpUreg0P0': vectorRegElem('0'),
616        'AA64FpUreg0P1': vectorRegElem('1'),
617        'AA64FpUreg0P2': vectorRegElem('2'),
618        'AA64FpUreg0P3': vectorRegElem('3'),
619        'AA64FpUreg0S':  vectorRegElem('0', 'sf', zeroing = True),
620        'AA64FpUreg0D':  vectorRegElem('0', 'df', zeroing = True),
621        'AA64FpUreg0Q':  vectorRegElem('0', 'tud', zeroing = True)
622    }),
623
624    # Predicate register operands
625    'GpOp': vecPredReg('gp'),
626    'POp1': vecPredReg('op1'),
627    'POp2': vecPredReg('op2'),
628    'PDest': vecPredReg('dest'),
629    'PDestMerge': vecPredReg('dest'),
630    'Ffr': vecPredReg('PREDREG_FFR'),
631    'FfrAux': vecPredReg('PREDREG_FFR'),
632    'PUreg0': vecPredReg('PREDREG_UREG0'),
633
634    #Abstracted control reg operands
635    'MiscDest': cntrlReg('dest'),
636    'MiscOp1': cntrlReg('op1'),
637    'MiscNsBankedDest': cntrlNsBankedReg('dest'),
638    'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
639    'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
640    'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
641
642    #Fixed index control regs
643    'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
644    'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
645    'Spsr': cntrlRegNC('MISCREG_SPSR'),
646    'Fpsr': cntrlRegNC('MISCREG_FPSR'),
647    'Fpsid': cntrlRegNC('MISCREG_FPSID'),
648    'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
649    'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
650    'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
651    'Cpacr': cntrlReg('MISCREG_CPACR'),
652    'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
653    'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
654    'Nsacr': cntrlReg('MISCREG_NSACR'),
655    'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
656    'Hcr': cntrlReg('MISCREG_HCR'),
657    'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
658    'Hdcr': cntrlReg('MISCREG_HDCR'),
659    'Hcptr': cntrlReg('MISCREG_HCPTR'),
660    'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
661    'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
662    'Hstr': cntrlReg('MISCREG_HSTR'),
663    'Scr': cntrlReg('MISCREG_SCR'),
664    'Scr64': cntrlReg('MISCREG_SCR_EL3'),
665    'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
666    'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
667    'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
668    'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
669
670    #Register fields for microops
671    'URa' : intReg('ura'),
672    'XURa' : intRegX64('ura'),
673    'WURa' : intRegW64('ura'),
674    'IWRa' : intRegIWPC('ura'),
675    'Fa' : vectorElem('ura / 4', 'ura % 4'),
676    'URb' : intReg('urb'),
677    'XURb' : intRegX64('urb'),
678    'URc' : intReg('urc'),
679    'XURc' : intRegX64('urc'),
680
681    #Memory Operand
682    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
683
684    #PCState fields
685    'RawPC': pcStateReg('pc', srtPC),
686    'PC': pcStateReg('instPC', srtPC),
687    'NPC': pcStateReg('instNPC', srtPC),
688    'pNPC': pcStateReg('instNPC', srtEPC),
689    'IWNPC': pcStateReg('instIWNPC', srtPC),
690    'Thumb': pcStateReg('thumb', srtPC),
691    'NextThumb': pcStateReg('nextThumb', srtMode),
692    'NextJazelle': pcStateReg('nextJazelle', srtMode),
693    'NextItState': pcStateReg('nextItstate', srtMode),
694    'Itstate': pcStateReg('itstate', srtMode),
695    'NextAArch64': pcStateReg('nextAArch64', srtMode),
696
697    #Register operands depending on a field in the instruction encoding. These
698    #should be avoided since they may not be portable across different
699    #encodings of the same instruction.
700    'Rd': intReg('RD'),
701    'Rm': intReg('RM'),
702    'Rs': intReg('RS'),
703    'Rn': intReg('RN'),
704    'Rt': intReg('RT')
705}};
706