misc64.isa revision 12538
110037SARM gem5 Developers// -*- mode:c++ -*- 210037SARM gem5 Developers 312531Sandreas.sandberg@arm.com// Copyright (c) 2011-2013, 2016-2018 ARM Limited 410037SARM gem5 Developers// All rights reserved 510037SARM gem5 Developers// 610037SARM gem5 Developers// The license below extends only to copyright in the software and shall 710037SARM gem5 Developers// not be construed as granting a license to any other intellectual 810037SARM gem5 Developers// property including but not limited to intellectual property relating 910037SARM gem5 Developers// to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1410037SARM gem5 Developers// 1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2410037SARM gem5 Developers// this software without specific prior written permission. 2510037SARM gem5 Developers// 2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3710037SARM gem5 Developers// 3810037SARM gem5 Developers// Authors: Gabe Black 3910037SARM gem5 Developers 4010037SARM gem5 Developerslet {{ 4110037SARM gem5 Developers svcCode = ''' 4210474Sandreas.hansson@arm.com fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5)); 4310037SARM gem5 Developers ''' 4410037SARM gem5 Developers 4512538Sgiacomo.travaglini@arm.com svcIop = InstObjParams("svc", "Svc64", "ImmOp64", 4610037SARM gem5 Developers svcCode, ["IsSyscall", "IsNonSpeculative", 4710037SARM gem5 Developers "IsSerializeAfter"]) 4812538Sgiacomo.travaglini@arm.com header_output = ImmOp64Declare.subst(svcIop) 4912538Sgiacomo.travaglini@arm.com decoder_output = ImmOp64Constructor.subst(svcIop) 5010037SARM gem5 Developers exec_output = BasicExecute.subst(svcIop) 5110037SARM gem5 Developers 5211576SDylan.Johnson@ARM.com hvcCode = ''' 5311576SDylan.Johnson@ARM.com SCR scr = Scr64; 5411576SDylan.Johnson@ARM.com 5511576SDylan.Johnson@ARM.com if (!ArmSystem::haveVirtualization(xc->tcBase()) || 5612298Sgiacomo.travaglini@arm.com (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { 5711576SDylan.Johnson@ARM.com fault = disabledFault(); 5811576SDylan.Johnson@ARM.com } else { 5911576SDylan.Johnson@ARM.com fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5)); 6011576SDylan.Johnson@ARM.com } 6111576SDylan.Johnson@ARM.com ''' 6211576SDylan.Johnson@ARM.com 6312538Sgiacomo.travaglini@arm.com hvcIop = InstObjParams("hvc", "Hvc64", "ImmOp64", 6411576SDylan.Johnson@ARM.com hvcCode, ["IsSyscall", "IsNonSpeculative", 6511576SDylan.Johnson@ARM.com "IsSerializeAfter"]) 6612538Sgiacomo.travaglini@arm.com header_output += ImmOp64Declare.subst(hvcIop) 6712538Sgiacomo.travaglini@arm.com decoder_output += ImmOp64Constructor.subst(hvcIop) 6811576SDylan.Johnson@ARM.com exec_output += BasicExecute.subst(hvcIop) 6911576SDylan.Johnson@ARM.com 7010037SARM gem5 Developers # @todo: extend to take into account Virtualization. 7110037SARM gem5 Developers smcCode = ''' 7210037SARM gem5 Developers SCR scr = Scr64; 7310037SARM gem5 Developers CPSR cpsr = Cpsr; 7410037SARM gem5 Developers 7510037SARM gem5 Developers if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) { 7610037SARM gem5 Developers fault = disabledFault(); 7710037SARM gem5 Developers } else { 7810474Sandreas.hansson@arm.com fault = std::make_shared<SecureMonitorCall>(machInst); 7910037SARM gem5 Developers } 8010037SARM gem5 Developers ''' 8110037SARM gem5 Developers 8212538Sgiacomo.travaglini@arm.com smcIop = InstObjParams("smc", "Smc64", "ImmOp64", 8310037SARM gem5 Developers smcCode, ["IsNonSpeculative", "IsSerializeAfter"]) 8412538Sgiacomo.travaglini@arm.com header_output += ImmOp64Declare.subst(smcIop) 8512538Sgiacomo.travaglini@arm.com decoder_output += ImmOp64Constructor.subst(smcIop) 8610037SARM gem5 Developers exec_output += BasicExecute.subst(smcIop) 8710037SARM gem5 Developers 8810037SARM gem5 Developers def subst(templateBase, iop): 8910037SARM gem5 Developers global header_output, decoder_output, exec_output 9010037SARM gem5 Developers header_output += eval(templateBase + "Declare").subst(iop) 9110037SARM gem5 Developers decoder_output += eval(templateBase + "Constructor").subst(iop) 9210037SARM gem5 Developers exec_output += BasicExecute.subst(iop) 9310037SARM gem5 Developers 9410037SARM gem5 Developers bfmMaskCode = ''' 9510037SARM gem5 Developers uint64_t bitMask; 9610037SARM gem5 Developers int diff = imm2 - imm1; 9710037SARM gem5 Developers if (imm1 <= imm2) { 9810037SARM gem5 Developers bitMask = mask(diff + 1); 9910037SARM gem5 Developers } else { 10010037SARM gem5 Developers bitMask = mask(imm2 + 1); 10110037SARM gem5 Developers bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1)); 10210037SARM gem5 Developers diff += intWidth; 10310037SARM gem5 Developers } 10410037SARM gem5 Developers uint64_t topBits M5_VAR_USED = ~mask(diff+1); 10510537Sandreas.hansson@arm.com uint64_t result = imm1 == 0 ? Op164 : 10610537Sandreas.hansson@arm.com (Op164 >> imm1) | (Op164 << (intWidth - imm1)); 10710037SARM gem5 Developers result &= bitMask; 10810037SARM gem5 Developers ''' 10910037SARM gem5 Developers 11010037SARM gem5 Developers bfmCode = bfmMaskCode + 'Dest64 = result | (Dest64 & ~bitMask);' 11110037SARM gem5 Developers bfmIop = InstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode); 11210037SARM gem5 Developers subst("RegRegImmImmOp64", bfmIop) 11310037SARM gem5 Developers 11410037SARM gem5 Developers ubfmCode = bfmMaskCode + 'Dest64 = result;' 11510037SARM gem5 Developers ubfmIop = InstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode); 11610037SARM gem5 Developers subst("RegRegImmImmOp64", ubfmIop) 11710037SARM gem5 Developers 11810037SARM gem5 Developers sbfmCode = bfmMaskCode + \ 11910037SARM gem5 Developers 'Dest64 = result | (bits(Op164, imm2) ? topBits : 0);' 12010037SARM gem5 Developers sbfmIop = InstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode); 12110037SARM gem5 Developers subst("RegRegImmImmOp64", sbfmIop) 12210037SARM gem5 Developers 12310037SARM gem5 Developers extrCode = ''' 12410037SARM gem5 Developers if (imm == 0) { 12510037SARM gem5 Developers Dest64 = Op264; 12610037SARM gem5 Developers } else { 12710037SARM gem5 Developers Dest64 = (Op164 << (intWidth - imm)) | (Op264 >> imm); 12810037SARM gem5 Developers } 12910037SARM gem5 Developers ''' 13010037SARM gem5 Developers extrIop = InstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode); 13110037SARM gem5 Developers subst("RegRegRegImmOp64", extrIop); 13210037SARM gem5 Developers 13310037SARM gem5 Developers unknownCode = ''' 13410474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, true); 13510037SARM gem5 Developers ''' 13610037SARM gem5 Developers unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64", 13710037SARM gem5 Developers unknownCode) 13810037SARM gem5 Developers header_output += BasicDeclare.subst(unknown64Iop) 13910037SARM gem5 Developers decoder_output += BasicConstructor64.subst(unknown64Iop) 14010037SARM gem5 Developers exec_output += BasicExecute.subst(unknown64Iop) 14110037SARM gem5 Developers 14212259Sgiacomo.travaglini@arm.com isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "", 14312488Sgiacomo.travaglini@arm.com ['IsSquashAfter']) 14410037SARM gem5 Developers header_output += BasicDeclare.subst(isbIop) 14510037SARM gem5 Developers decoder_output += BasicConstructor64.subst(isbIop) 14610037SARM gem5 Developers exec_output += BasicExecute.subst(isbIop) 14710037SARM gem5 Developers 14812259Sgiacomo.travaglini@arm.com dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "", 14912261Sgiacomo.travaglini@arm.com ['IsMemBarrier', 'IsSerializeAfter']) 15010037SARM gem5 Developers header_output += BasicDeclare.subst(dsbIop) 15110037SARM gem5 Developers decoder_output += BasicConstructor64.subst(dsbIop) 15210037SARM gem5 Developers exec_output += BasicExecute.subst(dsbIop) 15310037SARM gem5 Developers 15410037SARM gem5 Developers dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "", 15510037SARM gem5 Developers ['IsMemBarrier']) 15610037SARM gem5 Developers header_output += BasicDeclare.subst(dmbIop) 15710037SARM gem5 Developers decoder_output += BasicConstructor64.subst(dmbIop) 15810037SARM gem5 Developers exec_output += BasicExecute.subst(dmbIop) 15910037SARM gem5 Developers 16010037SARM gem5 Developers clrexIop = InstObjParams("clrex", "Clrex64", "ArmStaticInst", 16110037SARM gem5 Developers "LLSCLock = 0;") 16210037SARM gem5 Developers header_output += BasicDeclare.subst(clrexIop) 16310037SARM gem5 Developers decoder_output += BasicConstructor64.subst(clrexIop) 16410037SARM gem5 Developers exec_output += BasicExecute.subst(clrexIop) 16512299Sandreas.sandberg@arm.com 16612299Sandreas.sandberg@arm.com 16712299Sandreas.sandberg@arm.com brkCode = ''' 16812299Sandreas.sandberg@arm.com fault = std::make_shared<SoftwareBreakpoint>(machInst, 16912299Sandreas.sandberg@arm.com bits(machInst, 20, 5)); 17012299Sandreas.sandberg@arm.com ''' 17112299Sandreas.sandberg@arm.com 17212538Sgiacomo.travaglini@arm.com brkIop = InstObjParams("brk", "Brk64", "ImmOp64", 17312299Sandreas.sandberg@arm.com brkCode, ["IsSerializeAfter"]) 17412538Sgiacomo.travaglini@arm.com header_output += ImmOp64Declare.subst(brkIop) 17512538Sgiacomo.travaglini@arm.com decoder_output += ImmOp64Constructor.subst(brkIop) 17612299Sandreas.sandberg@arm.com exec_output += BasicExecute.subst(brkIop) 17712531Sandreas.sandberg@arm.com 17812531Sandreas.sandberg@arm.com hltCode = ''' 17912531Sandreas.sandberg@arm.com ThreadContext *tc = xc->tcBase(); 18012531Sandreas.sandberg@arm.com if (ArmSystem::haveSemihosting(tc) && bits(machInst, 20, 5) == 0xF000) { 18112531Sandreas.sandberg@arm.com X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1); 18212531Sandreas.sandberg@arm.com } else { 18312531Sandreas.sandberg@arm.com // HLT instructions aren't implemented, so treat them as undefined 18412531Sandreas.sandberg@arm.com // instructions. 18512531Sandreas.sandberg@arm.com fault = std::make_shared<UndefinedInstruction>( 18612531Sandreas.sandberg@arm.com machInst, false, mnemonic); 18712531Sandreas.sandberg@arm.com } 18812531Sandreas.sandberg@arm.com 18912531Sandreas.sandberg@arm.com ''' 19012531Sandreas.sandberg@arm.com 19112538Sgiacomo.travaglini@arm.com hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64", 19212531Sandreas.sandberg@arm.com hltCode, ["IsNonSpeculative"]) 19312538Sgiacomo.travaglini@arm.com header_output += ImmOp64Declare.subst(hltIop) 19412538Sgiacomo.travaglini@arm.com decoder_output += ImmOp64Constructor.subst(hltIop) 19512531Sandreas.sandberg@arm.com exec_output += BasicExecute.subst(hltIop) 19610037SARM gem5 Developers}}; 197