misc64.isa revision 12538
1// -*- mode:c++ -*- 2 3// Copyright (c) 2011-2013, 2016-2018 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 svcCode = ''' 42 fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5)); 43 ''' 44 45 svcIop = InstObjParams("svc", "Svc64", "ImmOp64", 46 svcCode, ["IsSyscall", "IsNonSpeculative", 47 "IsSerializeAfter"]) 48 header_output = ImmOp64Declare.subst(svcIop) 49 decoder_output = ImmOp64Constructor.subst(svcIop) 50 exec_output = BasicExecute.subst(svcIop) 51 52 hvcCode = ''' 53 SCR scr = Scr64; 54 55 if (!ArmSystem::haveVirtualization(xc->tcBase()) || 56 (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { 57 fault = disabledFault(); 58 } else { 59 fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5)); 60 } 61 ''' 62 63 hvcIop = InstObjParams("hvc", "Hvc64", "ImmOp64", 64 hvcCode, ["IsSyscall", "IsNonSpeculative", 65 "IsSerializeAfter"]) 66 header_output += ImmOp64Declare.subst(hvcIop) 67 decoder_output += ImmOp64Constructor.subst(hvcIop) 68 exec_output += BasicExecute.subst(hvcIop) 69 70 # @todo: extend to take into account Virtualization. 71 smcCode = ''' 72 SCR scr = Scr64; 73 CPSR cpsr = Cpsr; 74 75 if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) { 76 fault = disabledFault(); 77 } else { 78 fault = std::make_shared<SecureMonitorCall>(machInst); 79 } 80 ''' 81 82 smcIop = InstObjParams("smc", "Smc64", "ImmOp64", 83 smcCode, ["IsNonSpeculative", "IsSerializeAfter"]) 84 header_output += ImmOp64Declare.subst(smcIop) 85 decoder_output += ImmOp64Constructor.subst(smcIop) 86 exec_output += BasicExecute.subst(smcIop) 87 88 def subst(templateBase, iop): 89 global header_output, decoder_output, exec_output 90 header_output += eval(templateBase + "Declare").subst(iop) 91 decoder_output += eval(templateBase + "Constructor").subst(iop) 92 exec_output += BasicExecute.subst(iop) 93 94 bfmMaskCode = ''' 95 uint64_t bitMask; 96 int diff = imm2 - imm1; 97 if (imm1 <= imm2) { 98 bitMask = mask(diff + 1); 99 } else { 100 bitMask = mask(imm2 + 1); 101 bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1)); 102 diff += intWidth; 103 } 104 uint64_t topBits M5_VAR_USED = ~mask(diff+1); 105 uint64_t result = imm1 == 0 ? Op164 : 106 (Op164 >> imm1) | (Op164 << (intWidth - imm1)); 107 result &= bitMask; 108 ''' 109 110 bfmCode = bfmMaskCode + 'Dest64 = result | (Dest64 & ~bitMask);' 111 bfmIop = InstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode); 112 subst("RegRegImmImmOp64", bfmIop) 113 114 ubfmCode = bfmMaskCode + 'Dest64 = result;' 115 ubfmIop = InstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode); 116 subst("RegRegImmImmOp64", ubfmIop) 117 118 sbfmCode = bfmMaskCode + \ 119 'Dest64 = result | (bits(Op164, imm2) ? topBits : 0);' 120 sbfmIop = InstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode); 121 subst("RegRegImmImmOp64", sbfmIop) 122 123 extrCode = ''' 124 if (imm == 0) { 125 Dest64 = Op264; 126 } else { 127 Dest64 = (Op164 << (intWidth - imm)) | (Op264 >> imm); 128 } 129 ''' 130 extrIop = InstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode); 131 subst("RegRegRegImmOp64", extrIop); 132 133 unknownCode = ''' 134 return std::make_shared<UndefinedInstruction>(machInst, true); 135 ''' 136 unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64", 137 unknownCode) 138 header_output += BasicDeclare.subst(unknown64Iop) 139 decoder_output += BasicConstructor64.subst(unknown64Iop) 140 exec_output += BasicExecute.subst(unknown64Iop) 141 142 isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "", 143 ['IsSquashAfter']) 144 header_output += BasicDeclare.subst(isbIop) 145 decoder_output += BasicConstructor64.subst(isbIop) 146 exec_output += BasicExecute.subst(isbIop) 147 148 dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "", 149 ['IsMemBarrier', 'IsSerializeAfter']) 150 header_output += BasicDeclare.subst(dsbIop) 151 decoder_output += BasicConstructor64.subst(dsbIop) 152 exec_output += BasicExecute.subst(dsbIop) 153 154 dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "", 155 ['IsMemBarrier']) 156 header_output += BasicDeclare.subst(dmbIop) 157 decoder_output += BasicConstructor64.subst(dmbIop) 158 exec_output += BasicExecute.subst(dmbIop) 159 160 clrexIop = InstObjParams("clrex", "Clrex64", "ArmStaticInst", 161 "LLSCLock = 0;") 162 header_output += BasicDeclare.subst(clrexIop) 163 decoder_output += BasicConstructor64.subst(clrexIop) 164 exec_output += BasicExecute.subst(clrexIop) 165 166 167 brkCode = ''' 168 fault = std::make_shared<SoftwareBreakpoint>(machInst, 169 bits(machInst, 20, 5)); 170 ''' 171 172 brkIop = InstObjParams("brk", "Brk64", "ImmOp64", 173 brkCode, ["IsSerializeAfter"]) 174 header_output += ImmOp64Declare.subst(brkIop) 175 decoder_output += ImmOp64Constructor.subst(brkIop) 176 exec_output += BasicExecute.subst(brkIop) 177 178 hltCode = ''' 179 ThreadContext *tc = xc->tcBase(); 180 if (ArmSystem::haveSemihosting(tc) && bits(machInst, 20, 5) == 0xF000) { 181 X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1); 182 } else { 183 // HLT instructions aren't implemented, so treat them as undefined 184 // instructions. 185 fault = std::make_shared<UndefinedInstruction>( 186 machInst, false, mnemonic); 187 } 188 189 ''' 190 191 hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64", 192 hltCode, ["IsNonSpeculative"]) 193 header_output += ImmOp64Declare.subst(hltIop) 194 decoder_output += ImmOp64Constructor.subst(hltIop) 195 exec_output += BasicExecute.subst(hltIop) 196}}; 197