macromem.isa revision 7422
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42//          Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49let {{
50    microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
51    microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
52                                   'MicroMemOp',
53                                   {'memacc_code': microLdrUopCode,
54                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
55                                    'predicate_test': predicateTest},
56                                   ['IsMicroop'])
57
58    microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
59    microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
60                                     'MicroMemOp',
61                                     {'memacc_code': microLdrFpUopCode,
62                                      'ea_code': 'EA = Rb + (up ? imm : -imm);',
63                                      'predicate_test': predicateTest},
64                                     ['IsMicroop'])
65
66    microLdrRetUopCode = '''
67        CPSR cpsr = Cpsr;
68        SCTLR sctlr = Sctlr;
69        uint32_t newCpsr =
70            cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
71        Cpsr = ~CondCodesMask & newCpsr;
72        CondCodes = CondCodesMask & newCpsr;
73        IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
74    '''
75    microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
76                                      'MicroMemOp',
77                                      {'memacc_code': microLdrRetUopCode,
78                                       'ea_code':
79                                          'EA = Rb + (up ? imm : -imm);',
80                                       'predicate_test': condPredicateTest},
81                                      ['IsMicroop'])
82
83    microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
84    microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
85                                   'MicroMemOp',
86                                   {'memacc_code': microStrUopCode,
87                                    'postacc_code': "",
88                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
89                                    'predicate_test': predicateTest},
90                                   ['IsMicroop'])
91
92    microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
93    microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
94                                     'MicroMemOp',
95                                     {'memacc_code': microStrFpUopCode,
96                                      'postacc_code': "",
97                                      'ea_code': 'EA = Rb + (up ? imm : -imm);',
98                                      'predicate_test': predicateTest},
99                                     ['IsMicroop'])
100
101    header_output = decoder_output = exec_output = ''
102
103    loadIops = (microLdrUopIop, microLdrFpUopIop, microLdrRetUopIop)
104    storeIops = (microStrUopIop, microStrFpUopIop)
105    for iop in loadIops + storeIops:
106        header_output += MicroMemDeclare.subst(iop)
107        decoder_output += MicroMemConstructor.subst(iop)
108    for iop in loadIops:
109        exec_output += LoadExecute.subst(iop) + \
110                       LoadInitiateAcc.subst(iop) + \
111                       LoadCompleteAcc.subst(iop)
112    for iop in storeIops:
113        exec_output += StoreExecute.subst(iop) + \
114                       StoreInitiateAcc.subst(iop) + \
115                       StoreCompleteAcc.subst(iop)
116}};
117
118////////////////////////////////////////////////////////////////////
119//
120// Integer = Integer op Immediate microops
121//
122
123let {{
124    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
125                                    'MicroIntOp',
126                                    {'code': 'Ra = Rb + imm;',
127                                     'predicate_test': predicateTest},
128                                    ['IsMicroop'])
129
130    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
131                                    'MicroIntOp',
132                                    {'code': 'Ra = Rb - imm;',
133                                     'predicate_test': predicateTest},
134                                    ['IsMicroop'])
135
136    header_output = MicroIntDeclare.subst(microAddiUopIop) + \
137                    MicroIntDeclare.subst(microSubiUopIop)
138    decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
139                     MicroIntConstructor.subst(microSubiUopIop)
140    exec_output = PredOpExecute.subst(microAddiUopIop) + \
141                  PredOpExecute.subst(microSubiUopIop)
142}};
143
144let {{
145    iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
146    header_output = MacroMemDeclare.subst(iop)
147    decoder_output = MacroMemConstructor.subst(iop)
148
149    vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", [])
150    header_output += MacroVFPMemDeclare.subst(vfpIop)
151    decoder_output += MacroVFPMemConstructor.subst(vfpIop)
152}};
153