macromem.isa revision 7296
111723Sar4jc@virginia.edu// -*- mode:c++ -*- 211723Sar4jc@virginia.edu 311723Sar4jc@virginia.edu// Copyright (c) 2010 ARM Limited 411723Sar4jc@virginia.edu// All rights reserved 511723Sar4jc@virginia.edu// 611723Sar4jc@virginia.edu// The license below extends only to copyright in the software and shall 711723Sar4jc@virginia.edu// not be construed as granting a license to any other intellectual 811723Sar4jc@virginia.edu// property including but not limited to intellectual property relating 911723Sar4jc@virginia.edu// to a hardware implementation of the functionality of the software 1011723Sar4jc@virginia.edu// licensed hereunder. You may use the software subject to the license 1111723Sar4jc@virginia.edu// terms below provided that you ensure that this notice is replicated 1211723Sar4jc@virginia.edu// unmodified and in its entirety in all distributions of the software, 1311723Sar4jc@virginia.edu// modified or unmodified, in source code or in binary form. 1411723Sar4jc@virginia.edu// 1511723Sar4jc@virginia.edu// Copyright (c) 2007-2008 The Florida State University 1611723Sar4jc@virginia.edu// All rights reserved. 1711723Sar4jc@virginia.edu// 1811723Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 1911723Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 2011723Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 2111723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 2211723Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 2311723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 2411723Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 2511723Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 2611723Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 2711723Sar4jc@virginia.edu// this software without specific prior written permission. 2811723Sar4jc@virginia.edu// 2911723Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011723Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111723Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211723Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311723Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411723Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511723Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611723Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711723Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811723Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911723Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011723Sar4jc@virginia.edu// 4111723Sar4jc@virginia.edu// Authors: Stephen Hines 4211723Sar4jc@virginia.edu// Gabe Black 4311723Sar4jc@virginia.edu 4411723Sar4jc@virginia.edu//////////////////////////////////////////////////////////////////// 4511723Sar4jc@virginia.edu// 4612334Sgabeblack@google.com// Load/store microops 4712106SRekai.GonzalezAlberquilla@arm.com// 4811723Sar4jc@virginia.edu 4911723Sar4jc@virginia.edulet {{ 5011723Sar4jc@virginia.edu predicateTest = 'testPredicate(CondCodes, condCode)' 5111723Sar4jc@virginia.edu}}; 5211723Sar4jc@virginia.edu 5311723Sar4jc@virginia.edulet {{ 5411723Sar4jc@virginia.edu microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 5511723Sar4jc@virginia.edu microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 5611723Sar4jc@virginia.edu 'MicroMemOp', 5711723Sar4jc@virginia.edu {'memacc_code': microLdrUopCode, 5811723Sar4jc@virginia.edu 'ea_code': 'EA = Rb + (up ? imm : -imm);', 5911723Sar4jc@virginia.edu 'predicate_test': predicateTest}, 6011723Sar4jc@virginia.edu ['IsMicroop']) 6111723Sar4jc@virginia.edu 6211723Sar4jc@virginia.edu microLdrFpUopCode = "Fa = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 6311723Sar4jc@virginia.edu microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', 6411723Sar4jc@virginia.edu 'MicroMemOp', 6511723Sar4jc@virginia.edu {'memacc_code': microLdrFpUopCode, 6611723Sar4jc@virginia.edu 'ea_code': 'EA = Rb + (up ? imm : -imm);', 6711723Sar4jc@virginia.edu 'predicate_test': predicateTest}, 6811723Sar4jc@virginia.edu ['IsMicroop']) 6911723Sar4jc@virginia.edu 7011723Sar4jc@virginia.edu microLdrRetUopCode = ''' 7111723Sar4jc@virginia.edu CPSR cpsr = Cpsr; 7211723Sar4jc@virginia.edu uint32_t newCpsr = 7311723Sar4jc@virginia.edu cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true); 7411723Sar4jc@virginia.edu Cpsr = ~CondCodesMask & newCpsr; 7511723Sar4jc@virginia.edu CondCodes = CondCodesMask & newCpsr; 7611723Sar4jc@virginia.edu IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); 7711723Sar4jc@virginia.edu ''' 7811723Sar4jc@virginia.edu microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 7911723Sar4jc@virginia.edu 'MicroMemOp', 8011723Sar4jc@virginia.edu {'memacc_code': microLdrRetUopCode, 8112106SRekai.GonzalezAlberquilla@arm.com 'ea_code': 8212106SRekai.GonzalezAlberquilla@arm.com 'EA = Rb + (up ? imm : -imm);', 8312106SRekai.GonzalezAlberquilla@arm.com 'predicate_test': predicateTest}, 8412106SRekai.GonzalezAlberquilla@arm.com ['IsMicroop']) 8512106SRekai.GonzalezAlberquilla@arm.com 8612106SRekai.GonzalezAlberquilla@arm.com microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);" 8711723Sar4jc@virginia.edu microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 8811723Sar4jc@virginia.edu 'MicroMemOp', 8911723Sar4jc@virginia.edu {'memacc_code': microStrUopCode, 9011723Sar4jc@virginia.edu 'ea_code': 'EA = Rb + (up ? imm : -imm);', 9111723Sar4jc@virginia.edu 'predicate_test': predicateTest}, 9211723Sar4jc@virginia.edu ['IsMicroop']) 9311723Sar4jc@virginia.edu 9411723Sar4jc@virginia.edu microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" 9511723Sar4jc@virginia.edu microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop', 9611723Sar4jc@virginia.edu 'MicroMemOp', 9711723Sar4jc@virginia.edu {'memacc_code': microStrFpUopCode, 9811723Sar4jc@virginia.edu 'ea_code': 'EA = Rb + (up ? imm : -imm);', 9912109SRekai.GonzalezAlberquilla@arm.com 'predicate_test': predicateTest}, 10012109SRekai.GonzalezAlberquilla@arm.com ['IsMicroop']) 10112109SRekai.GonzalezAlberquilla@arm.com 10212109SRekai.GonzalezAlberquilla@arm.com header_output = decoder_output = exec_output = '' 10312109SRekai.GonzalezAlberquilla@arm.com 10412109SRekai.GonzalezAlberquilla@arm.com loadIops = (microLdrUopIop, microLdrFpUopIop, microLdrRetUopIop) 10512109SRekai.GonzalezAlberquilla@arm.com storeIops = (microStrUopIop, microStrFpUopIop) 10612109SRekai.GonzalezAlberquilla@arm.com for iop in loadIops + storeIops: 10712109SRekai.GonzalezAlberquilla@arm.com header_output += MicroMemDeclare.subst(iop) 10812109SRekai.GonzalezAlberquilla@arm.com decoder_output += MicroMemConstructor.subst(iop) 10912109SRekai.GonzalezAlberquilla@arm.com for iop in loadIops: 11012109SRekai.GonzalezAlberquilla@arm.com exec_output += LoadExecute.subst(iop) + \ 11111723Sar4jc@virginia.edu LoadInitiateAcc.subst(iop) + \ 11211723Sar4jc@virginia.edu LoadCompleteAcc.subst(iop) 11311723Sar4jc@virginia.edu for iop in storeIops: 11411723Sar4jc@virginia.edu exec_output += StoreExecute.subst(iop) + \ 11511723Sar4jc@virginia.edu StoreInitiateAcc.subst(iop) + \ 11611723Sar4jc@virginia.edu StoreCompleteAcc.subst(iop) 11711723Sar4jc@virginia.edu}}; 11811723Sar4jc@virginia.edu 11911723Sar4jc@virginia.edu//////////////////////////////////////////////////////////////////// 12011723Sar4jc@virginia.edu// 12111723Sar4jc@virginia.edu// Integer = Integer op Immediate microops 12211723Sar4jc@virginia.edu// 12311723Sar4jc@virginia.edu 12411723Sar4jc@virginia.edulet {{ 12511723Sar4jc@virginia.edu microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 12611723Sar4jc@virginia.edu 'MicroIntOp', 12711723Sar4jc@virginia.edu {'code': 'Ra = Rb + imm;', 12811723Sar4jc@virginia.edu 'predicate_test': predicateTest}, 12911723Sar4jc@virginia.edu ['IsMicroop']) 13011723Sar4jc@virginia.edu 13111723Sar4jc@virginia.edu microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 13211723Sar4jc@virginia.edu 'MicroIntOp', 13311723Sar4jc@virginia.edu {'code': 'Ra = Rb - imm;', 13411723Sar4jc@virginia.edu 'predicate_test': predicateTest}, 13511723Sar4jc@virginia.edu ['IsMicroop']) 13611723Sar4jc@virginia.edu 13711723Sar4jc@virginia.edu header_output = MicroIntDeclare.subst(microAddiUopIop) + \ 138 MicroIntDeclare.subst(microSubiUopIop) 139 decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \ 140 MicroIntConstructor.subst(microSubiUopIop) 141 exec_output = PredOpExecute.subst(microAddiUopIop) + \ 142 PredOpExecute.subst(microSubiUopIop) 143}}; 144 145let {{ 146 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", []) 147 header_output = MacroMemDeclare.subst(iop) 148 decoder_output = MacroMemConstructor.subst(iop) 149 150 vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", []) 151 header_output += MacroVFPMemDeclare.subst(vfpIop) 152 decoder_output += MacroVFPMemConstructor.subst(vfpIop) 153}}; 154