macromem.isa revision 8303
16019SN/A// -*- mode:c++ -*- 26019SN/A 37134Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 497134Sgblack@eecs.umich.edulet {{ 507296Sgblack@eecs.umich.edu microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 516309SN/A microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 526309SN/A 'MicroMemOp', 537296Sgblack@eecs.umich.edu {'memacc_code': microLdrUopCode, 548139SMatt.Horsnell@arm.com 'ea_code': 'EA = URb + (up ? imm : -imm);', 556309SN/A 'predicate_test': predicateTest}, 566309SN/A ['IsMicroop']) 576309SN/A 587342Sgblack@eecs.umich.edu microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 597174Sgblack@eecs.umich.edu microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', 607639Sgblack@eecs.umich.edu 'MicroMemOp', 617639Sgblack@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 627644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + 638139SMatt.Horsnell@arm.com 'EA = URb + (up ? imm : -imm);', 647639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 657639Sgblack@eecs.umich.edu ['IsMicroop']) 667639Sgblack@eecs.umich.edu 677639Sgblack@eecs.umich.edu microLdrDBFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 687639Sgblack@eecs.umich.edu microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop', 697639Sgblack@eecs.umich.edu 'MicroMemOp', 707639Sgblack@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 717644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + ''' 728139SMatt.Horsnell@arm.com EA = URb + (up ? imm : -imm) + 737639Sgblack@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 747639Sgblack@eecs.umich.edu ''', 757639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 767639Sgblack@eecs.umich.edu ['IsMicroop']) 777639Sgblack@eecs.umich.edu 787639Sgblack@eecs.umich.edu microLdrDTFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 797639Sgblack@eecs.umich.edu microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop', 807639Sgblack@eecs.umich.edu 'MicroMemOp', 817639Sgblack@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 827644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + ''' 838139SMatt.Horsnell@arm.com EA = URb + (up ? imm : -imm) - 847639Sgblack@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 857639Sgblack@eecs.umich.edu ''', 867639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 877639Sgblack@eecs.umich.edu ['IsMicroop']) 887174Sgblack@eecs.umich.edu 898148SAli.Saidi@ARM.com microRetUopCode = ''' 908303SAli.Saidi@ARM.com CPSR old_cpsr = Cpsr; 917400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 928303SAli.Saidi@ARM.com old_cpsr.nz = CondCodesNZ; 938303SAli.Saidi@ARM.com old_cpsr.c = CondCodesC; 948303SAli.Saidi@ARM.com old_cpsr.v = CondCodesV; 958303SAli.Saidi@ARM.com old_cpsr.ge = CondCodesGE; 968303SAli.Saidi@ARM.com 978303SAli.Saidi@ARM.com CPSR new_cpsr = 988303SAli.Saidi@ARM.com cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); 998303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 1008303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 1018303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 1028303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 1038303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 1048303SAli.Saidi@ARM.com IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0); 1058205SAli.Saidi@ARM.com NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) 1067858SMatt.Horsnell@arm.com | (((CPSR)Spsr).it1 & 0x3); 1078285SPrakash.Ramrakhyani@arm.com SevMailbox = 1; 1086754SN/A ''' 1098148SAli.Saidi@ARM.com 1106754SN/A microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 1116754SN/A 'MicroMemOp', 1128148SAli.Saidi@ARM.com {'memacc_code': 1138148SAli.Saidi@ARM.com microRetUopCode % 'Mem.uw', 1146754SN/A 'ea_code': 1158139SMatt.Horsnell@arm.com 'EA = URb + (up ? imm : -imm);', 1167422Sgblack@eecs.umich.edu 'predicate_test': condPredicateTest}, 1178148SAli.Saidi@ARM.com ['IsMicroop','IsNonSpeculative', 1188148SAli.Saidi@ARM.com 'IsSerializeAfter']) 1196754SN/A 1208139SMatt.Horsnell@arm.com microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);" 1216309SN/A microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 1226309SN/A 'MicroMemOp', 1237296Sgblack@eecs.umich.edu {'memacc_code': microStrUopCode, 1247303Sgblack@eecs.umich.edu 'postacc_code': "", 1258139SMatt.Horsnell@arm.com 'ea_code': 'EA = URb + (up ? imm : -imm);', 1266309SN/A 'predicate_test': predicateTest}, 1276309SN/A ['IsMicroop']) 1286309SN/A 1297296Sgblack@eecs.umich.edu microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" 1307174Sgblack@eecs.umich.edu microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop', 1317174Sgblack@eecs.umich.edu 'MicroMemOp', 1327296Sgblack@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1337303Sgblack@eecs.umich.edu 'postacc_code': "", 1347644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + 1358139SMatt.Horsnell@arm.com 'EA = URb + (up ? imm : -imm);', 1367174Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 1377174Sgblack@eecs.umich.edu ['IsMicroop']) 1387174Sgblack@eecs.umich.edu 1397639Sgblack@eecs.umich.edu microStrDBFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" 1407639Sgblack@eecs.umich.edu microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop', 1417639Sgblack@eecs.umich.edu 'MicroMemOp', 1427639Sgblack@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1437639Sgblack@eecs.umich.edu 'postacc_code': "", 1447644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + ''' 1458139SMatt.Horsnell@arm.com EA = URb + (up ? imm : -imm) + 1467639Sgblack@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 1477639Sgblack@eecs.umich.edu ''', 1487639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 1497639Sgblack@eecs.umich.edu ['IsMicroop']) 1507639Sgblack@eecs.umich.edu 1517639Sgblack@eecs.umich.edu microStrDTFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" 1527639Sgblack@eecs.umich.edu microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop', 1537639Sgblack@eecs.umich.edu 'MicroMemOp', 1547639Sgblack@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1557639Sgblack@eecs.umich.edu 'postacc_code': "", 1567644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + ''' 1578139SMatt.Horsnell@arm.com EA = URb + (up ? imm : -imm) - 1587639Sgblack@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 1597639Sgblack@eecs.umich.edu ''', 1607639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 1617639Sgblack@eecs.umich.edu ['IsMicroop']) 1627639Sgblack@eecs.umich.edu 1637174Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = '' 1647174Sgblack@eecs.umich.edu 1657639Sgblack@eecs.umich.edu loadIops = (microLdrUopIop, microLdrRetUopIop, 1667639Sgblack@eecs.umich.edu microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop) 1677639Sgblack@eecs.umich.edu storeIops = (microStrUopIop, microStrFpUopIop, 1687639Sgblack@eecs.umich.edu microStrDBFpUopIop, microStrDTFpUopIop) 1697174Sgblack@eecs.umich.edu for iop in loadIops + storeIops: 1707174Sgblack@eecs.umich.edu header_output += MicroMemDeclare.subst(iop) 1717174Sgblack@eecs.umich.edu decoder_output += MicroMemConstructor.subst(iop) 1727174Sgblack@eecs.umich.edu for iop in loadIops: 1737174Sgblack@eecs.umich.edu exec_output += LoadExecute.subst(iop) + \ 1747174Sgblack@eecs.umich.edu LoadInitiateAcc.subst(iop) + \ 1757174Sgblack@eecs.umich.edu LoadCompleteAcc.subst(iop) 1767174Sgblack@eecs.umich.edu for iop in storeIops: 1777174Sgblack@eecs.umich.edu exec_output += StoreExecute.subst(iop) + \ 1787174Sgblack@eecs.umich.edu StoreInitiateAcc.subst(iop) + \ 1797174Sgblack@eecs.umich.edu StoreCompleteAcc.subst(iop) 1806309SN/A}}; 1816308SN/A 1827639Sgblack@eecs.umich.edulet {{ 1837639Sgblack@eecs.umich.edu exec_output = header_output = '' 1847639Sgblack@eecs.umich.edu 1858139SMatt.Horsnell@arm.com eaCode = 'EA = URa + imm;' 1867639Sgblack@eecs.umich.edu 1877639Sgblack@eecs.umich.edu for size in (1, 2, 3, 4, 6, 8, 12, 16): 1887639Sgblack@eecs.umich.edu # Set up the memory access. 1897639Sgblack@eecs.umich.edu regs = (size + 3) // 4 1907639Sgblack@eecs.umich.edu subst = { "size" : size, "regs" : regs } 1917639Sgblack@eecs.umich.edu memDecl = ''' 1927639Sgblack@eecs.umich.edu union MemUnion { 1937639Sgblack@eecs.umich.edu uint8_t bytes[%(size)d]; 1947639Sgblack@eecs.umich.edu Element elements[%(size)d / sizeof(Element)]; 1957639Sgblack@eecs.umich.edu uint32_t floatRegBits[%(regs)d]; 1967639Sgblack@eecs.umich.edu }; 1977639Sgblack@eecs.umich.edu ''' % subst 1987639Sgblack@eecs.umich.edu 1997639Sgblack@eecs.umich.edu # Do endian conversion for all the elements. 2007639Sgblack@eecs.umich.edu convCode = ''' 2017639Sgblack@eecs.umich.edu const unsigned eCount = sizeof(memUnion.elements) / 2027639Sgblack@eecs.umich.edu sizeof(memUnion.elements[0]); 2037639Sgblack@eecs.umich.edu if (((CPSR)Cpsr).e) { 2047639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 2057639Sgblack@eecs.umich.edu memUnion.elements[i] = gtobe(memUnion.elements[i]); 2067639Sgblack@eecs.umich.edu } 2077639Sgblack@eecs.umich.edu } else { 2087639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 2097639Sgblack@eecs.umich.edu memUnion.elements[i] = gtole(memUnion.elements[i]); 2107639Sgblack@eecs.umich.edu } 2117639Sgblack@eecs.umich.edu } 2127639Sgblack@eecs.umich.edu ''' 2137639Sgblack@eecs.umich.edu 2147639Sgblack@eecs.umich.edu # Offload everything into registers 2157639Sgblack@eecs.umich.edu regSetCode = '' 2167639Sgblack@eecs.umich.edu for reg in range(regs): 2177639Sgblack@eecs.umich.edu mask = '' 2187639Sgblack@eecs.umich.edu if reg == regs - 1: 2197639Sgblack@eecs.umich.edu mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size)) 2207639Sgblack@eecs.umich.edu regSetCode += ''' 2217639Sgblack@eecs.umich.edu FpDestP%(reg)d.uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s; 2227639Sgblack@eecs.umich.edu ''' % { "reg" : reg, "mask" : mask } 2237639Sgblack@eecs.umich.edu 2247639Sgblack@eecs.umich.edu # Pull everything in from registers 2257639Sgblack@eecs.umich.edu regGetCode = '' 2267639Sgblack@eecs.umich.edu for reg in range(regs): 2277639Sgblack@eecs.umich.edu regGetCode += ''' 2287639Sgblack@eecs.umich.edu memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d.uw); 2297639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 2307639Sgblack@eecs.umich.edu 2317639Sgblack@eecs.umich.edu loadMemAccCode = convCode + regSetCode 2327639Sgblack@eecs.umich.edu storeMemAccCode = regGetCode + convCode 2337639Sgblack@eecs.umich.edu 2347639Sgblack@eecs.umich.edu loadIop = InstObjParams('ldrneon%(size)d_uop' % subst, 2357639Sgblack@eecs.umich.edu 'MicroLdrNeon%(size)dUop' % subst, 2367639Sgblack@eecs.umich.edu 'MicroNeonMemOp', 2377639Sgblack@eecs.umich.edu { 'mem_decl' : memDecl, 2387639Sgblack@eecs.umich.edu 'size' : size, 2397639Sgblack@eecs.umich.edu 'memacc_code' : loadMemAccCode, 2407644Sali.saidi@arm.com 'ea_code' : simdEnabledCheckCode + eaCode, 2417639Sgblack@eecs.umich.edu 'predicate_test' : predicateTest }, 2427639Sgblack@eecs.umich.edu [ 'IsMicroop', 'IsMemRef', 'IsLoad' ]) 2437639Sgblack@eecs.umich.edu storeIop = InstObjParams('strneon%(size)d_uop' % subst, 2447639Sgblack@eecs.umich.edu 'MicroStrNeon%(size)dUop' % subst, 2457639Sgblack@eecs.umich.edu 'MicroNeonMemOp', 2467639Sgblack@eecs.umich.edu { 'mem_decl' : memDecl, 2477639Sgblack@eecs.umich.edu 'size' : size, 2487639Sgblack@eecs.umich.edu 'memacc_code' : storeMemAccCode, 2497644Sali.saidi@arm.com 'ea_code' : simdEnabledCheckCode + eaCode, 2507639Sgblack@eecs.umich.edu 'predicate_test' : predicateTest }, 2517639Sgblack@eecs.umich.edu [ 'IsMicroop', 'IsMemRef', 'IsStore' ]) 2527639Sgblack@eecs.umich.edu 2537639Sgblack@eecs.umich.edu exec_output += NeonLoadExecute.subst(loadIop) + \ 2547639Sgblack@eecs.umich.edu NeonLoadInitiateAcc.subst(loadIop) + \ 2557639Sgblack@eecs.umich.edu NeonLoadCompleteAcc.subst(loadIop) + \ 2567639Sgblack@eecs.umich.edu NeonStoreExecute.subst(storeIop) + \ 2577639Sgblack@eecs.umich.edu NeonStoreInitiateAcc.subst(storeIop) + \ 2587639Sgblack@eecs.umich.edu NeonStoreCompleteAcc.subst(storeIop) 2597639Sgblack@eecs.umich.edu header_output += MicroNeonMemDeclare.subst(loadIop) + \ 2607639Sgblack@eecs.umich.edu MicroNeonMemDeclare.subst(storeIop) 2617639Sgblack@eecs.umich.edu}}; 2627639Sgblack@eecs.umich.edu 2637639Sgblack@eecs.umich.edulet {{ 2647639Sgblack@eecs.umich.edu exec_output = '' 2657639Sgblack@eecs.umich.edu for eSize, type in (1, 'uint8_t'), \ 2667639Sgblack@eecs.umich.edu (2, 'uint16_t'), \ 2677639Sgblack@eecs.umich.edu (4, 'uint32_t'), \ 2687639Sgblack@eecs.umich.edu (8, 'uint64_t'): 2697639Sgblack@eecs.umich.edu size = eSize 2707639Sgblack@eecs.umich.edu # An instruction handles no more than 16 bytes and no more than 2717639Sgblack@eecs.umich.edu # 4 elements, or the number of elements needed to fill 8 or 16 bytes. 2727639Sgblack@eecs.umich.edu sizes = set((16, 8)) 2737639Sgblack@eecs.umich.edu for count in 1, 2, 3, 4: 2747639Sgblack@eecs.umich.edu size = count * eSize 2757639Sgblack@eecs.umich.edu if size <= 16: 2767639Sgblack@eecs.umich.edu sizes.add(size) 2777639Sgblack@eecs.umich.edu for size in sizes: 2787639Sgblack@eecs.umich.edu substDict = { 2797639Sgblack@eecs.umich.edu "class_name" : "MicroLdrNeon%dUop" % size, 2807639Sgblack@eecs.umich.edu "targs" : type 2817639Sgblack@eecs.umich.edu } 2827639Sgblack@eecs.umich.edu exec_output += MicroNeonMemExecDeclare.subst(substDict) 2837639Sgblack@eecs.umich.edu substDict["class_name"] = "MicroStrNeon%dUop" % size 2847639Sgblack@eecs.umich.edu exec_output += MicroNeonMemExecDeclare.subst(substDict) 2857639Sgblack@eecs.umich.edu size += eSize 2867639Sgblack@eecs.umich.edu}}; 2877639Sgblack@eecs.umich.edu 2887639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2897639Sgblack@eecs.umich.edu// 2907639Sgblack@eecs.umich.edu// Neon (de)interlacing microops 2917639Sgblack@eecs.umich.edu// 2927639Sgblack@eecs.umich.edu 2937639Sgblack@eecs.umich.edulet {{ 2947639Sgblack@eecs.umich.edu header_output = exec_output = '' 2957639Sgblack@eecs.umich.edu for dRegs in (2, 3, 4): 2967639Sgblack@eecs.umich.edu loadConv = '' 2977639Sgblack@eecs.umich.edu unloadConv = '' 2987639Sgblack@eecs.umich.edu for dReg in range(dRegs): 2997639Sgblack@eecs.umich.edu loadConv += ''' 3007639Sgblack@eecs.umich.edu conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d.uw); 3017639Sgblack@eecs.umich.edu conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d.uw); 3027639Sgblack@eecs.umich.edu ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) } 3037639Sgblack@eecs.umich.edu unloadConv += ''' 3047639Sgblack@eecs.umich.edu FpDestS%(dReg)dP0.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]); 3057639Sgblack@eecs.umich.edu FpDestS%(dReg)dP1.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]); 3067639Sgblack@eecs.umich.edu ''' % { "dReg" : dReg } 3077639Sgblack@eecs.umich.edu microDeintNeonCode = ''' 3087639Sgblack@eecs.umich.edu const unsigned dRegs = %(dRegs)d; 3097639Sgblack@eecs.umich.edu const unsigned regs = 2 * dRegs; 3107639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 3117639Sgblack@eecs.umich.edu sizeof(Element); 3127639Sgblack@eecs.umich.edu union convStruct { 3137639Sgblack@eecs.umich.edu FloatRegBits cRegs[regs]; 3147639Sgblack@eecs.umich.edu Element elements[dRegs * perDReg]; 3157639Sgblack@eecs.umich.edu } conv1, conv2; 3167639Sgblack@eecs.umich.edu 3177639Sgblack@eecs.umich.edu %(loadConv)s 3187639Sgblack@eecs.umich.edu 3197639Sgblack@eecs.umich.edu unsigned srcElem = 0; 3207639Sgblack@eecs.umich.edu for (unsigned destOffset = 0; 3217639Sgblack@eecs.umich.edu destOffset < perDReg; destOffset++) { 3227639Sgblack@eecs.umich.edu for (unsigned dReg = 0; dReg < dRegs; dReg++) { 3237639Sgblack@eecs.umich.edu conv2.elements[dReg * perDReg + destOffset] = 3247639Sgblack@eecs.umich.edu conv1.elements[srcElem++]; 3257639Sgblack@eecs.umich.edu } 3267639Sgblack@eecs.umich.edu } 3277639Sgblack@eecs.umich.edu 3287639Sgblack@eecs.umich.edu %(unloadConv)s 3297639Sgblack@eecs.umich.edu ''' % { "dRegs" : dRegs, 3307639Sgblack@eecs.umich.edu "loadConv" : loadConv, 3317639Sgblack@eecs.umich.edu "unloadConv" : unloadConv } 3327639Sgblack@eecs.umich.edu microDeintNeonIop = \ 3337639Sgblack@eecs.umich.edu InstObjParams('deintneon%duop' % (dRegs * 2), 3347639Sgblack@eecs.umich.edu 'MicroDeintNeon%dUop' % (dRegs * 2), 3357639Sgblack@eecs.umich.edu 'MicroNeonMixOp', 3367639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 3377639Sgblack@eecs.umich.edu 'code' : microDeintNeonCode }, 3387639Sgblack@eecs.umich.edu ['IsMicroop']) 3397639Sgblack@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microDeintNeonIop) 3407639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microDeintNeonIop) 3417639Sgblack@eecs.umich.edu 3427639Sgblack@eecs.umich.edu loadConv = '' 3437639Sgblack@eecs.umich.edu unloadConv = '' 3447639Sgblack@eecs.umich.edu for dReg in range(dRegs): 3457639Sgblack@eecs.umich.edu loadConv += ''' 3467639Sgblack@eecs.umich.edu conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0.uw); 3477639Sgblack@eecs.umich.edu conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1.uw); 3487639Sgblack@eecs.umich.edu ''' % { "dReg" : dReg } 3497639Sgblack@eecs.umich.edu unloadConv += ''' 3507639Sgblack@eecs.umich.edu FpDestP%(sReg0)d.uw = gtoh(conv2.cRegs[%(sReg0)d]); 3517639Sgblack@eecs.umich.edu FpDestP%(sReg1)d.uw = gtoh(conv2.cRegs[%(sReg1)d]); 3527639Sgblack@eecs.umich.edu ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) } 3537639Sgblack@eecs.umich.edu microInterNeonCode = ''' 3547639Sgblack@eecs.umich.edu const unsigned dRegs = %(dRegs)d; 3557639Sgblack@eecs.umich.edu const unsigned regs = 2 * dRegs; 3567639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 3577639Sgblack@eecs.umich.edu sizeof(Element); 3587639Sgblack@eecs.umich.edu union convStruct { 3597639Sgblack@eecs.umich.edu FloatRegBits cRegs[regs]; 3607639Sgblack@eecs.umich.edu Element elements[dRegs * perDReg]; 3617639Sgblack@eecs.umich.edu } conv1, conv2; 3627639Sgblack@eecs.umich.edu 3637639Sgblack@eecs.umich.edu %(loadConv)s 3647639Sgblack@eecs.umich.edu 3657639Sgblack@eecs.umich.edu unsigned destElem = 0; 3667639Sgblack@eecs.umich.edu for (unsigned srcOffset = 0; 3677639Sgblack@eecs.umich.edu srcOffset < perDReg; srcOffset++) { 3687639Sgblack@eecs.umich.edu for (unsigned dReg = 0; dReg < dRegs; dReg++) { 3697639Sgblack@eecs.umich.edu conv2.elements[destElem++] = 3707639Sgblack@eecs.umich.edu conv1.elements[dReg * perDReg + srcOffset]; 3717639Sgblack@eecs.umich.edu } 3727639Sgblack@eecs.umich.edu } 3737639Sgblack@eecs.umich.edu 3747639Sgblack@eecs.umich.edu %(unloadConv)s 3757639Sgblack@eecs.umich.edu ''' % { "dRegs" : dRegs, 3767639Sgblack@eecs.umich.edu "loadConv" : loadConv, 3777639Sgblack@eecs.umich.edu "unloadConv" : unloadConv } 3787639Sgblack@eecs.umich.edu microInterNeonIop = \ 3797639Sgblack@eecs.umich.edu InstObjParams('interneon%duop' % (dRegs * 2), 3807639Sgblack@eecs.umich.edu 'MicroInterNeon%dUop' % (dRegs * 2), 3817639Sgblack@eecs.umich.edu 'MicroNeonMixOp', 3827639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 3837639Sgblack@eecs.umich.edu 'code' : microInterNeonCode }, 3847639Sgblack@eecs.umich.edu ['IsMicroop']) 3857639Sgblack@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microInterNeonIop) 3867639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microInterNeonIop) 3877639Sgblack@eecs.umich.edu}}; 3887639Sgblack@eecs.umich.edu 3897639Sgblack@eecs.umich.edulet {{ 3907639Sgblack@eecs.umich.edu exec_output = '' 3917639Sgblack@eecs.umich.edu for type in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'): 3927639Sgblack@eecs.umich.edu for dRegs in (2, 3, 4): 3937639Sgblack@eecs.umich.edu Name = "MicroDeintNeon%dUop" % (dRegs * 2) 3947639Sgblack@eecs.umich.edu substDict = { "class_name" : Name, "targs" : type } 3957639Sgblack@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 3967639Sgblack@eecs.umich.edu Name = "MicroInterNeon%dUop" % (dRegs * 2) 3977639Sgblack@eecs.umich.edu substDict = { "class_name" : Name, "targs" : type } 3987639Sgblack@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 3997639Sgblack@eecs.umich.edu}}; 4007639Sgblack@eecs.umich.edu 4017639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 4027639Sgblack@eecs.umich.edu// 4037639Sgblack@eecs.umich.edu// Neon microops to pack/unpack a single lane 4047639Sgblack@eecs.umich.edu// 4057639Sgblack@eecs.umich.edu 4067639Sgblack@eecs.umich.edulet {{ 4077639Sgblack@eecs.umich.edu header_output = exec_output = '' 4087639Sgblack@eecs.umich.edu for sRegs in 1, 2: 4097639Sgblack@eecs.umich.edu baseLoadRegs = '' 4107639Sgblack@eecs.umich.edu for reg in range(sRegs): 4117639Sgblack@eecs.umich.edu baseLoadRegs += ''' 4127639Sgblack@eecs.umich.edu sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw); 4137639Sgblack@eecs.umich.edu sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw); 4147639Sgblack@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 4157639Sgblack@eecs.umich.edu "reg1" : (2 * reg + 1) } 4167639Sgblack@eecs.umich.edu for dRegs in range(sRegs, 5): 4177639Sgblack@eecs.umich.edu unloadRegs = '' 4187639Sgblack@eecs.umich.edu loadRegs = baseLoadRegs 4197639Sgblack@eecs.umich.edu for reg in range(dRegs): 4207639Sgblack@eecs.umich.edu loadRegs += ''' 4217639Sgblack@eecs.umich.edu destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0.uw); 4227639Sgblack@eecs.umich.edu destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1.uw); 4237639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 4247639Sgblack@eecs.umich.edu unloadRegs += ''' 4257639Sgblack@eecs.umich.edu FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]); 4267639Sgblack@eecs.umich.edu FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]); 4277639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 4287639Sgblack@eecs.umich.edu microUnpackNeonCode = ''' 4297639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 4307639Sgblack@eecs.umich.edu sizeof(Element); 4317639Sgblack@eecs.umich.edu 4327639Sgblack@eecs.umich.edu union SourceRegs { 4337639Sgblack@eecs.umich.edu FloatRegBits fRegs[2 * %(sRegs)d]; 4347639Sgblack@eecs.umich.edu Element elements[%(sRegs)d * perDReg]; 4357639Sgblack@eecs.umich.edu } sourceRegs; 4367639Sgblack@eecs.umich.edu 4377639Sgblack@eecs.umich.edu union DestReg { 4387639Sgblack@eecs.umich.edu FloatRegBits fRegs[2]; 4397639Sgblack@eecs.umich.edu Element elements[perDReg]; 4407639Sgblack@eecs.umich.edu } destRegs[%(dRegs)d]; 4417639Sgblack@eecs.umich.edu 4427639Sgblack@eecs.umich.edu %(loadRegs)s 4437639Sgblack@eecs.umich.edu 4447639Sgblack@eecs.umich.edu for (unsigned i = 0; i < %(dRegs)d; i++) { 4457639Sgblack@eecs.umich.edu destRegs[i].elements[lane] = sourceRegs.elements[i]; 4467639Sgblack@eecs.umich.edu } 4477639Sgblack@eecs.umich.edu 4487639Sgblack@eecs.umich.edu %(unloadRegs)s 4497639Sgblack@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 4507639Sgblack@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 4517639Sgblack@eecs.umich.edu 4527639Sgblack@eecs.umich.edu microUnpackNeonIop = \ 4537639Sgblack@eecs.umich.edu InstObjParams('unpackneon%dto%duop' % (sRegs * 2, dRegs * 2), 4547639Sgblack@eecs.umich.edu 'MicroUnpackNeon%dto%dUop' % 4557639Sgblack@eecs.umich.edu (sRegs * 2, dRegs * 2), 4567639Sgblack@eecs.umich.edu 'MicroNeonMixLaneOp', 4577639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 4587639Sgblack@eecs.umich.edu 'code' : microUnpackNeonCode }, 4597639Sgblack@eecs.umich.edu ['IsMicroop']) 4607639Sgblack@eecs.umich.edu header_output += MicroNeonMixLaneDeclare.subst(microUnpackNeonIop) 4617639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microUnpackNeonIop) 4627639Sgblack@eecs.umich.edu 4637639Sgblack@eecs.umich.edu for sRegs in 1, 2: 4647639Sgblack@eecs.umich.edu loadRegs = '' 4657639Sgblack@eecs.umich.edu for reg in range(sRegs): 4667639Sgblack@eecs.umich.edu loadRegs += ''' 4677639Sgblack@eecs.umich.edu sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw); 4687639Sgblack@eecs.umich.edu sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw); 4697639Sgblack@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 4707639Sgblack@eecs.umich.edu "reg1" : (2 * reg + 1) } 4717639Sgblack@eecs.umich.edu for dRegs in range(sRegs, 5): 4727639Sgblack@eecs.umich.edu unloadRegs = '' 4737639Sgblack@eecs.umich.edu for reg in range(dRegs): 4747639Sgblack@eecs.umich.edu unloadRegs += ''' 4757639Sgblack@eecs.umich.edu FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]); 4767639Sgblack@eecs.umich.edu FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]); 4777639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 4787639Sgblack@eecs.umich.edu microUnpackAllNeonCode = ''' 4797639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 4807639Sgblack@eecs.umich.edu sizeof(Element); 4817639Sgblack@eecs.umich.edu 4827639Sgblack@eecs.umich.edu union SourceRegs { 4837639Sgblack@eecs.umich.edu FloatRegBits fRegs[2 * %(sRegs)d]; 4847639Sgblack@eecs.umich.edu Element elements[%(sRegs)d * perDReg]; 4857639Sgblack@eecs.umich.edu } sourceRegs; 4867639Sgblack@eecs.umich.edu 4877639Sgblack@eecs.umich.edu union DestReg { 4887639Sgblack@eecs.umich.edu FloatRegBits fRegs[2]; 4897639Sgblack@eecs.umich.edu Element elements[perDReg]; 4907639Sgblack@eecs.umich.edu } destRegs[%(dRegs)d]; 4917639Sgblack@eecs.umich.edu 4927639Sgblack@eecs.umich.edu %(loadRegs)s 4937639Sgblack@eecs.umich.edu 4947639Sgblack@eecs.umich.edu for (unsigned i = 0; i < %(dRegs)d; i++) { 4957639Sgblack@eecs.umich.edu for (unsigned j = 0; j < perDReg; j++) 4967639Sgblack@eecs.umich.edu destRegs[i].elements[j] = sourceRegs.elements[i]; 4977639Sgblack@eecs.umich.edu } 4987639Sgblack@eecs.umich.edu 4997639Sgblack@eecs.umich.edu %(unloadRegs)s 5007639Sgblack@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 5017639Sgblack@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 5027639Sgblack@eecs.umich.edu 5037639Sgblack@eecs.umich.edu microUnpackAllNeonIop = \ 5047639Sgblack@eecs.umich.edu InstObjParams('unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2), 5057639Sgblack@eecs.umich.edu 'MicroUnpackAllNeon%dto%dUop' % 5067639Sgblack@eecs.umich.edu (sRegs * 2, dRegs * 2), 5077639Sgblack@eecs.umich.edu 'MicroNeonMixOp', 5087639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 5097639Sgblack@eecs.umich.edu 'code' : microUnpackAllNeonCode }, 5107639Sgblack@eecs.umich.edu ['IsMicroop']) 5117639Sgblack@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microUnpackAllNeonIop) 5127639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microUnpackAllNeonIop) 5137639Sgblack@eecs.umich.edu 5147639Sgblack@eecs.umich.edu for dRegs in 1, 2: 5157639Sgblack@eecs.umich.edu unloadRegs = '' 5167639Sgblack@eecs.umich.edu for reg in range(dRegs): 5177639Sgblack@eecs.umich.edu unloadRegs += ''' 5187639Sgblack@eecs.umich.edu FpDestP%(reg0)d.uw = gtoh(destRegs.fRegs[%(reg0)d]); 5197639Sgblack@eecs.umich.edu FpDestP%(reg1)d.uw = gtoh(destRegs.fRegs[%(reg1)d]); 5207639Sgblack@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 5217639Sgblack@eecs.umich.edu "reg1" : (2 * reg + 1) } 5227639Sgblack@eecs.umich.edu for sRegs in range(dRegs, 5): 5237639Sgblack@eecs.umich.edu loadRegs = '' 5247639Sgblack@eecs.umich.edu for reg in range(sRegs): 5257639Sgblack@eecs.umich.edu loadRegs += ''' 5267639Sgblack@eecs.umich.edu sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0.uw); 5277639Sgblack@eecs.umich.edu sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1.uw); 5287639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 5297639Sgblack@eecs.umich.edu microPackNeonCode = ''' 5307639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 5317639Sgblack@eecs.umich.edu sizeof(Element); 5327639Sgblack@eecs.umich.edu 5337639Sgblack@eecs.umich.edu union SourceReg { 5347639Sgblack@eecs.umich.edu FloatRegBits fRegs[2]; 5357639Sgblack@eecs.umich.edu Element elements[perDReg]; 5367639Sgblack@eecs.umich.edu } sourceRegs[%(sRegs)d]; 5377639Sgblack@eecs.umich.edu 5387639Sgblack@eecs.umich.edu union DestRegs { 5397639Sgblack@eecs.umich.edu FloatRegBits fRegs[2 * %(dRegs)d]; 5407639Sgblack@eecs.umich.edu Element elements[%(dRegs)d * perDReg]; 5417639Sgblack@eecs.umich.edu } destRegs; 5427639Sgblack@eecs.umich.edu 5437639Sgblack@eecs.umich.edu %(loadRegs)s 5447639Sgblack@eecs.umich.edu 5457639Sgblack@eecs.umich.edu for (unsigned i = 0; i < %(sRegs)d; i++) { 5467639Sgblack@eecs.umich.edu destRegs.elements[i] = sourceRegs[i].elements[lane]; 5477639Sgblack@eecs.umich.edu } 5487639Sgblack@eecs.umich.edu 5497639Sgblack@eecs.umich.edu %(unloadRegs)s 5507639Sgblack@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 5517639Sgblack@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 5527639Sgblack@eecs.umich.edu 5537639Sgblack@eecs.umich.edu microPackNeonIop = \ 5547639Sgblack@eecs.umich.edu InstObjParams('packneon%dto%duop' % (sRegs * 2, dRegs * 2), 5557639Sgblack@eecs.umich.edu 'MicroPackNeon%dto%dUop' % 5567639Sgblack@eecs.umich.edu (sRegs * 2, dRegs * 2), 5577639Sgblack@eecs.umich.edu 'MicroNeonMixLaneOp', 5587639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 5597639Sgblack@eecs.umich.edu 'code' : microPackNeonCode }, 5607639Sgblack@eecs.umich.edu ['IsMicroop']) 5617639Sgblack@eecs.umich.edu header_output += MicroNeonMixLaneDeclare.subst(microPackNeonIop) 5627639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microPackNeonIop) 5637639Sgblack@eecs.umich.edu}}; 5647639Sgblack@eecs.umich.edu 5657639Sgblack@eecs.umich.edulet {{ 5667639Sgblack@eecs.umich.edu exec_output = '' 5677639Sgblack@eecs.umich.edu for type in ('uint8_t', 'uint16_t', 'uint32_t'): 5687639Sgblack@eecs.umich.edu for sRegs in 1, 2: 5697639Sgblack@eecs.umich.edu for dRegs in range(sRegs, 5): 5707639Sgblack@eecs.umich.edu for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop", 5717639Sgblack@eecs.umich.edu "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop", 5727639Sgblack@eecs.umich.edu "MicroPackNeon%(dRegs)dto%(sRegs)dUop"): 5737639Sgblack@eecs.umich.edu Name = format % { "sRegs" : sRegs * 2, 5747639Sgblack@eecs.umich.edu "dRegs" : dRegs * 2 } 5757639Sgblack@eecs.umich.edu substDict = { "class_name" : Name, "targs" : type } 5767639Sgblack@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 5777639Sgblack@eecs.umich.edu}}; 5787639Sgblack@eecs.umich.edu 5796308SN/A//////////////////////////////////////////////////////////////////// 5806308SN/A// 5816308SN/A// Integer = Integer op Immediate microops 5826308SN/A// 5836308SN/A 5846308SN/Alet {{ 5856308SN/A microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 5867639Sgblack@eecs.umich.edu 'MicroIntImmOp', 5878139SMatt.Horsnell@arm.com {'code': 'URa = URb + imm;', 5886308SN/A 'predicate_test': predicateTest}, 5896308SN/A ['IsMicroop']) 5906308SN/A 5917639Sgblack@eecs.umich.edu microAddUopIop = InstObjParams('add_uop', 'MicroAddUop', 5927646Sgene.wu@arm.com 'MicroIntRegOp', 5937646Sgene.wu@arm.com {'code': 5948139SMatt.Horsnell@arm.com '''URa = URb + shift_rm_imm(URc, shiftAmt, 5957646Sgene.wu@arm.com shiftType, 5968303SAli.Saidi@ARM.com CondCodesC); 5977646Sgene.wu@arm.com ''', 5987639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 5997639Sgblack@eecs.umich.edu ['IsMicroop']) 6007639Sgblack@eecs.umich.edu 6016308SN/A microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 6027639Sgblack@eecs.umich.edu 'MicroIntImmOp', 6038139SMatt.Horsnell@arm.com {'code': 'URa = URb - imm;', 6046308SN/A 'predicate_test': predicateTest}, 6056308SN/A ['IsMicroop']) 6066308SN/A 6077646Sgene.wu@arm.com microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop', 6087646Sgene.wu@arm.com 'MicroIntRegOp', 6097646Sgene.wu@arm.com {'code': 6108139SMatt.Horsnell@arm.com '''URa = URb - shift_rm_imm(URc, shiftAmt, 6117646Sgene.wu@arm.com shiftType, 6128303SAli.Saidi@ARM.com CondCodesC); 6137646Sgene.wu@arm.com ''', 6147646Sgene.wu@arm.com 'predicate_test': predicateTest}, 6157646Sgene.wu@arm.com ['IsMicroop']) 6167646Sgene.wu@arm.com 6177646Sgene.wu@arm.com microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov', 6187646Sgene.wu@arm.com 'MicroIntMov', 6198139SMatt.Horsnell@arm.com {'code': 'IWRa = URb;', 6207646Sgene.wu@arm.com 'predicate_test': predicateTest}, 6217646Sgene.wu@arm.com ['IsMicroop']) 6227646Sgene.wu@arm.com 6238148SAli.Saidi@ARM.com microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet', 6248148SAli.Saidi@ARM.com 'MicroIntMov', 6258148SAli.Saidi@ARM.com {'code': microRetUopCode % 'URb', 6268148SAli.Saidi@ARM.com 'predicate_test': predicateTest}, 6278148SAli.Saidi@ARM.com ['IsMicroop', 'IsNonSpeculative', 6288148SAli.Saidi@ARM.com 'IsSerializeAfter']) 6298148SAli.Saidi@ARM.com 6308140SMatt.Horsnell@arm.com setPCCPSRDecl = ''' 6318140SMatt.Horsnell@arm.com CPSR cpsrOrCondCodes = URc; 6328140SMatt.Horsnell@arm.com SCTLR sctlr = Sctlr; 6338140SMatt.Horsnell@arm.com pNPC = URa; 6348303SAli.Saidi@ARM.com CPSR new_cpsr = 6358140SMatt.Horsnell@arm.com cpsrWriteByInstr(cpsrOrCondCodes, URb, 6368140SMatt.Horsnell@arm.com 0xF, true, sctlr.nmfi); 6378303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 6388303SAli.Saidi@ARM.com NextThumb = new_cpsr.t; 6398303SAli.Saidi@ARM.com NextJazelle = new_cpsr.j; 6408205SAli.Saidi@ARM.com NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) 6418140SMatt.Horsnell@arm.com | (((CPSR)URb).it1 & 0x3); 6428303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 6438303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 6448303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 6458303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 6468140SMatt.Horsnell@arm.com ''' 6478140SMatt.Horsnell@arm.com 6488140SMatt.Horsnell@arm.com microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', 6498140SMatt.Horsnell@arm.com 'MicroSetPCCPSR', 6508140SMatt.Horsnell@arm.com {'code': setPCCPSRDecl, 6518140SMatt.Horsnell@arm.com 'predicate_test': predicateTest}, 6528140SMatt.Horsnell@arm.com ['IsMicroop']) 6538140SMatt.Horsnell@arm.com 6547639Sgblack@eecs.umich.edu header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \ 6557639Sgblack@eecs.umich.edu MicroIntImmDeclare.subst(microSubiUopIop) + \ 6567646Sgene.wu@arm.com MicroIntRegDeclare.subst(microAddUopIop) + \ 6577646Sgene.wu@arm.com MicroIntRegDeclare.subst(microSubUopIop) + \ 6588140SMatt.Horsnell@arm.com MicroIntMovDeclare.subst(microUopRegMovIop) + \ 6598148SAli.Saidi@ARM.com MicroIntMovDeclare.subst(microUopRegMovRetIop) + \ 6608140SMatt.Horsnell@arm.com MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop) 6617646Sgene.wu@arm.com 6627639Sgblack@eecs.umich.edu decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \ 6637639Sgblack@eecs.umich.edu MicroIntImmConstructor.subst(microSubiUopIop) + \ 6647646Sgene.wu@arm.com MicroIntRegConstructor.subst(microAddUopIop) + \ 6657646Sgene.wu@arm.com MicroIntRegConstructor.subst(microSubUopIop) + \ 6668140SMatt.Horsnell@arm.com MicroIntMovConstructor.subst(microUopRegMovIop) + \ 6678148SAli.Saidi@ARM.com MicroIntMovConstructor.subst(microUopRegMovRetIop) + \ 6688140SMatt.Horsnell@arm.com MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop) 6697646Sgene.wu@arm.com 6706308SN/A exec_output = PredOpExecute.subst(microAddiUopIop) + \ 6717639Sgblack@eecs.umich.edu PredOpExecute.subst(microSubiUopIop) + \ 6727646Sgene.wu@arm.com PredOpExecute.subst(microAddUopIop) + \ 6737646Sgene.wu@arm.com PredOpExecute.subst(microSubUopIop) + \ 6748140SMatt.Horsnell@arm.com PredOpExecute.subst(microUopRegMovIop) + \ 6758148SAli.Saidi@ARM.com PredOpExecute.subst(microUopRegMovRetIop) + \ 6768140SMatt.Horsnell@arm.com PredOpExecute.subst(microUopSetPCCPSRIop) 6778140SMatt.Horsnell@arm.com 6786308SN/A}}; 6796019SN/A 6807134Sgblack@eecs.umich.edulet {{ 6817170Sgblack@eecs.umich.edu iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", []) 6827134Sgblack@eecs.umich.edu header_output = MacroMemDeclare.subst(iop) 6837134Sgblack@eecs.umich.edu decoder_output = MacroMemConstructor.subst(iop) 6847179Sgblack@eecs.umich.edu 6857639Sgblack@eecs.umich.edu iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", []) 6867639Sgblack@eecs.umich.edu header_output += VMemMultDeclare.subst(iop) 6877639Sgblack@eecs.umich.edu decoder_output += VMemMultConstructor.subst(iop) 6887639Sgblack@eecs.umich.edu 6897639Sgblack@eecs.umich.edu iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", []) 6907639Sgblack@eecs.umich.edu header_output += VMemSingleDeclare.subst(iop) 6917639Sgblack@eecs.umich.edu decoder_output += VMemSingleConstructor.subst(iop) 6927639Sgblack@eecs.umich.edu 6937639Sgblack@eecs.umich.edu iop = InstObjParams("vstmult", "VstMult", 'VstMultOp', "", []) 6947639Sgblack@eecs.umich.edu header_output += VMemMultDeclare.subst(iop) 6957639Sgblack@eecs.umich.edu decoder_output += VMemMultConstructor.subst(iop) 6967639Sgblack@eecs.umich.edu 6977639Sgblack@eecs.umich.edu iop = InstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", []) 6987639Sgblack@eecs.umich.edu header_output += VMemSingleDeclare.subst(iop) 6997639Sgblack@eecs.umich.edu decoder_output += VMemSingleConstructor.subst(iop) 7007639Sgblack@eecs.umich.edu 7017179Sgblack@eecs.umich.edu vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", []) 7027179Sgblack@eecs.umich.edu header_output += MacroVFPMemDeclare.subst(vfpIop) 7037179Sgblack@eecs.umich.edu decoder_output += MacroVFPMemConstructor.subst(vfpIop) 7046019SN/A}}; 705