macromem.isa revision 8139
16019SN/A// -*- mode:c++ -*-
26019SN/A
37134Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited
47134Sgblack@eecs.umich.edu// All rights reserved
57134Sgblack@eecs.umich.edu//
67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
107134Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
147134Sgblack@eecs.umich.edu//
156019SN/A// Copyright (c) 2007-2008 The Florida State University
166019SN/A// All rights reserved.
176019SN/A//
186019SN/A// Redistribution and use in source and binary forms, with or without
196019SN/A// modification, are permitted provided that the following conditions are
206019SN/A// met: redistributions of source code must retain the above copyright
216019SN/A// notice, this list of conditions and the following disclaimer;
226019SN/A// redistributions in binary form must reproduce the above copyright
236019SN/A// notice, this list of conditions and the following disclaimer in the
246019SN/A// documentation and/or other materials provided with the distribution;
256019SN/A// neither the name of the copyright holders nor the names of its
266019SN/A// contributors may be used to endorse or promote products derived from
276019SN/A// this software without specific prior written permission.
286019SN/A//
296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406019SN/A//
416019SN/A// Authors: Stephen Hines
426308SN/A//          Gabe Black
436308SN/A
446309SN/A////////////////////////////////////////////////////////////////////
456309SN/A//
466309SN/A// Load/store microops
476309SN/A//
486309SN/A
497134Sgblack@eecs.umich.edulet {{
507296Sgblack@eecs.umich.edu    microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
516309SN/A    microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
526309SN/A                                   'MicroMemOp',
537296Sgblack@eecs.umich.edu                                   {'memacc_code': microLdrUopCode,
548139SMatt.Horsnell@arm.com                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
556309SN/A                                    'predicate_test': predicateTest},
566309SN/A                                   ['IsMicroop'])
576309SN/A
587342Sgblack@eecs.umich.edu    microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
597174Sgblack@eecs.umich.edu    microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
607639Sgblack@eecs.umich.edu                                      'MicroMemOp',
617639Sgblack@eecs.umich.edu                                      {'memacc_code': microLdrFpUopCode,
627644Sali.saidi@arm.com                                       'ea_code': vfpEnabledCheckCode +
638139SMatt.Horsnell@arm.com                                           'EA = URb + (up ? imm : -imm);',
647639Sgblack@eecs.umich.edu                                       'predicate_test': predicateTest},
657639Sgblack@eecs.umich.edu                                      ['IsMicroop'])
667639Sgblack@eecs.umich.edu
677639Sgblack@eecs.umich.edu    microLdrDBFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
687639Sgblack@eecs.umich.edu    microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
697639Sgblack@eecs.umich.edu                                      'MicroMemOp',
707639Sgblack@eecs.umich.edu                                      {'memacc_code': microLdrFpUopCode,
717644Sali.saidi@arm.com                                       'ea_code': vfpEnabledCheckCode + '''
728139SMatt.Horsnell@arm.com                                        EA = URb + (up ? imm : -imm) +
737639Sgblack@eecs.umich.edu                                             (((CPSR)Cpsr).e ? 4 : 0);
747639Sgblack@eecs.umich.edu                                        ''',
757639Sgblack@eecs.umich.edu                                       'predicate_test': predicateTest},
767639Sgblack@eecs.umich.edu                                      ['IsMicroop'])
777639Sgblack@eecs.umich.edu
787639Sgblack@eecs.umich.edu    microLdrDTFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
797639Sgblack@eecs.umich.edu    microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
807639Sgblack@eecs.umich.edu                                      'MicroMemOp',
817639Sgblack@eecs.umich.edu                                      {'memacc_code': microLdrFpUopCode,
827644Sali.saidi@arm.com                                       'ea_code': vfpEnabledCheckCode + '''
838139SMatt.Horsnell@arm.com                                        EA = URb + (up ? imm : -imm) -
847639Sgblack@eecs.umich.edu                                             (((CPSR)Cpsr).e ? 4 : 0);
857639Sgblack@eecs.umich.edu                                        ''',
867639Sgblack@eecs.umich.edu                                       'predicate_test': predicateTest},
877639Sgblack@eecs.umich.edu                                      ['IsMicroop'])
887174Sgblack@eecs.umich.edu
896754SN/A    microLdrRetUopCode = '''
907296Sgblack@eecs.umich.edu        CPSR cpsr = Cpsr;
917400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
927134Sgblack@eecs.umich.edu        uint32_t newCpsr =
937400SAli.Saidi@ARM.com            cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
947134Sgblack@eecs.umich.edu        Cpsr = ~CondCodesMask & newCpsr;
957134Sgblack@eecs.umich.edu        CondCodes = CondCodesMask & newCpsr;
967797Sgblack@eecs.umich.edu        IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
977858SMatt.Horsnell@arm.com        ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
987858SMatt.Horsnell@arm.com                | (((CPSR)Spsr).it1 & 0x3);
996754SN/A    '''
1006754SN/A    microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
1016754SN/A                                      'MicroMemOp',
1026754SN/A                                      {'memacc_code': microLdrRetUopCode,
1036754SN/A                                       'ea_code':
1048139SMatt.Horsnell@arm.com                                          'EA = URb + (up ? imm : -imm);',
1057422Sgblack@eecs.umich.edu                                       'predicate_test': condPredicateTest},
1067648SAli.Saidi@ARM.com                                      ['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
1076754SN/A
1088139SMatt.Horsnell@arm.com    microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
1096309SN/A    microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
1106309SN/A                                   'MicroMemOp',
1117296Sgblack@eecs.umich.edu                                   {'memacc_code': microStrUopCode,
1127303Sgblack@eecs.umich.edu                                    'postacc_code': "",
1138139SMatt.Horsnell@arm.com                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
1146309SN/A                                    'predicate_test': predicateTest},
1156309SN/A                                   ['IsMicroop'])
1166309SN/A
1177296Sgblack@eecs.umich.edu    microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
1187174Sgblack@eecs.umich.edu    microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
1197174Sgblack@eecs.umich.edu                                     'MicroMemOp',
1207296Sgblack@eecs.umich.edu                                     {'memacc_code': microStrFpUopCode,
1217303Sgblack@eecs.umich.edu                                      'postacc_code': "",
1227644Sali.saidi@arm.com                                      'ea_code': vfpEnabledCheckCode +
1238139SMatt.Horsnell@arm.com                                           'EA = URb + (up ? imm : -imm);',
1247174Sgblack@eecs.umich.edu                                      'predicate_test': predicateTest},
1257174Sgblack@eecs.umich.edu                                     ['IsMicroop'])
1267174Sgblack@eecs.umich.edu
1277639Sgblack@eecs.umich.edu    microStrDBFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
1287639Sgblack@eecs.umich.edu    microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop',
1297639Sgblack@eecs.umich.edu                                       'MicroMemOp',
1307639Sgblack@eecs.umich.edu                                       {'memacc_code': microStrFpUopCode,
1317639Sgblack@eecs.umich.edu                                        'postacc_code': "",
1327644Sali.saidi@arm.com                                        'ea_code': vfpEnabledCheckCode + '''
1338139SMatt.Horsnell@arm.com                                         EA = URb + (up ? imm : -imm) +
1347639Sgblack@eecs.umich.edu                                              (((CPSR)Cpsr).e ? 4 : 0);
1357639Sgblack@eecs.umich.edu                                         ''',
1367639Sgblack@eecs.umich.edu                                        'predicate_test': predicateTest},
1377639Sgblack@eecs.umich.edu                                       ['IsMicroop'])
1387639Sgblack@eecs.umich.edu
1397639Sgblack@eecs.umich.edu    microStrDTFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
1407639Sgblack@eecs.umich.edu    microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop',
1417639Sgblack@eecs.umich.edu                                       'MicroMemOp',
1427639Sgblack@eecs.umich.edu                                       {'memacc_code': microStrFpUopCode,
1437639Sgblack@eecs.umich.edu                                        'postacc_code': "",
1447644Sali.saidi@arm.com                                        'ea_code': vfpEnabledCheckCode + '''
1458139SMatt.Horsnell@arm.com                                         EA = URb + (up ? imm : -imm) -
1467639Sgblack@eecs.umich.edu                                              (((CPSR)Cpsr).e ? 4 : 0);
1477639Sgblack@eecs.umich.edu                                         ''',
1487639Sgblack@eecs.umich.edu                                        'predicate_test': predicateTest},
1497639Sgblack@eecs.umich.edu                                       ['IsMicroop'])
1507639Sgblack@eecs.umich.edu
1517174Sgblack@eecs.umich.edu    header_output = decoder_output = exec_output = ''
1527174Sgblack@eecs.umich.edu
1537639Sgblack@eecs.umich.edu    loadIops = (microLdrUopIop, microLdrRetUopIop,
1547639Sgblack@eecs.umich.edu                microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop)
1557639Sgblack@eecs.umich.edu    storeIops = (microStrUopIop, microStrFpUopIop,
1567639Sgblack@eecs.umich.edu                 microStrDBFpUopIop, microStrDTFpUopIop)
1577174Sgblack@eecs.umich.edu    for iop in loadIops + storeIops:
1587174Sgblack@eecs.umich.edu        header_output += MicroMemDeclare.subst(iop)
1597174Sgblack@eecs.umich.edu        decoder_output += MicroMemConstructor.subst(iop)
1607174Sgblack@eecs.umich.edu    for iop in loadIops:
1617174Sgblack@eecs.umich.edu        exec_output += LoadExecute.subst(iop) + \
1627174Sgblack@eecs.umich.edu                       LoadInitiateAcc.subst(iop) + \
1637174Sgblack@eecs.umich.edu                       LoadCompleteAcc.subst(iop)
1647174Sgblack@eecs.umich.edu    for iop in storeIops:
1657174Sgblack@eecs.umich.edu        exec_output += StoreExecute.subst(iop) + \
1667174Sgblack@eecs.umich.edu                       StoreInitiateAcc.subst(iop) + \
1677174Sgblack@eecs.umich.edu                       StoreCompleteAcc.subst(iop)
1686309SN/A}};
1696308SN/A
1707639Sgblack@eecs.umich.edulet {{
1717639Sgblack@eecs.umich.edu    exec_output = header_output = ''
1727639Sgblack@eecs.umich.edu
1738139SMatt.Horsnell@arm.com    eaCode = 'EA = URa + imm;'
1747639Sgblack@eecs.umich.edu
1757639Sgblack@eecs.umich.edu    for size in (1, 2, 3, 4, 6, 8, 12, 16):
1767639Sgblack@eecs.umich.edu        # Set up the memory access.
1777639Sgblack@eecs.umich.edu        regs = (size + 3) // 4
1787639Sgblack@eecs.umich.edu        subst = { "size" : size, "regs" : regs }
1797639Sgblack@eecs.umich.edu        memDecl = '''
1807639Sgblack@eecs.umich.edu        union MemUnion {
1817639Sgblack@eecs.umich.edu            uint8_t bytes[%(size)d];
1827639Sgblack@eecs.umich.edu            Element elements[%(size)d / sizeof(Element)];
1837639Sgblack@eecs.umich.edu            uint32_t floatRegBits[%(regs)d];
1847639Sgblack@eecs.umich.edu        };
1857639Sgblack@eecs.umich.edu        ''' % subst
1867639Sgblack@eecs.umich.edu
1877639Sgblack@eecs.umich.edu        # Do endian conversion for all the elements.
1887639Sgblack@eecs.umich.edu        convCode = '''
1897639Sgblack@eecs.umich.edu            const unsigned eCount = sizeof(memUnion.elements) /
1907639Sgblack@eecs.umich.edu                                    sizeof(memUnion.elements[0]);
1917639Sgblack@eecs.umich.edu            if (((CPSR)Cpsr).e) {
1927639Sgblack@eecs.umich.edu                for (unsigned i = 0; i < eCount; i++) {
1937639Sgblack@eecs.umich.edu                    memUnion.elements[i] = gtobe(memUnion.elements[i]);
1947639Sgblack@eecs.umich.edu                }
1957639Sgblack@eecs.umich.edu            } else {
1967639Sgblack@eecs.umich.edu                for (unsigned i = 0; i < eCount; i++) {
1977639Sgblack@eecs.umich.edu                    memUnion.elements[i] = gtole(memUnion.elements[i]);
1987639Sgblack@eecs.umich.edu                }
1997639Sgblack@eecs.umich.edu            }
2007639Sgblack@eecs.umich.edu        '''
2017639Sgblack@eecs.umich.edu
2027639Sgblack@eecs.umich.edu        # Offload everything into registers
2037639Sgblack@eecs.umich.edu        regSetCode = ''
2047639Sgblack@eecs.umich.edu        for reg in range(regs):
2057639Sgblack@eecs.umich.edu            mask = ''
2067639Sgblack@eecs.umich.edu            if reg == regs - 1:
2077639Sgblack@eecs.umich.edu                mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size))
2087639Sgblack@eecs.umich.edu            regSetCode += '''
2097639Sgblack@eecs.umich.edu            FpDestP%(reg)d.uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s;
2107639Sgblack@eecs.umich.edu            ''' % { "reg" : reg, "mask" : mask }
2117639Sgblack@eecs.umich.edu
2127639Sgblack@eecs.umich.edu        # Pull everything in from registers
2137639Sgblack@eecs.umich.edu        regGetCode = ''
2147639Sgblack@eecs.umich.edu        for reg in range(regs):
2157639Sgblack@eecs.umich.edu            regGetCode += '''
2167639Sgblack@eecs.umich.edu            memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d.uw);
2177639Sgblack@eecs.umich.edu            ''' % { "reg" : reg }
2187639Sgblack@eecs.umich.edu
2197639Sgblack@eecs.umich.edu        loadMemAccCode = convCode + regSetCode
2207639Sgblack@eecs.umich.edu        storeMemAccCode = regGetCode + convCode
2217639Sgblack@eecs.umich.edu
2227639Sgblack@eecs.umich.edu        loadIop = InstObjParams('ldrneon%(size)d_uop' % subst,
2237639Sgblack@eecs.umich.edu                                'MicroLdrNeon%(size)dUop' % subst,
2247639Sgblack@eecs.umich.edu                                'MicroNeonMemOp',
2257639Sgblack@eecs.umich.edu                                { 'mem_decl' : memDecl,
2267639Sgblack@eecs.umich.edu                                  'size' : size,
2277639Sgblack@eecs.umich.edu                                  'memacc_code' : loadMemAccCode,
2287644Sali.saidi@arm.com                                  'ea_code' : simdEnabledCheckCode + eaCode,
2297639Sgblack@eecs.umich.edu                                  'predicate_test' : predicateTest },
2307639Sgblack@eecs.umich.edu                                [ 'IsMicroop', 'IsMemRef', 'IsLoad' ])
2317639Sgblack@eecs.umich.edu        storeIop = InstObjParams('strneon%(size)d_uop' % subst,
2327639Sgblack@eecs.umich.edu                                 'MicroStrNeon%(size)dUop' % subst,
2337639Sgblack@eecs.umich.edu                                 'MicroNeonMemOp',
2347639Sgblack@eecs.umich.edu                                 { 'mem_decl' : memDecl,
2357639Sgblack@eecs.umich.edu                                   'size' : size,
2367639Sgblack@eecs.umich.edu                                   'memacc_code' : storeMemAccCode,
2377644Sali.saidi@arm.com                                   'ea_code' : simdEnabledCheckCode + eaCode,
2387639Sgblack@eecs.umich.edu                                   'predicate_test' : predicateTest },
2397639Sgblack@eecs.umich.edu                                 [ 'IsMicroop', 'IsMemRef', 'IsStore' ])
2407639Sgblack@eecs.umich.edu
2417639Sgblack@eecs.umich.edu        exec_output += NeonLoadExecute.subst(loadIop) + \
2427639Sgblack@eecs.umich.edu                       NeonLoadInitiateAcc.subst(loadIop) + \
2437639Sgblack@eecs.umich.edu                       NeonLoadCompleteAcc.subst(loadIop) + \
2447639Sgblack@eecs.umich.edu                       NeonStoreExecute.subst(storeIop) + \
2457639Sgblack@eecs.umich.edu                       NeonStoreInitiateAcc.subst(storeIop) + \
2467639Sgblack@eecs.umich.edu                       NeonStoreCompleteAcc.subst(storeIop)
2477639Sgblack@eecs.umich.edu        header_output += MicroNeonMemDeclare.subst(loadIop) + \
2487639Sgblack@eecs.umich.edu                         MicroNeonMemDeclare.subst(storeIop)
2497639Sgblack@eecs.umich.edu}};
2507639Sgblack@eecs.umich.edu
2517639Sgblack@eecs.umich.edulet {{
2527639Sgblack@eecs.umich.edu    exec_output = ''
2537639Sgblack@eecs.umich.edu    for eSize, type in (1, 'uint8_t'), \
2547639Sgblack@eecs.umich.edu                       (2, 'uint16_t'), \
2557639Sgblack@eecs.umich.edu                       (4, 'uint32_t'), \
2567639Sgblack@eecs.umich.edu                       (8, 'uint64_t'):
2577639Sgblack@eecs.umich.edu        size = eSize
2587639Sgblack@eecs.umich.edu        # An instruction handles no more than 16 bytes and no more than
2597639Sgblack@eecs.umich.edu        # 4 elements, or the number of elements needed to fill 8 or 16 bytes.
2607639Sgblack@eecs.umich.edu        sizes = set((16, 8))
2617639Sgblack@eecs.umich.edu        for count in 1, 2, 3, 4:
2627639Sgblack@eecs.umich.edu            size = count * eSize
2637639Sgblack@eecs.umich.edu            if size <= 16:
2647639Sgblack@eecs.umich.edu                sizes.add(size)
2657639Sgblack@eecs.umich.edu        for size in sizes:
2667639Sgblack@eecs.umich.edu            substDict = {
2677639Sgblack@eecs.umich.edu                "class_name" : "MicroLdrNeon%dUop" % size,
2687639Sgblack@eecs.umich.edu                "targs" : type
2697639Sgblack@eecs.umich.edu            }
2707639Sgblack@eecs.umich.edu            exec_output += MicroNeonMemExecDeclare.subst(substDict)
2717639Sgblack@eecs.umich.edu            substDict["class_name"] = "MicroStrNeon%dUop" % size
2727639Sgblack@eecs.umich.edu            exec_output += MicroNeonMemExecDeclare.subst(substDict)
2737639Sgblack@eecs.umich.edu            size += eSize
2747639Sgblack@eecs.umich.edu}};
2757639Sgblack@eecs.umich.edu
2767639Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////
2777639Sgblack@eecs.umich.edu//
2787639Sgblack@eecs.umich.edu// Neon (de)interlacing microops
2797639Sgblack@eecs.umich.edu//
2807639Sgblack@eecs.umich.edu
2817639Sgblack@eecs.umich.edulet {{
2827639Sgblack@eecs.umich.edu    header_output = exec_output = ''
2837639Sgblack@eecs.umich.edu    for dRegs in (2, 3, 4):
2847639Sgblack@eecs.umich.edu        loadConv = ''
2857639Sgblack@eecs.umich.edu        unloadConv = ''
2867639Sgblack@eecs.umich.edu        for dReg in range(dRegs):
2877639Sgblack@eecs.umich.edu            loadConv += '''
2887639Sgblack@eecs.umich.edu                conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d.uw);
2897639Sgblack@eecs.umich.edu                conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d.uw);
2907639Sgblack@eecs.umich.edu            ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
2917639Sgblack@eecs.umich.edu            unloadConv += '''
2927639Sgblack@eecs.umich.edu                FpDestS%(dReg)dP0.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]);
2937639Sgblack@eecs.umich.edu                FpDestS%(dReg)dP1.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]);
2947639Sgblack@eecs.umich.edu            ''' % { "dReg" : dReg }
2957639Sgblack@eecs.umich.edu        microDeintNeonCode = '''
2967639Sgblack@eecs.umich.edu            const unsigned dRegs = %(dRegs)d;
2977639Sgblack@eecs.umich.edu            const unsigned regs = 2 * dRegs;
2987639Sgblack@eecs.umich.edu            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
2997639Sgblack@eecs.umich.edu                                     sizeof(Element);
3007639Sgblack@eecs.umich.edu            union convStruct {
3017639Sgblack@eecs.umich.edu                FloatRegBits cRegs[regs];
3027639Sgblack@eecs.umich.edu                Element elements[dRegs * perDReg];
3037639Sgblack@eecs.umich.edu            } conv1, conv2;
3047639Sgblack@eecs.umich.edu
3057639Sgblack@eecs.umich.edu            %(loadConv)s
3067639Sgblack@eecs.umich.edu
3077639Sgblack@eecs.umich.edu            unsigned srcElem = 0;
3087639Sgblack@eecs.umich.edu            for (unsigned destOffset = 0;
3097639Sgblack@eecs.umich.edu                    destOffset < perDReg; destOffset++) {
3107639Sgblack@eecs.umich.edu                for (unsigned dReg = 0; dReg < dRegs; dReg++) {
3117639Sgblack@eecs.umich.edu                    conv2.elements[dReg * perDReg + destOffset] =
3127639Sgblack@eecs.umich.edu                        conv1.elements[srcElem++];
3137639Sgblack@eecs.umich.edu                }
3147639Sgblack@eecs.umich.edu            }
3157639Sgblack@eecs.umich.edu
3167639Sgblack@eecs.umich.edu            %(unloadConv)s
3177639Sgblack@eecs.umich.edu        ''' % { "dRegs" : dRegs,
3187639Sgblack@eecs.umich.edu                "loadConv" : loadConv,
3197639Sgblack@eecs.umich.edu                "unloadConv" : unloadConv }
3207639Sgblack@eecs.umich.edu        microDeintNeonIop = \
3217639Sgblack@eecs.umich.edu            InstObjParams('deintneon%duop' % (dRegs * 2),
3227639Sgblack@eecs.umich.edu                          'MicroDeintNeon%dUop' % (dRegs * 2),
3237639Sgblack@eecs.umich.edu                          'MicroNeonMixOp',
3247639Sgblack@eecs.umich.edu                          { 'predicate_test': predicateTest,
3257639Sgblack@eecs.umich.edu                            'code' : microDeintNeonCode },
3267639Sgblack@eecs.umich.edu                            ['IsMicroop'])
3277639Sgblack@eecs.umich.edu        header_output += MicroNeonMixDeclare.subst(microDeintNeonIop)
3287639Sgblack@eecs.umich.edu        exec_output += MicroNeonMixExecute.subst(microDeintNeonIop)
3297639Sgblack@eecs.umich.edu
3307639Sgblack@eecs.umich.edu        loadConv = ''
3317639Sgblack@eecs.umich.edu        unloadConv = ''
3327639Sgblack@eecs.umich.edu        for dReg in range(dRegs):
3337639Sgblack@eecs.umich.edu            loadConv += '''
3347639Sgblack@eecs.umich.edu                conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0.uw);
3357639Sgblack@eecs.umich.edu                conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1.uw);
3367639Sgblack@eecs.umich.edu            ''' % { "dReg" : dReg }
3377639Sgblack@eecs.umich.edu            unloadConv += '''
3387639Sgblack@eecs.umich.edu                FpDestP%(sReg0)d.uw = gtoh(conv2.cRegs[%(sReg0)d]);
3397639Sgblack@eecs.umich.edu                FpDestP%(sReg1)d.uw = gtoh(conv2.cRegs[%(sReg1)d]);
3407639Sgblack@eecs.umich.edu            ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
3417639Sgblack@eecs.umich.edu        microInterNeonCode = '''
3427639Sgblack@eecs.umich.edu            const unsigned dRegs = %(dRegs)d;
3437639Sgblack@eecs.umich.edu            const unsigned regs = 2 * dRegs;
3447639Sgblack@eecs.umich.edu            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
3457639Sgblack@eecs.umich.edu                                     sizeof(Element);
3467639Sgblack@eecs.umich.edu            union convStruct {
3477639Sgblack@eecs.umich.edu                FloatRegBits cRegs[regs];
3487639Sgblack@eecs.umich.edu                Element elements[dRegs * perDReg];
3497639Sgblack@eecs.umich.edu            } conv1, conv2;
3507639Sgblack@eecs.umich.edu
3517639Sgblack@eecs.umich.edu            %(loadConv)s
3527639Sgblack@eecs.umich.edu
3537639Sgblack@eecs.umich.edu            unsigned destElem = 0;
3547639Sgblack@eecs.umich.edu            for (unsigned srcOffset = 0;
3557639Sgblack@eecs.umich.edu                    srcOffset < perDReg; srcOffset++) {
3567639Sgblack@eecs.umich.edu                for (unsigned dReg = 0; dReg < dRegs; dReg++) {
3577639Sgblack@eecs.umich.edu                    conv2.elements[destElem++] =
3587639Sgblack@eecs.umich.edu                        conv1.elements[dReg * perDReg + srcOffset];
3597639Sgblack@eecs.umich.edu                }
3607639Sgblack@eecs.umich.edu            }
3617639Sgblack@eecs.umich.edu
3627639Sgblack@eecs.umich.edu            %(unloadConv)s
3637639Sgblack@eecs.umich.edu        ''' % { "dRegs" : dRegs,
3647639Sgblack@eecs.umich.edu                "loadConv" : loadConv,
3657639Sgblack@eecs.umich.edu                "unloadConv" : unloadConv }
3667639Sgblack@eecs.umich.edu        microInterNeonIop = \
3677639Sgblack@eecs.umich.edu            InstObjParams('interneon%duop' % (dRegs * 2),
3687639Sgblack@eecs.umich.edu                          'MicroInterNeon%dUop' % (dRegs * 2),
3697639Sgblack@eecs.umich.edu                          'MicroNeonMixOp',
3707639Sgblack@eecs.umich.edu                          { 'predicate_test': predicateTest,
3717639Sgblack@eecs.umich.edu                            'code' : microInterNeonCode },
3727639Sgblack@eecs.umich.edu                            ['IsMicroop'])
3737639Sgblack@eecs.umich.edu        header_output += MicroNeonMixDeclare.subst(microInterNeonIop)
3747639Sgblack@eecs.umich.edu        exec_output += MicroNeonMixExecute.subst(microInterNeonIop)
3757639Sgblack@eecs.umich.edu}};
3767639Sgblack@eecs.umich.edu
3777639Sgblack@eecs.umich.edulet {{
3787639Sgblack@eecs.umich.edu    exec_output = ''
3797639Sgblack@eecs.umich.edu    for type in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'):
3807639Sgblack@eecs.umich.edu        for dRegs in (2, 3, 4):
3817639Sgblack@eecs.umich.edu            Name = "MicroDeintNeon%dUop" % (dRegs * 2)
3827639Sgblack@eecs.umich.edu            substDict = { "class_name" : Name, "targs" : type }
3837639Sgblack@eecs.umich.edu            exec_output += MicroNeonExecDeclare.subst(substDict)
3847639Sgblack@eecs.umich.edu            Name = "MicroInterNeon%dUop" % (dRegs * 2)
3857639Sgblack@eecs.umich.edu            substDict = { "class_name" : Name, "targs" : type }
3867639Sgblack@eecs.umich.edu            exec_output += MicroNeonExecDeclare.subst(substDict)
3877639Sgblack@eecs.umich.edu}};
3887639Sgblack@eecs.umich.edu
3897639Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////
3907639Sgblack@eecs.umich.edu//
3917639Sgblack@eecs.umich.edu// Neon microops to pack/unpack a single lane
3927639Sgblack@eecs.umich.edu//
3937639Sgblack@eecs.umich.edu
3947639Sgblack@eecs.umich.edulet {{
3957639Sgblack@eecs.umich.edu    header_output = exec_output = ''
3967639Sgblack@eecs.umich.edu    for sRegs in 1, 2:
3977639Sgblack@eecs.umich.edu        baseLoadRegs = ''
3987639Sgblack@eecs.umich.edu        for reg in range(sRegs):
3997639Sgblack@eecs.umich.edu            baseLoadRegs += '''
4007639Sgblack@eecs.umich.edu                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw);
4017639Sgblack@eecs.umich.edu                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw);
4027639Sgblack@eecs.umich.edu            ''' % { "reg0" : (2 * reg + 0),
4037639Sgblack@eecs.umich.edu                    "reg1" : (2 * reg + 1) }
4047639Sgblack@eecs.umich.edu        for dRegs in range(sRegs, 5):
4057639Sgblack@eecs.umich.edu            unloadRegs = ''
4067639Sgblack@eecs.umich.edu            loadRegs = baseLoadRegs
4077639Sgblack@eecs.umich.edu            for reg in range(dRegs):
4087639Sgblack@eecs.umich.edu                loadRegs += '''
4097639Sgblack@eecs.umich.edu                    destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0.uw);
4107639Sgblack@eecs.umich.edu                    destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1.uw);
4117639Sgblack@eecs.umich.edu                ''' % { "reg" : reg }
4127639Sgblack@eecs.umich.edu                unloadRegs += '''
4137639Sgblack@eecs.umich.edu                    FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]);
4147639Sgblack@eecs.umich.edu                    FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]);
4157639Sgblack@eecs.umich.edu                ''' % { "reg" : reg }
4167639Sgblack@eecs.umich.edu            microUnpackNeonCode = '''
4177639Sgblack@eecs.umich.edu            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
4187639Sgblack@eecs.umich.edu                                     sizeof(Element);
4197639Sgblack@eecs.umich.edu
4207639Sgblack@eecs.umich.edu            union SourceRegs {
4217639Sgblack@eecs.umich.edu                FloatRegBits fRegs[2 * %(sRegs)d];
4227639Sgblack@eecs.umich.edu                Element elements[%(sRegs)d * perDReg];
4237639Sgblack@eecs.umich.edu            } sourceRegs;
4247639Sgblack@eecs.umich.edu
4257639Sgblack@eecs.umich.edu            union DestReg {
4267639Sgblack@eecs.umich.edu                FloatRegBits fRegs[2];
4277639Sgblack@eecs.umich.edu                Element elements[perDReg];
4287639Sgblack@eecs.umich.edu            } destRegs[%(dRegs)d];
4297639Sgblack@eecs.umich.edu
4307639Sgblack@eecs.umich.edu            %(loadRegs)s
4317639Sgblack@eecs.umich.edu
4327639Sgblack@eecs.umich.edu            for (unsigned i = 0; i < %(dRegs)d; i++) {
4337639Sgblack@eecs.umich.edu                destRegs[i].elements[lane] = sourceRegs.elements[i];
4347639Sgblack@eecs.umich.edu            }
4357639Sgblack@eecs.umich.edu
4367639Sgblack@eecs.umich.edu            %(unloadRegs)s
4377639Sgblack@eecs.umich.edu            ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
4387639Sgblack@eecs.umich.edu                    "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
4397639Sgblack@eecs.umich.edu
4407639Sgblack@eecs.umich.edu            microUnpackNeonIop = \
4417639Sgblack@eecs.umich.edu                InstObjParams('unpackneon%dto%duop' % (sRegs * 2, dRegs * 2),
4427639Sgblack@eecs.umich.edu                              'MicroUnpackNeon%dto%dUop' %
4437639Sgblack@eecs.umich.edu                                    (sRegs * 2, dRegs * 2),
4447639Sgblack@eecs.umich.edu                              'MicroNeonMixLaneOp',
4457639Sgblack@eecs.umich.edu                              { 'predicate_test': predicateTest,
4467639Sgblack@eecs.umich.edu                                'code' : microUnpackNeonCode },
4477639Sgblack@eecs.umich.edu                                ['IsMicroop'])
4487639Sgblack@eecs.umich.edu            header_output += MicroNeonMixLaneDeclare.subst(microUnpackNeonIop)
4497639Sgblack@eecs.umich.edu            exec_output += MicroNeonMixExecute.subst(microUnpackNeonIop)
4507639Sgblack@eecs.umich.edu
4517639Sgblack@eecs.umich.edu    for sRegs in 1, 2:
4527639Sgblack@eecs.umich.edu        loadRegs = ''
4537639Sgblack@eecs.umich.edu        for reg in range(sRegs):
4547639Sgblack@eecs.umich.edu            loadRegs += '''
4557639Sgblack@eecs.umich.edu                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw);
4567639Sgblack@eecs.umich.edu                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw);
4577639Sgblack@eecs.umich.edu            ''' % { "reg0" : (2 * reg + 0),
4587639Sgblack@eecs.umich.edu                    "reg1" : (2 * reg + 1) }
4597639Sgblack@eecs.umich.edu        for dRegs in range(sRegs, 5):
4607639Sgblack@eecs.umich.edu            unloadRegs = ''
4617639Sgblack@eecs.umich.edu            for reg in range(dRegs):
4627639Sgblack@eecs.umich.edu                unloadRegs += '''
4637639Sgblack@eecs.umich.edu                    FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]);
4647639Sgblack@eecs.umich.edu                    FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]);
4657639Sgblack@eecs.umich.edu                ''' % { "reg" : reg }
4667639Sgblack@eecs.umich.edu            microUnpackAllNeonCode = '''
4677639Sgblack@eecs.umich.edu            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
4687639Sgblack@eecs.umich.edu                                     sizeof(Element);
4697639Sgblack@eecs.umich.edu
4707639Sgblack@eecs.umich.edu            union SourceRegs {
4717639Sgblack@eecs.umich.edu                FloatRegBits fRegs[2 * %(sRegs)d];
4727639Sgblack@eecs.umich.edu                Element elements[%(sRegs)d * perDReg];
4737639Sgblack@eecs.umich.edu            } sourceRegs;
4747639Sgblack@eecs.umich.edu
4757639Sgblack@eecs.umich.edu            union DestReg {
4767639Sgblack@eecs.umich.edu                FloatRegBits fRegs[2];
4777639Sgblack@eecs.umich.edu                Element elements[perDReg];
4787639Sgblack@eecs.umich.edu            } destRegs[%(dRegs)d];
4797639Sgblack@eecs.umich.edu
4807639Sgblack@eecs.umich.edu            %(loadRegs)s
4817639Sgblack@eecs.umich.edu
4827639Sgblack@eecs.umich.edu            for (unsigned i = 0; i < %(dRegs)d; i++) {
4837639Sgblack@eecs.umich.edu                for (unsigned j = 0; j < perDReg; j++)
4847639Sgblack@eecs.umich.edu                    destRegs[i].elements[j] = sourceRegs.elements[i];
4857639Sgblack@eecs.umich.edu            }
4867639Sgblack@eecs.umich.edu
4877639Sgblack@eecs.umich.edu            %(unloadRegs)s
4887639Sgblack@eecs.umich.edu            ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
4897639Sgblack@eecs.umich.edu                    "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
4907639Sgblack@eecs.umich.edu
4917639Sgblack@eecs.umich.edu            microUnpackAllNeonIop = \
4927639Sgblack@eecs.umich.edu                InstObjParams('unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2),
4937639Sgblack@eecs.umich.edu                              'MicroUnpackAllNeon%dto%dUop' %
4947639Sgblack@eecs.umich.edu                                    (sRegs * 2, dRegs * 2),
4957639Sgblack@eecs.umich.edu                              'MicroNeonMixOp',
4967639Sgblack@eecs.umich.edu                              { 'predicate_test': predicateTest,
4977639Sgblack@eecs.umich.edu                                'code' : microUnpackAllNeonCode },
4987639Sgblack@eecs.umich.edu                                ['IsMicroop'])
4997639Sgblack@eecs.umich.edu            header_output += MicroNeonMixDeclare.subst(microUnpackAllNeonIop)
5007639Sgblack@eecs.umich.edu            exec_output += MicroNeonMixExecute.subst(microUnpackAllNeonIop)
5017639Sgblack@eecs.umich.edu
5027639Sgblack@eecs.umich.edu    for dRegs in 1, 2:
5037639Sgblack@eecs.umich.edu        unloadRegs = ''
5047639Sgblack@eecs.umich.edu        for reg in range(dRegs):
5057639Sgblack@eecs.umich.edu            unloadRegs += '''
5067639Sgblack@eecs.umich.edu                FpDestP%(reg0)d.uw = gtoh(destRegs.fRegs[%(reg0)d]);
5077639Sgblack@eecs.umich.edu                FpDestP%(reg1)d.uw = gtoh(destRegs.fRegs[%(reg1)d]);
5087639Sgblack@eecs.umich.edu            ''' % { "reg0" : (2 * reg + 0),
5097639Sgblack@eecs.umich.edu                    "reg1" : (2 * reg + 1) }
5107639Sgblack@eecs.umich.edu        for sRegs in range(dRegs, 5):
5117639Sgblack@eecs.umich.edu            loadRegs = ''
5127639Sgblack@eecs.umich.edu            for reg in range(sRegs):
5137639Sgblack@eecs.umich.edu                loadRegs += '''
5147639Sgblack@eecs.umich.edu                    sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0.uw);
5157639Sgblack@eecs.umich.edu                    sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1.uw);
5167639Sgblack@eecs.umich.edu                ''' % { "reg" : reg }
5177639Sgblack@eecs.umich.edu            microPackNeonCode = '''
5187639Sgblack@eecs.umich.edu            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
5197639Sgblack@eecs.umich.edu                                     sizeof(Element);
5207639Sgblack@eecs.umich.edu
5217639Sgblack@eecs.umich.edu            union SourceReg {
5227639Sgblack@eecs.umich.edu                FloatRegBits fRegs[2];
5237639Sgblack@eecs.umich.edu                Element elements[perDReg];
5247639Sgblack@eecs.umich.edu            } sourceRegs[%(sRegs)d];
5257639Sgblack@eecs.umich.edu
5267639Sgblack@eecs.umich.edu            union DestRegs {
5277639Sgblack@eecs.umich.edu                FloatRegBits fRegs[2 * %(dRegs)d];
5287639Sgblack@eecs.umich.edu                Element elements[%(dRegs)d * perDReg];
5297639Sgblack@eecs.umich.edu            } destRegs;
5307639Sgblack@eecs.umich.edu
5317639Sgblack@eecs.umich.edu            %(loadRegs)s
5327639Sgblack@eecs.umich.edu
5337639Sgblack@eecs.umich.edu            for (unsigned i = 0; i < %(sRegs)d; i++) {
5347639Sgblack@eecs.umich.edu                destRegs.elements[i] = sourceRegs[i].elements[lane];
5357639Sgblack@eecs.umich.edu            }
5367639Sgblack@eecs.umich.edu
5377639Sgblack@eecs.umich.edu            %(unloadRegs)s
5387639Sgblack@eecs.umich.edu            ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
5397639Sgblack@eecs.umich.edu                    "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
5407639Sgblack@eecs.umich.edu
5417639Sgblack@eecs.umich.edu            microPackNeonIop = \
5427639Sgblack@eecs.umich.edu                InstObjParams('packneon%dto%duop' % (sRegs * 2, dRegs * 2),
5437639Sgblack@eecs.umich.edu                              'MicroPackNeon%dto%dUop' %
5447639Sgblack@eecs.umich.edu                                    (sRegs * 2, dRegs * 2),
5457639Sgblack@eecs.umich.edu                              'MicroNeonMixLaneOp',
5467639Sgblack@eecs.umich.edu                              { 'predicate_test': predicateTest,
5477639Sgblack@eecs.umich.edu                                'code' : microPackNeonCode },
5487639Sgblack@eecs.umich.edu                                ['IsMicroop'])
5497639Sgblack@eecs.umich.edu            header_output += MicroNeonMixLaneDeclare.subst(microPackNeonIop)
5507639Sgblack@eecs.umich.edu            exec_output += MicroNeonMixExecute.subst(microPackNeonIop)
5517639Sgblack@eecs.umich.edu}};
5527639Sgblack@eecs.umich.edu
5537639Sgblack@eecs.umich.edulet {{
5547639Sgblack@eecs.umich.edu    exec_output = ''
5557639Sgblack@eecs.umich.edu    for type in ('uint8_t', 'uint16_t', 'uint32_t'):
5567639Sgblack@eecs.umich.edu        for sRegs in 1, 2:
5577639Sgblack@eecs.umich.edu            for dRegs in range(sRegs, 5):
5587639Sgblack@eecs.umich.edu                for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop",
5597639Sgblack@eecs.umich.edu                               "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop",
5607639Sgblack@eecs.umich.edu                               "MicroPackNeon%(dRegs)dto%(sRegs)dUop"):
5617639Sgblack@eecs.umich.edu                    Name = format % { "sRegs" : sRegs * 2,
5627639Sgblack@eecs.umich.edu                                      "dRegs" : dRegs * 2 }
5637639Sgblack@eecs.umich.edu                    substDict = { "class_name" : Name, "targs" : type }
5647639Sgblack@eecs.umich.edu                    exec_output += MicroNeonExecDeclare.subst(substDict)
5657639Sgblack@eecs.umich.edu}};
5667639Sgblack@eecs.umich.edu
5676308SN/A////////////////////////////////////////////////////////////////////
5686308SN/A//
5696308SN/A// Integer = Integer op Immediate microops
5706308SN/A//
5716308SN/A
5726308SN/Alet {{
5736308SN/A    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
5747639Sgblack@eecs.umich.edu                                    'MicroIntImmOp',
5758139SMatt.Horsnell@arm.com                                    {'code': 'URa = URb + imm;',
5766308SN/A                                     'predicate_test': predicateTest},
5776308SN/A                                    ['IsMicroop'])
5786308SN/A
5797639Sgblack@eecs.umich.edu    microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
5807646Sgene.wu@arm.com                                   'MicroIntRegOp',
5817646Sgene.wu@arm.com                                   {'code':
5828139SMatt.Horsnell@arm.com                                    '''URa = URb + shift_rm_imm(URc, shiftAmt,
5837646Sgene.wu@arm.com                                                              shiftType,
5847646Sgene.wu@arm.com                                                              CondCodes<29:>);
5857646Sgene.wu@arm.com                                    ''',
5867639Sgblack@eecs.umich.edu                                    'predicate_test': predicateTest},
5877639Sgblack@eecs.umich.edu                                   ['IsMicroop'])
5887639Sgblack@eecs.umich.edu
5896308SN/A    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
5907639Sgblack@eecs.umich.edu                                    'MicroIntImmOp',
5918139SMatt.Horsnell@arm.com                                    {'code': 'URa = URb - imm;',
5926308SN/A                                     'predicate_test': predicateTest},
5936308SN/A                                    ['IsMicroop'])
5946308SN/A
5957646Sgene.wu@arm.com    microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
5967646Sgene.wu@arm.com                                   'MicroIntRegOp',
5977646Sgene.wu@arm.com                                   {'code':
5988139SMatt.Horsnell@arm.com                                    '''URa = URb - shift_rm_imm(URc, shiftAmt,
5997646Sgene.wu@arm.com                                                              shiftType,
6007646Sgene.wu@arm.com                                                              CondCodes<29:>);
6017646Sgene.wu@arm.com                                    ''',
6027646Sgene.wu@arm.com                                    'predicate_test': predicateTest},
6037646Sgene.wu@arm.com                                   ['IsMicroop'])
6047646Sgene.wu@arm.com
6057646Sgene.wu@arm.com    microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
6067646Sgene.wu@arm.com                                   'MicroIntMov',
6078139SMatt.Horsnell@arm.com                                   {'code': 'IWRa = URb;',
6087646Sgene.wu@arm.com                                    'predicate_test': predicateTest},
6097646Sgene.wu@arm.com                                   ['IsMicroop'])
6107646Sgene.wu@arm.com
6117639Sgblack@eecs.umich.edu    header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
6127639Sgblack@eecs.umich.edu                    MicroIntImmDeclare.subst(microSubiUopIop) + \
6137646Sgene.wu@arm.com                    MicroIntRegDeclare.subst(microAddUopIop) + \
6147646Sgene.wu@arm.com                    MicroIntRegDeclare.subst(microSubUopIop) + \
6157646Sgene.wu@arm.com                    MicroIntMovDeclare.subst(microUopRegMovIop)
6167646Sgene.wu@arm.com
6177639Sgblack@eecs.umich.edu    decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
6187639Sgblack@eecs.umich.edu                     MicroIntImmConstructor.subst(microSubiUopIop) + \
6197646Sgene.wu@arm.com                     MicroIntRegConstructor.subst(microAddUopIop) + \
6207646Sgene.wu@arm.com                     MicroIntRegConstructor.subst(microSubUopIop) + \
6217646Sgene.wu@arm.com                     MicroIntMovConstructor.subst(microUopRegMovIop)
6227646Sgene.wu@arm.com
6236308SN/A    exec_output = PredOpExecute.subst(microAddiUopIop) + \
6247639Sgblack@eecs.umich.edu                  PredOpExecute.subst(microSubiUopIop) + \
6257646Sgene.wu@arm.com                  PredOpExecute.subst(microAddUopIop) + \
6267646Sgene.wu@arm.com                  PredOpExecute.subst(microSubUopIop) + \
6277646Sgene.wu@arm.com                  PredOpExecute.subst(microUopRegMovIop)
6286308SN/A}};
6296019SN/A
6307134Sgblack@eecs.umich.edulet {{
6317170Sgblack@eecs.umich.edu    iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
6327134Sgblack@eecs.umich.edu    header_output = MacroMemDeclare.subst(iop)
6337134Sgblack@eecs.umich.edu    decoder_output = MacroMemConstructor.subst(iop)
6347179Sgblack@eecs.umich.edu
6357639Sgblack@eecs.umich.edu    iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])
6367639Sgblack@eecs.umich.edu    header_output += VMemMultDeclare.subst(iop)
6377639Sgblack@eecs.umich.edu    decoder_output += VMemMultConstructor.subst(iop)
6387639Sgblack@eecs.umich.edu
6397639Sgblack@eecs.umich.edu    iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", [])
6407639Sgblack@eecs.umich.edu    header_output += VMemSingleDeclare.subst(iop)
6417639Sgblack@eecs.umich.edu    decoder_output += VMemSingleConstructor.subst(iop)
6427639Sgblack@eecs.umich.edu
6437639Sgblack@eecs.umich.edu    iop = InstObjParams("vstmult", "VstMult", 'VstMultOp', "", [])
6447639Sgblack@eecs.umich.edu    header_output += VMemMultDeclare.subst(iop)
6457639Sgblack@eecs.umich.edu    decoder_output += VMemMultConstructor.subst(iop)
6467639Sgblack@eecs.umich.edu
6477639Sgblack@eecs.umich.edu    iop = InstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", [])
6487639Sgblack@eecs.umich.edu    header_output += VMemSingleDeclare.subst(iop)
6497639Sgblack@eecs.umich.edu    decoder_output += VMemSingleConstructor.subst(iop)
6507639Sgblack@eecs.umich.edu
6517179Sgblack@eecs.umich.edu    vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", [])
6527179Sgblack@eecs.umich.edu    header_output += MacroVFPMemDeclare.subst(vfpIop)
6537179Sgblack@eecs.umich.edu    decoder_output += MacroVFPMemConstructor.subst(vfpIop)
6546019SN/A}};
655