macromem.isa revision 7134
15390SN/A// -*- mode:c++ -*- 25445SN/A 35390SN/A// Copyright (c) 2010 ARM Limited 45390SN/A// All rights reserved 55390SN/A// 65390SN/A// The license below extends only to copyright in the software and shall 75390SN/A// not be construed as granting a license to any other intellectual 85390SN/A// property including but not limited to intellectual property relating 95390SN/A// to a hardware implementation of the functionality of the software 105390SN/A// licensed hereunder. You may use the software subject to the license 115390SN/A// terms below provided that you ensure that this notice is replicated 125390SN/A// unmodified and in its entirety in all distributions of the software, 135390SN/A// modified or unmodified, in source code or in binary form. 145390SN/A// 155390SN/A// Copyright (c) 2007-2008 The Florida State University 165390SN/A// All rights reserved. 175390SN/A// 185390SN/A// Redistribution and use in source and binary forms, with or without 195390SN/A// modification, are permitted provided that the following conditions are 205390SN/A// met: redistributions of source code must retain the above copyright 215390SN/A// notice, this list of conditions and the following disclaimer; 225390SN/A// redistributions in binary form must reproduce the above copyright 235390SN/A// notice, this list of conditions and the following disclaimer in the 245390SN/A// documentation and/or other materials provided with the distribution; 255390SN/A// neither the name of the copyright holders nor the names of its 265390SN/A// contributors may be used to endorse or promote products derived from 275390SN/A// this software without specific prior written permission. 285390SN/A// 295390SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305390SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315636Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325636Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335390SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345636Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359338SAndreas.Sandberg@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365636Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375390SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385390SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395390SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405390SN/A// 415445SN/A// Authors: Stephen Hines 425445SN/A// Gabe Black 435636Sgblack@eecs.umich.edu 445390SN/A//////////////////////////////////////////////////////////////////// 455445SN/A// 465636Sgblack@eecs.umich.edu// Load/store microops 475636Sgblack@eecs.umich.edu// 485445SN/A 495445SN/Alet {{ 505445SN/A predicateTest = 'testPredicate(CondCodes, condCode)' 515445SN/A}}; 525445SN/A 535445SN/Alet {{ 545445SN/A microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 555445SN/A 'MicroMemOp', 565445SN/A {'memacc_code': 'Ra = Mem;', 575445SN/A 'ea_code': 'EA = Rb + (up ? imm : -imm);', 585390SN/A 'predicate_test': predicateTest}, 595636Sgblack@eecs.umich.edu ['IsMicroop']) 605390SN/A 615636Sgblack@eecs.umich.edu microLdrRetUopCode = ''' 625636Sgblack@eecs.umich.edu Ra = Mem; 635636Sgblack@eecs.umich.edu uint32_t newCpsr = 645636Sgblack@eecs.umich.edu cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true); 655636Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 665636Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 679808Sstever@gmail.com ''' 685826Sgblack@eecs.umich.edu microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 695636Sgblack@eecs.umich.edu 'MicroMemOp', 705636Sgblack@eecs.umich.edu {'memacc_code': microLdrRetUopCode, 715390SN/A 'ea_code': 7211175Sandreas.hansson@arm.com 'EA = Rb + (up ? imm : -imm);', 735390SN/A 'predicate_test': predicateTest}, 7411175Sandreas.hansson@arm.com ['IsMicroop']) 757903Shestness@cs.utexas.edu 7611168Sandreas.hansson@arm.com microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 7711168Sandreas.hansson@arm.com 'MicroMemOp', 785390SN/A {'memacc_code': 'Mem = Ra;', 795390SN/A 'ea_code': 'EA = Rb + (up ? imm : -imm);', 807811Ssteve.reinhardt@amd.com 'predicate_test': predicateTest}, 815390SN/A ['IsMicroop']) 825636Sgblack@eecs.umich.edu 83 header_output = MicroMemDeclare.subst(microLdrUopIop) + \ 84 MicroMemDeclare.subst(microLdrRetUopIop) + \ 85 MicroMemDeclare.subst(microStrUopIop) 86 decoder_output = MicroMemConstructor.subst(microLdrUopIop) + \ 87 MicroMemConstructor.subst(microLdrRetUopIop) + \ 88 MicroMemConstructor.subst(microStrUopIop) 89 exec_output = LoadExecute.subst(microLdrUopIop) + \ 90 LoadExecute.subst(microLdrRetUopIop) + \ 91 StoreExecute.subst(microStrUopIop) + \ 92 LoadInitiateAcc.subst(microLdrUopIop) + \ 93 LoadInitiateAcc.subst(microLdrRetUopIop) + \ 94 StoreInitiateAcc.subst(microStrUopIop) + \ 95 LoadCompleteAcc.subst(microLdrUopIop) + \ 96 LoadCompleteAcc.subst(microLdrRetUopIop) + \ 97 StoreCompleteAcc.subst(microStrUopIop) 98}}; 99 100//////////////////////////////////////////////////////////////////// 101// 102// Integer = Integer op Immediate microops 103// 104 105let {{ 106 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 107 'MicroIntOp', 108 {'code': 'Ra = Rb + imm;', 109 'predicate_test': predicateTest}, 110 ['IsMicroop']) 111 112 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 113 'MicroIntOp', 114 {'code': 'Ra = Rb - imm;', 115 'predicate_test': predicateTest}, 116 ['IsMicroop']) 117 118 header_output = MicroIntDeclare.subst(microAddiUopIop) + \ 119 MicroIntDeclare.subst(microSubiUopIop) 120 decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \ 121 MicroIntConstructor.subst(microSubiUopIop) 122 exec_output = PredOpExecute.subst(microAddiUopIop) + \ 123 PredOpExecute.subst(microSubiUopIop) 124}}; 125 126let {{ 127 iop = InstObjParams("ldmstm", "LdmStm", 'PredMacroOp', "", []) 128 header_output = MacroMemDeclare.subst(iop) 129 decoder_output = MacroMemConstructor.subst(iop) 130 exec_output = MacroMemExecute.subst(iop) 131}}; 132