macromem.isa revision 6308 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Stephen Hines
30//          Gabe Black
31
32
33////////////////////////////////////////////////////////////////////
34//
35// Integer = Integer op Immediate microops
36//
37
38def template MicroIntDeclare {{
39    class %(class_name)s : public %(base_class)s
40    {
41      public:
42        %(class_name)s(ExtMachInst machInst,
43                       RegIndex _ura, RegIndex _urb,
44                       uint8_t _imm);
45        %(BasicExecDeclare)s
46    };
47}};
48
49def template MicroIntConstructor {{
50    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
51                                          RegIndex _ura,
52                                          RegIndex _urb,
53                                          uint8_t _imm)
54        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
55                         _ura, _urb, _imm)
56    {
57        %(constructor)s;
58    }
59}};
60
61let {{
62    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
63                                    'MicroIntOp',
64                                    {'code': 'Ra = Rb + imm;',
65                                     'predicate_test': predicateTest},
66                                    ['IsMicroop'])
67
68    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
69                                    'MicroIntOp',
70                                    {'code': 'Ra = Rb - imm;',
71                                     'predicate_test': predicateTest},
72                                    ['IsMicroop'])
73
74    header_output = MicroIntDeclare.subst(microAddiUopIop) + \
75                    MicroIntDeclare.subst(microSubiUopIop)
76    decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
77                     MicroIntConstructor.subst(microSubiUopIop)
78    exec_output = PredOpExecute.subst(microAddiUopIop) + \
79                  PredOpExecute.subst(microSubiUopIop)
80}};
81
82////////////////////////////////////////////////////////////////////
83//
84// Macro Memory-format instructions
85//
86
87def template MacroStoreDeclare {{
88/**
89 * Static instructions class for a store multiple instruction
90 */
91class %(class_name)s : public %(base_class)s
92{
93    public:
94        // Constructor
95        %(class_name)s(ExtMachInst machInst);
96        %(BasicExecDeclare)s
97};
98}};
99
100def template MacroStoreConstructor {{
101inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
102    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
103{
104    %(constructor)s;
105    uint32_t regs_to_handle = reglist;
106    uint32_t start_addr = 0;
107
108    switch (puswl)
109    {
110        case 0x00: //       stmda
111        case 0x01: //     L ldmda_l
112        case 0x02: //    W  stmda_w
113        case 0x03: //    WL ldmda_wl
114            start_addr = (ones << 2) - 4;
115            break;
116        case 0x08: //  U    stmia_u
117        case 0x09: //  U  L ldmia_ul
118        case 0x0a: //  U W  stmia
119        case 0x0b: //  U WL ldmia
120            start_addr = 0;
121            break;
122        case 0x10: // P     stmdb
123        case 0x11: // P   L ldmdb
124        case 0x12: // P  W  stmdb
125        case 0x13: // P  WL ldmdb
126            start_addr = (ones << 2); // U-bit is already 0 for subtract
127            break;
128        case 0x18: // PU    stmib
129        case 0x19: // PU  L ldmib
130        case 0x1a: // PU W  stmib
131        case 0x1b: // PU WL ldmib
132            start_addr = 4;
133            break;
134        default:
135            panic("Unhandled Load/Store Multiple Instruction, "
136                "puswl = 0x%x", (unsigned) puswl);
137            break;
138    }
139
140    // Add 0 to Rn and stick it in Raddr (register 17).
141    // This is equivalent to a move.
142    microOps[0] = new MicroAddiUop(machInst, 17, RN, 0);
143
144    unsigned j = 0;
145    for (int i = 1; i < ones+1; i++) {
146        // Get next available bit for transfer
147        while (! ( regs_to_handle & (1<<j)))
148            j++;
149        regs_to_handle &= ~(1<<j);
150
151        microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr);
152
153        if (up)
154            start_addr += 4;
155        else
156            start_addr -= 4;
157    }
158
159    if (writeback) {
160        if (up) {
161            microOps[numMicroops-1] =
162                new MicroAddiUop(machInst, RN, RN, ones * 4);
163        } else {
164            microOps[numMicroops-1] =
165                new MicroSubiUop(machInst, RN, RN, ones * 4);
166        }
167    }
168    microOps[numMicroops-1]->setLastMicroop();
169}
170
171}};
172
173def template MacroStoreExecute {{
174Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
175{
176    Fault fault = NoFault;
177
178    %(fp_enable_check)s;
179    %(op_decl)s;
180    %(op_rd)s;
181    %(code)s;
182    if (fault == NoFault)
183    {
184        %(op_wb)s;
185    }
186
187    return fault;
188}
189}};
190
191def template MacroFPAConstructor {{
192inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
193    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
194{
195    %(constructor)s;
196
197    uint32_t start_addr = 0;
198
199    if (prepost)
200        start_addr = disp8;
201    else
202        start_addr = 0;
203
204    emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr);
205
206    if (writeback)
207    {
208        if (up) {
209            microOps[numMicroops-1] =
210                new MicroAddiUop(machInst, RN, RN, disp8);
211        } else {
212            microOps[numMicroops-1] =
213                new MicroSubiUop(machInst, RN, RN, disp8);
214        }
215    }
216    microOps[numMicroops-1]->setLastMicroop();
217}
218
219}};
220
221
222def template MacroFMConstructor {{
223inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
224    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
225{
226    %(constructor)s;
227
228    uint32_t start_addr = 0;
229
230    if (prepost)
231        start_addr = disp8;
232    else
233        start_addr = 0;
234
235    for (int i = 0; i < count; i++)
236        emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr);
237
238    if (writeback) {
239        if (up) {
240            microOps[numMicroops-1] =
241                new MicroAddiUop(machInst, RN, RN, disp8);
242        } else {
243            microOps[numMicroops-1] =
244                new MicroSubiUop(machInst, RN, RN, disp8);
245        }
246    }
247    microOps[numMicroops-1]->setLastMicroop();
248}
249}};
250
251
252def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
253    iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)
254    header_output = MacroStoreDeclare.subst(iop)
255    decoder_output = MacroStoreConstructor.subst(iop)
256    decode_block = BasicDecode.subst(iop)
257    exec_output = MacroStoreExecute.subst(iop)
258}};
259
260def format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{
261    iop = InstObjParams(name, Name, 'ArmMacroFPAOp',
262                        {"code": code,
263                         "predicate_test": predicateTest},
264                        opt_flags)
265    header_output = BasicDeclare.subst(iop)
266    decoder_output = MacroFPAConstructor.subst(iop)
267    decode_block = BasicDecode.subst(iop)
268    exec_output = PredOpExecute.subst(iop)
269}};
270
271def format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{
272    iop = InstObjParams(name, Name, 'ArmMacroFMOp',
273                        {"code": code,
274                         "predicate_test": predicateTest},
275                        opt_flags)
276    header_output = BasicDeclare.subst(iop)
277    decoder_output = MacroFMConstructor.subst(iop)
278    decode_block = BasicDecode.subst(iop)
279    exec_output = PredOpExecute.subst(iop)
280}};
281