macromem.isa revision 13544
16019SN/A// -*- mode:c++ -*-
26019SN/A
310346Smitch.hayenga@arm.com// Copyright (c) 2010-2014 ARM Limited
47134Sgblack@eecs.umich.edu// All rights reserved
57134Sgblack@eecs.umich.edu//
67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
107134Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
147134Sgblack@eecs.umich.edu//
156019SN/A// Copyright (c) 2007-2008 The Florida State University
166019SN/A// All rights reserved.
176019SN/A//
186019SN/A// Redistribution and use in source and binary forms, with or without
196019SN/A// modification, are permitted provided that the following conditions are
206019SN/A// met: redistributions of source code must retain the above copyright
216019SN/A// notice, this list of conditions and the following disclaimer;
226019SN/A// redistributions in binary form must reproduce the above copyright
236019SN/A// notice, this list of conditions and the following disclaimer in the
246019SN/A// documentation and/or other materials provided with the distribution;
256019SN/A// neither the name of the copyright holders nor the names of its
266019SN/A// contributors may be used to endorse or promote products derived from
276019SN/A// this software without specific prior written permission.
286019SN/A//
296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406019SN/A//
416019SN/A// Authors: Stephen Hines
426308SN/A//          Gabe Black
436308SN/A
446309SN/A////////////////////////////////////////////////////////////////////
456309SN/A//
466309SN/A// Load/store microops
476309SN/A//
486309SN/A
497134Sgblack@eecs.umich.edulet {{
508588Sgblack@eecs.umich.edu    microLdrUopCode = "IWRa = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
516309SN/A    microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
526309SN/A                                   'MicroMemOp',
537296Sgblack@eecs.umich.edu                                   {'memacc_code': microLdrUopCode,
548139SMatt.Horsnell@arm.com                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
556309SN/A                                    'predicate_test': predicateTest},
566309SN/A                                   ['IsMicroop'])
576309SN/A
5810346Smitch.hayenga@arm.com    microLdr2UopCode = '''
5910346Smitch.hayenga@arm.com                        uint64_t data = Mem_ud;
6010346Smitch.hayenga@arm.com                        Dest = cSwap((uint32_t) data, ((CPSR)Cpsr).e);
6112134Sgedare@rtems.org                        IWDest2 = cSwap((uint32_t) (data >> 32),
6212134Sgedare@rtems.org                                        ((CPSR)Cpsr).e);
6310346Smitch.hayenga@arm.com                        '''
6410346Smitch.hayenga@arm.com    microLdr2UopIop = InstObjParams('ldr2_uop', 'MicroLdr2Uop',
6510346Smitch.hayenga@arm.com                                   'MicroMemPairOp',
6610346Smitch.hayenga@arm.com                                   {'memacc_code': microLdr2UopCode,
6710346Smitch.hayenga@arm.com                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
6810346Smitch.hayenga@arm.com                                    'predicate_test': predicateTest},
6910346Smitch.hayenga@arm.com                                   ['IsMicroop'])
7010346Smitch.hayenga@arm.com
718588Sgblack@eecs.umich.edu    microLdrFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
727174Sgblack@eecs.umich.edu    microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
737639Sgblack@eecs.umich.edu                                      'MicroMemOp',
747639Sgblack@eecs.umich.edu                                      {'memacc_code': microLdrFpUopCode,
757644Sali.saidi@arm.com                                       'ea_code': vfpEnabledCheckCode +
768139SMatt.Horsnell@arm.com                                           'EA = URb + (up ? imm : -imm);',
777639Sgblack@eecs.umich.edu                                       'predicate_test': predicateTest},
787639Sgblack@eecs.umich.edu                                      ['IsMicroop'])
797639Sgblack@eecs.umich.edu
808588Sgblack@eecs.umich.edu    microLdrDBFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
817639Sgblack@eecs.umich.edu    microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
827639Sgblack@eecs.umich.edu                                      'MicroMemOp',
837639Sgblack@eecs.umich.edu                                      {'memacc_code': microLdrFpUopCode,
847644Sali.saidi@arm.com                                       'ea_code': vfpEnabledCheckCode + '''
858139SMatt.Horsnell@arm.com                                        EA = URb + (up ? imm : -imm) +
867639Sgblack@eecs.umich.edu                                             (((CPSR)Cpsr).e ? 4 : 0);
877639Sgblack@eecs.umich.edu                                        ''',
887639Sgblack@eecs.umich.edu                                       'predicate_test': predicateTest},
897639Sgblack@eecs.umich.edu                                      ['IsMicroop'])
907639Sgblack@eecs.umich.edu
918588Sgblack@eecs.umich.edu    microLdrDTFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
927639Sgblack@eecs.umich.edu    microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
937639Sgblack@eecs.umich.edu                                      'MicroMemOp',
947639Sgblack@eecs.umich.edu                                      {'memacc_code': microLdrFpUopCode,
957644Sali.saidi@arm.com                                       'ea_code': vfpEnabledCheckCode + '''
968139SMatt.Horsnell@arm.com                                        EA = URb + (up ? imm : -imm) -
977639Sgblack@eecs.umich.edu                                             (((CPSR)Cpsr).e ? 4 : 0);
987639Sgblack@eecs.umich.edu                                        ''',
997639Sgblack@eecs.umich.edu                                       'predicate_test': predicateTest},
1007639Sgblack@eecs.umich.edu                                      ['IsMicroop'])
1017174Sgblack@eecs.umich.edu
1028148SAli.Saidi@ARM.com    microRetUopCode = '''
1038303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
1047400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
1058303SAli.Saidi@ARM.com
1068303SAli.Saidi@ARM.com        CPSR new_cpsr =
10710037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF, true,
10810037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
1098303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
1108303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
1118303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
1128303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
1138303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
1148303SAli.Saidi@ARM.com        IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
1158205SAli.Saidi@ARM.com        NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
1167858SMatt.Horsnell@arm.com                | (((CPSR)Spsr).it1 & 0x3);
1178285SPrakash.Ramrakhyani@arm.com        SevMailbox = 1;
1186754SN/A    '''
1198148SAli.Saidi@ARM.com
1206754SN/A    microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
1216754SN/A                                      'MicroMemOp',
1228148SAli.Saidi@ARM.com                                      {'memacc_code':
1238588Sgblack@eecs.umich.edu                                          microRetUopCode % 'Mem_uw',
1246754SN/A                                       'ea_code':
1258139SMatt.Horsnell@arm.com                                          'EA = URb + (up ? imm : -imm);',
1267422Sgblack@eecs.umich.edu                                       'predicate_test': condPredicateTest},
1278148SAli.Saidi@ARM.com                                      ['IsMicroop','IsNonSpeculative',
12811355Smitch.hayenga@arm.com                                       'IsSerializeAfter', 'IsSquashAfter'])
1296754SN/A
1308588Sgblack@eecs.umich.edu    microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);"
1316309SN/A    microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
1326309SN/A                                   'MicroMemOp',
1337296Sgblack@eecs.umich.edu                                   {'memacc_code': microStrUopCode,
1347303Sgblack@eecs.umich.edu                                    'postacc_code': "",
1358139SMatt.Horsnell@arm.com                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
1366309SN/A                                    'predicate_test': predicateTest},
1376309SN/A                                   ['IsMicroop'])
1386309SN/A
1398588Sgblack@eecs.umich.edu    microStrFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
1407174Sgblack@eecs.umich.edu    microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
1417174Sgblack@eecs.umich.edu                                     'MicroMemOp',
1427296Sgblack@eecs.umich.edu                                     {'memacc_code': microStrFpUopCode,
1437303Sgblack@eecs.umich.edu                                      'postacc_code': "",
1447644Sali.saidi@arm.com                                      'ea_code': vfpEnabledCheckCode +
1458139SMatt.Horsnell@arm.com                                           'EA = URb + (up ? imm : -imm);',
1467174Sgblack@eecs.umich.edu                                      'predicate_test': predicateTest},
1477174Sgblack@eecs.umich.edu                                     ['IsMicroop'])
1487174Sgblack@eecs.umich.edu
1498588Sgblack@eecs.umich.edu    microStrDBFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
1507639Sgblack@eecs.umich.edu    microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop',
1517639Sgblack@eecs.umich.edu                                       'MicroMemOp',
1527639Sgblack@eecs.umich.edu                                       {'memacc_code': microStrFpUopCode,
1537639Sgblack@eecs.umich.edu                                        'postacc_code': "",
1547644Sali.saidi@arm.com                                        'ea_code': vfpEnabledCheckCode + '''
1558139SMatt.Horsnell@arm.com                                         EA = URb + (up ? imm : -imm) +
1567639Sgblack@eecs.umich.edu                                              (((CPSR)Cpsr).e ? 4 : 0);
1577639Sgblack@eecs.umich.edu                                         ''',
1587639Sgblack@eecs.umich.edu                                        'predicate_test': predicateTest},
1597639Sgblack@eecs.umich.edu                                       ['IsMicroop'])
1607639Sgblack@eecs.umich.edu
1618588Sgblack@eecs.umich.edu    microStrDTFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
1627639Sgblack@eecs.umich.edu    microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop',
1637639Sgblack@eecs.umich.edu                                       'MicroMemOp',
1647639Sgblack@eecs.umich.edu                                       {'memacc_code': microStrFpUopCode,
1657639Sgblack@eecs.umich.edu                                        'postacc_code': "",
1667644Sali.saidi@arm.com                                        'ea_code': vfpEnabledCheckCode + '''
1678139SMatt.Horsnell@arm.com                                         EA = URb + (up ? imm : -imm) -
1687639Sgblack@eecs.umich.edu                                              (((CPSR)Cpsr).e ? 4 : 0);
1697639Sgblack@eecs.umich.edu                                         ''',
1707639Sgblack@eecs.umich.edu                                        'predicate_test': predicateTest},
1717639Sgblack@eecs.umich.edu                                       ['IsMicroop'])
1727639Sgblack@eecs.umich.edu
1737174Sgblack@eecs.umich.edu    header_output = decoder_output = exec_output = ''
1747174Sgblack@eecs.umich.edu
17510346Smitch.hayenga@arm.com    loadIops = (microLdrUopIop, microLdrRetUopIop,
17610346Smitch.hayenga@arm.com                microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop)
1777639Sgblack@eecs.umich.edu    storeIops = (microStrUopIop, microStrFpUopIop,
1787639Sgblack@eecs.umich.edu                 microStrDBFpUopIop, microStrDTFpUopIop)
1797174Sgblack@eecs.umich.edu    for iop in loadIops + storeIops:
1807174Sgblack@eecs.umich.edu        header_output += MicroMemDeclare.subst(iop)
1817174Sgblack@eecs.umich.edu        decoder_output += MicroMemConstructor.subst(iop)
1827174Sgblack@eecs.umich.edu    for iop in loadIops:
1837174Sgblack@eecs.umich.edu        exec_output += LoadExecute.subst(iop) + \
1847174Sgblack@eecs.umich.edu                       LoadInitiateAcc.subst(iop) + \
1857174Sgblack@eecs.umich.edu                       LoadCompleteAcc.subst(iop)
1867174Sgblack@eecs.umich.edu    for iop in storeIops:
1877174Sgblack@eecs.umich.edu        exec_output += StoreExecute.subst(iop) + \
1887174Sgblack@eecs.umich.edu                       StoreInitiateAcc.subst(iop) + \
1897174Sgblack@eecs.umich.edu                       StoreCompleteAcc.subst(iop)
19010346Smitch.hayenga@arm.com
19110346Smitch.hayenga@arm.com    header_output += MicroMemPairDeclare.subst(microLdr2UopIop)
19210346Smitch.hayenga@arm.com    decoder_output += MicroMemPairConstructor.subst(microLdr2UopIop)
19310346Smitch.hayenga@arm.com    exec_output += LoadExecute.subst(microLdr2UopIop) + \
19410346Smitch.hayenga@arm.com                   LoadInitiateAcc.subst(microLdr2UopIop) + \
19510346Smitch.hayenga@arm.com                   LoadCompleteAcc.subst(microLdr2UopIop)
1966309SN/A}};
1976308SN/A
1987639Sgblack@eecs.umich.edulet {{
1997639Sgblack@eecs.umich.edu    exec_output = header_output = ''
2007639Sgblack@eecs.umich.edu
20110037SARM gem5 Developers    eaCode = 'EA = XURa + imm;'
2027639Sgblack@eecs.umich.edu
2037639Sgblack@eecs.umich.edu    for size in (1, 2, 3, 4, 6, 8, 12, 16):
2047639Sgblack@eecs.umich.edu        # Set up the memory access.
2057639Sgblack@eecs.umich.edu        regs = (size + 3) // 4
2067639Sgblack@eecs.umich.edu        subst = { "size" : size, "regs" : regs }
2077639Sgblack@eecs.umich.edu        memDecl = '''
2087639Sgblack@eecs.umich.edu        union MemUnion {
2097639Sgblack@eecs.umich.edu            uint8_t bytes[%(size)d];
2107639Sgblack@eecs.umich.edu            Element elements[%(size)d / sizeof(Element)];
2117639Sgblack@eecs.umich.edu            uint32_t floatRegBits[%(regs)d];
2127639Sgblack@eecs.umich.edu        };
2137639Sgblack@eecs.umich.edu        ''' % subst
2147639Sgblack@eecs.umich.edu
2157639Sgblack@eecs.umich.edu        # Do endian conversion for all the elements.
2167639Sgblack@eecs.umich.edu        convCode = '''
2177639Sgblack@eecs.umich.edu            const unsigned eCount = sizeof(memUnion.elements) /
2187639Sgblack@eecs.umich.edu                                    sizeof(memUnion.elements[0]);
2197639Sgblack@eecs.umich.edu            if (((CPSR)Cpsr).e) {
2207639Sgblack@eecs.umich.edu                for (unsigned i = 0; i < eCount; i++) {
2217639Sgblack@eecs.umich.edu                    memUnion.elements[i] = gtobe(memUnion.elements[i]);
2227639Sgblack@eecs.umich.edu                }
2237639Sgblack@eecs.umich.edu            } else {
2247639Sgblack@eecs.umich.edu                for (unsigned i = 0; i < eCount; i++) {
2257639Sgblack@eecs.umich.edu                    memUnion.elements[i] = gtole(memUnion.elements[i]);
2267639Sgblack@eecs.umich.edu                }
2277639Sgblack@eecs.umich.edu            }
2287639Sgblack@eecs.umich.edu        '''
2297639Sgblack@eecs.umich.edu
2307639Sgblack@eecs.umich.edu        # Offload everything into registers
2317639Sgblack@eecs.umich.edu        regSetCode = ''
2327639Sgblack@eecs.umich.edu        for reg in range(regs):
2337639Sgblack@eecs.umich.edu            mask = ''
2347639Sgblack@eecs.umich.edu            if reg == regs - 1:
2357639Sgblack@eecs.umich.edu                mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size))
2367639Sgblack@eecs.umich.edu            regSetCode += '''
2378588Sgblack@eecs.umich.edu            FpDestP%(reg)d_uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s;
2387639Sgblack@eecs.umich.edu            ''' % { "reg" : reg, "mask" : mask }
2397639Sgblack@eecs.umich.edu
2407639Sgblack@eecs.umich.edu        # Pull everything in from registers
2417639Sgblack@eecs.umich.edu        regGetCode = ''
2427639Sgblack@eecs.umich.edu        for reg in range(regs):
2437639Sgblack@eecs.umich.edu            regGetCode += '''
2448588Sgblack@eecs.umich.edu            memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d_uw);
2457639Sgblack@eecs.umich.edu            ''' % { "reg" : reg }
2467639Sgblack@eecs.umich.edu
2477639Sgblack@eecs.umich.edu        loadMemAccCode = convCode + regSetCode
2487639Sgblack@eecs.umich.edu        storeMemAccCode = regGetCode + convCode
2497639Sgblack@eecs.umich.edu
2507639Sgblack@eecs.umich.edu        loadIop = InstObjParams('ldrneon%(size)d_uop' % subst,
2517639Sgblack@eecs.umich.edu                                'MicroLdrNeon%(size)dUop' % subst,
2527639Sgblack@eecs.umich.edu                                'MicroNeonMemOp',
2537639Sgblack@eecs.umich.edu                                { 'mem_decl' : memDecl,
2547639Sgblack@eecs.umich.edu                                  'size' : size,
2557639Sgblack@eecs.umich.edu                                  'memacc_code' : loadMemAccCode,
2567644Sali.saidi@arm.com                                  'ea_code' : simdEnabledCheckCode + eaCode,
2577639Sgblack@eecs.umich.edu                                  'predicate_test' : predicateTest },
2587639Sgblack@eecs.umich.edu                                [ 'IsMicroop', 'IsMemRef', 'IsLoad' ])
2597639Sgblack@eecs.umich.edu        storeIop = InstObjParams('strneon%(size)d_uop' % subst,
2607639Sgblack@eecs.umich.edu                                 'MicroStrNeon%(size)dUop' % subst,
2617639Sgblack@eecs.umich.edu                                 'MicroNeonMemOp',
2627639Sgblack@eecs.umich.edu                                 { 'mem_decl' : memDecl,
2637639Sgblack@eecs.umich.edu                                   'size' : size,
2647639Sgblack@eecs.umich.edu                                   'memacc_code' : storeMemAccCode,
2657644Sali.saidi@arm.com                                   'ea_code' : simdEnabledCheckCode + eaCode,
2667639Sgblack@eecs.umich.edu                                   'predicate_test' : predicateTest },
2677639Sgblack@eecs.umich.edu                                 [ 'IsMicroop', 'IsMemRef', 'IsStore' ])
2687639Sgblack@eecs.umich.edu
2697639Sgblack@eecs.umich.edu        exec_output += NeonLoadExecute.subst(loadIop) + \
2707639Sgblack@eecs.umich.edu                       NeonLoadInitiateAcc.subst(loadIop) + \
2717639Sgblack@eecs.umich.edu                       NeonLoadCompleteAcc.subst(loadIop) + \
2727639Sgblack@eecs.umich.edu                       NeonStoreExecute.subst(storeIop) + \
2737639Sgblack@eecs.umich.edu                       NeonStoreInitiateAcc.subst(storeIop) + \
2747639Sgblack@eecs.umich.edu                       NeonStoreCompleteAcc.subst(storeIop)
2757639Sgblack@eecs.umich.edu        header_output += MicroNeonMemDeclare.subst(loadIop) + \
2767639Sgblack@eecs.umich.edu                         MicroNeonMemDeclare.subst(storeIop)
2777639Sgblack@eecs.umich.edu}};
2787639Sgblack@eecs.umich.edu
2797639Sgblack@eecs.umich.edulet {{
2807639Sgblack@eecs.umich.edu    exec_output = ''
2817639Sgblack@eecs.umich.edu    for eSize, type in (1, 'uint8_t'), \
2827639Sgblack@eecs.umich.edu                       (2, 'uint16_t'), \
2837639Sgblack@eecs.umich.edu                       (4, 'uint32_t'), \
2847639Sgblack@eecs.umich.edu                       (8, 'uint64_t'):
2857639Sgblack@eecs.umich.edu        size = eSize
2867639Sgblack@eecs.umich.edu        # An instruction handles no more than 16 bytes and no more than
2877639Sgblack@eecs.umich.edu        # 4 elements, or the number of elements needed to fill 8 or 16 bytes.
2887639Sgblack@eecs.umich.edu        sizes = set((16, 8))
2897639Sgblack@eecs.umich.edu        for count in 1, 2, 3, 4:
2907639Sgblack@eecs.umich.edu            size = count * eSize
2917639Sgblack@eecs.umich.edu            if size <= 16:
2927639Sgblack@eecs.umich.edu                sizes.add(size)
2937639Sgblack@eecs.umich.edu        for size in sizes:
2947639Sgblack@eecs.umich.edu            substDict = {
2957639Sgblack@eecs.umich.edu                "class_name" : "MicroLdrNeon%dUop" % size,
2967639Sgblack@eecs.umich.edu                "targs" : type
2977639Sgblack@eecs.umich.edu            }
2987639Sgblack@eecs.umich.edu            exec_output += MicroNeonMemExecDeclare.subst(substDict)
2997639Sgblack@eecs.umich.edu            substDict["class_name"] = "MicroStrNeon%dUop" % size
3007639Sgblack@eecs.umich.edu            exec_output += MicroNeonMemExecDeclare.subst(substDict)
3017639Sgblack@eecs.umich.edu            size += eSize
3027639Sgblack@eecs.umich.edu}};
3037639Sgblack@eecs.umich.edu
3047639Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////
3057639Sgblack@eecs.umich.edu//
3067639Sgblack@eecs.umich.edu// Neon (de)interlacing microops
3077639Sgblack@eecs.umich.edu//
3087639Sgblack@eecs.umich.edu
3097639Sgblack@eecs.umich.edulet {{
3107639Sgblack@eecs.umich.edu    header_output = exec_output = ''
3117639Sgblack@eecs.umich.edu    for dRegs in (2, 3, 4):
3127639Sgblack@eecs.umich.edu        loadConv = ''
3137639Sgblack@eecs.umich.edu        unloadConv = ''
3147639Sgblack@eecs.umich.edu        for dReg in range(dRegs):
3157639Sgblack@eecs.umich.edu            loadConv += '''
3168588Sgblack@eecs.umich.edu                conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d_uw);
3178588Sgblack@eecs.umich.edu                conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d_uw);
3187639Sgblack@eecs.umich.edu            ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
3197639Sgblack@eecs.umich.edu            unloadConv += '''
3208588Sgblack@eecs.umich.edu                FpDestS%(dReg)dP0_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]);
3218588Sgblack@eecs.umich.edu                FpDestS%(dReg)dP1_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]);
3227639Sgblack@eecs.umich.edu            ''' % { "dReg" : dReg }
3237639Sgblack@eecs.umich.edu        microDeintNeonCode = '''
3247639Sgblack@eecs.umich.edu            const unsigned dRegs = %(dRegs)d;
3257639Sgblack@eecs.umich.edu            const unsigned regs = 2 * dRegs;
32613544Sgabeblack@google.com            const unsigned perDReg =
32713544Sgabeblack@google.com                (2 * sizeof(uint32_t)) / sizeof(Element);
3287639Sgblack@eecs.umich.edu            union convStruct {
32913544Sgabeblack@google.com                uint32_t cRegs[regs];
3307639Sgblack@eecs.umich.edu                Element elements[dRegs * perDReg];
3317639Sgblack@eecs.umich.edu            } conv1, conv2;
3327639Sgblack@eecs.umich.edu
3337639Sgblack@eecs.umich.edu            %(loadConv)s
3347639Sgblack@eecs.umich.edu
3357639Sgblack@eecs.umich.edu            unsigned srcElem = 0;
3367639Sgblack@eecs.umich.edu            for (unsigned destOffset = 0;
3377639Sgblack@eecs.umich.edu                    destOffset < perDReg; destOffset++) {
3387639Sgblack@eecs.umich.edu                for (unsigned dReg = 0; dReg < dRegs; dReg++) {
3397639Sgblack@eecs.umich.edu                    conv2.elements[dReg * perDReg + destOffset] =
3407639Sgblack@eecs.umich.edu                        conv1.elements[srcElem++];
3417639Sgblack@eecs.umich.edu                }
3427639Sgblack@eecs.umich.edu            }
3437639Sgblack@eecs.umich.edu
3447639Sgblack@eecs.umich.edu            %(unloadConv)s
3457639Sgblack@eecs.umich.edu        ''' % { "dRegs" : dRegs,
3467639Sgblack@eecs.umich.edu                "loadConv" : loadConv,
3477639Sgblack@eecs.umich.edu                "unloadConv" : unloadConv }
3487639Sgblack@eecs.umich.edu        microDeintNeonIop = \
3497639Sgblack@eecs.umich.edu            InstObjParams('deintneon%duop' % (dRegs * 2),
3507639Sgblack@eecs.umich.edu                          'MicroDeintNeon%dUop' % (dRegs * 2),
3517639Sgblack@eecs.umich.edu                          'MicroNeonMixOp',
3527639Sgblack@eecs.umich.edu                          { 'predicate_test': predicateTest,
3537639Sgblack@eecs.umich.edu                            'code' : microDeintNeonCode },
3547639Sgblack@eecs.umich.edu                            ['IsMicroop'])
3557639Sgblack@eecs.umich.edu        header_output += MicroNeonMixDeclare.subst(microDeintNeonIop)
3567639Sgblack@eecs.umich.edu        exec_output += MicroNeonMixExecute.subst(microDeintNeonIop)
3577639Sgblack@eecs.umich.edu
3587639Sgblack@eecs.umich.edu        loadConv = ''
3597639Sgblack@eecs.umich.edu        unloadConv = ''
3607639Sgblack@eecs.umich.edu        for dReg in range(dRegs):
3617639Sgblack@eecs.umich.edu            loadConv += '''
3628588Sgblack@eecs.umich.edu                conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0_uw);
3638588Sgblack@eecs.umich.edu                conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1_uw);
3647639Sgblack@eecs.umich.edu            ''' % { "dReg" : dReg }
3657639Sgblack@eecs.umich.edu            unloadConv += '''
3668588Sgblack@eecs.umich.edu                FpDestP%(sReg0)d_uw = gtoh(conv2.cRegs[%(sReg0)d]);
3678588Sgblack@eecs.umich.edu                FpDestP%(sReg1)d_uw = gtoh(conv2.cRegs[%(sReg1)d]);
3687639Sgblack@eecs.umich.edu            ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
3697639Sgblack@eecs.umich.edu        microInterNeonCode = '''
3707639Sgblack@eecs.umich.edu            const unsigned dRegs = %(dRegs)d;
3717639Sgblack@eecs.umich.edu            const unsigned regs = 2 * dRegs;
37213544Sgabeblack@google.com            const unsigned perDReg =
37313544Sgabeblack@google.com                (2 * sizeof(uint32_t)) / sizeof(Element);
3747639Sgblack@eecs.umich.edu            union convStruct {
37513544Sgabeblack@google.com                uint32_t cRegs[regs];
3767639Sgblack@eecs.umich.edu                Element elements[dRegs * perDReg];
3777639Sgblack@eecs.umich.edu            } conv1, conv2;
3787639Sgblack@eecs.umich.edu
3797639Sgblack@eecs.umich.edu            %(loadConv)s
3807639Sgblack@eecs.umich.edu
3817639Sgblack@eecs.umich.edu            unsigned destElem = 0;
3827639Sgblack@eecs.umich.edu            for (unsigned srcOffset = 0;
3837639Sgblack@eecs.umich.edu                    srcOffset < perDReg; srcOffset++) {
3847639Sgblack@eecs.umich.edu                for (unsigned dReg = 0; dReg < dRegs; dReg++) {
3857639Sgblack@eecs.umich.edu                    conv2.elements[destElem++] =
3867639Sgblack@eecs.umich.edu                        conv1.elements[dReg * perDReg + srcOffset];
3877639Sgblack@eecs.umich.edu                }
3887639Sgblack@eecs.umich.edu            }
3897639Sgblack@eecs.umich.edu
3907639Sgblack@eecs.umich.edu            %(unloadConv)s
3917639Sgblack@eecs.umich.edu        ''' % { "dRegs" : dRegs,
3927639Sgblack@eecs.umich.edu                "loadConv" : loadConv,
3937639Sgblack@eecs.umich.edu                "unloadConv" : unloadConv }
3947639Sgblack@eecs.umich.edu        microInterNeonIop = \
3957639Sgblack@eecs.umich.edu            InstObjParams('interneon%duop' % (dRegs * 2),
3967639Sgblack@eecs.umich.edu                          'MicroInterNeon%dUop' % (dRegs * 2),
3977639Sgblack@eecs.umich.edu                          'MicroNeonMixOp',
3987639Sgblack@eecs.umich.edu                          { 'predicate_test': predicateTest,
3997639Sgblack@eecs.umich.edu                            'code' : microInterNeonCode },
4007639Sgblack@eecs.umich.edu                            ['IsMicroop'])
4017639Sgblack@eecs.umich.edu        header_output += MicroNeonMixDeclare.subst(microInterNeonIop)
4027639Sgblack@eecs.umich.edu        exec_output += MicroNeonMixExecute.subst(microInterNeonIop)
4037639Sgblack@eecs.umich.edu}};
4047639Sgblack@eecs.umich.edu
4057639Sgblack@eecs.umich.edulet {{
4067639Sgblack@eecs.umich.edu    exec_output = ''
4077639Sgblack@eecs.umich.edu    for type in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'):
4087639Sgblack@eecs.umich.edu        for dRegs in (2, 3, 4):
4097639Sgblack@eecs.umich.edu            Name = "MicroDeintNeon%dUop" % (dRegs * 2)
4107639Sgblack@eecs.umich.edu            substDict = { "class_name" : Name, "targs" : type }
4117639Sgblack@eecs.umich.edu            exec_output += MicroNeonExecDeclare.subst(substDict)
4127639Sgblack@eecs.umich.edu            Name = "MicroInterNeon%dUop" % (dRegs * 2)
4137639Sgblack@eecs.umich.edu            substDict = { "class_name" : Name, "targs" : type }
4147639Sgblack@eecs.umich.edu            exec_output += MicroNeonExecDeclare.subst(substDict)
4157639Sgblack@eecs.umich.edu}};
4167639Sgblack@eecs.umich.edu
4177639Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////
4187639Sgblack@eecs.umich.edu//
4197639Sgblack@eecs.umich.edu// Neon microops to pack/unpack a single lane
4207639Sgblack@eecs.umich.edu//
4217639Sgblack@eecs.umich.edu
4227639Sgblack@eecs.umich.edulet {{
4237639Sgblack@eecs.umich.edu    header_output = exec_output = ''
4247639Sgblack@eecs.umich.edu    for sRegs in 1, 2:
4257639Sgblack@eecs.umich.edu        baseLoadRegs = ''
4267639Sgblack@eecs.umich.edu        for reg in range(sRegs):
4277639Sgblack@eecs.umich.edu            baseLoadRegs += '''
4288588Sgblack@eecs.umich.edu                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw);
4298588Sgblack@eecs.umich.edu                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw);
4307639Sgblack@eecs.umich.edu            ''' % { "reg0" : (2 * reg + 0),
4317639Sgblack@eecs.umich.edu                    "reg1" : (2 * reg + 1) }
4327639Sgblack@eecs.umich.edu        for dRegs in range(sRegs, 5):
4337639Sgblack@eecs.umich.edu            unloadRegs = ''
4347639Sgblack@eecs.umich.edu            loadRegs = baseLoadRegs
4357639Sgblack@eecs.umich.edu            for reg in range(dRegs):
4367639Sgblack@eecs.umich.edu                loadRegs += '''
4378588Sgblack@eecs.umich.edu                    destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0_uw);
4388588Sgblack@eecs.umich.edu                    destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1_uw);
4397639Sgblack@eecs.umich.edu                ''' % { "reg" : reg }
4407639Sgblack@eecs.umich.edu                unloadRegs += '''
4418588Sgblack@eecs.umich.edu                    FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]);
4428588Sgblack@eecs.umich.edu                    FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
4437639Sgblack@eecs.umich.edu                ''' % { "reg" : reg }
4447639Sgblack@eecs.umich.edu            microUnpackNeonCode = '''
44513544Sgabeblack@google.com            const unsigned perDReg = (2 * sizeof(uint32_t)) / sizeof(Element);
4467639Sgblack@eecs.umich.edu
4477639Sgblack@eecs.umich.edu            union SourceRegs {
44813544Sgabeblack@google.com                uint32_t fRegs[2 * %(sRegs)d];
4497639Sgblack@eecs.umich.edu                Element elements[%(sRegs)d * perDReg];
4507639Sgblack@eecs.umich.edu            } sourceRegs;
4517639Sgblack@eecs.umich.edu
4527639Sgblack@eecs.umich.edu            union DestReg {
45313544Sgabeblack@google.com                uint32_t fRegs[2];
4547639Sgblack@eecs.umich.edu                Element elements[perDReg];
4557639Sgblack@eecs.umich.edu            } destRegs[%(dRegs)d];
4567639Sgblack@eecs.umich.edu
4577639Sgblack@eecs.umich.edu            %(loadRegs)s
4587639Sgblack@eecs.umich.edu
4597639Sgblack@eecs.umich.edu            for (unsigned i = 0; i < %(dRegs)d; i++) {
4607639Sgblack@eecs.umich.edu                destRegs[i].elements[lane] = sourceRegs.elements[i];
4617639Sgblack@eecs.umich.edu            }
4627639Sgblack@eecs.umich.edu
4637639Sgblack@eecs.umich.edu            %(unloadRegs)s
4647639Sgblack@eecs.umich.edu            ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
4657639Sgblack@eecs.umich.edu                    "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
4667639Sgblack@eecs.umich.edu
4677639Sgblack@eecs.umich.edu            microUnpackNeonIop = \
4687639Sgblack@eecs.umich.edu                InstObjParams('unpackneon%dto%duop' % (sRegs * 2, dRegs * 2),
4697639Sgblack@eecs.umich.edu                              'MicroUnpackNeon%dto%dUop' %
4707639Sgblack@eecs.umich.edu                                    (sRegs * 2, dRegs * 2),
4717639Sgblack@eecs.umich.edu                              'MicroNeonMixLaneOp',
4727639Sgblack@eecs.umich.edu                              { 'predicate_test': predicateTest,
4737639Sgblack@eecs.umich.edu                                'code' : microUnpackNeonCode },
4747639Sgblack@eecs.umich.edu                                ['IsMicroop'])
4757639Sgblack@eecs.umich.edu            header_output += MicroNeonMixLaneDeclare.subst(microUnpackNeonIop)
4767639Sgblack@eecs.umich.edu            exec_output += MicroNeonMixExecute.subst(microUnpackNeonIop)
4777639Sgblack@eecs.umich.edu
4787639Sgblack@eecs.umich.edu    for sRegs in 1, 2:
4797639Sgblack@eecs.umich.edu        loadRegs = ''
4807639Sgblack@eecs.umich.edu        for reg in range(sRegs):
4817639Sgblack@eecs.umich.edu            loadRegs += '''
4828588Sgblack@eecs.umich.edu                sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw);
4838588Sgblack@eecs.umich.edu                sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw);
4847639Sgblack@eecs.umich.edu            ''' % { "reg0" : (2 * reg + 0),
4857639Sgblack@eecs.umich.edu                    "reg1" : (2 * reg + 1) }
4867639Sgblack@eecs.umich.edu        for dRegs in range(sRegs, 5):
4877639Sgblack@eecs.umich.edu            unloadRegs = ''
4887639Sgblack@eecs.umich.edu            for reg in range(dRegs):
4897639Sgblack@eecs.umich.edu                unloadRegs += '''
4908588Sgblack@eecs.umich.edu                    FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]);
4918588Sgblack@eecs.umich.edu                    FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
4927639Sgblack@eecs.umich.edu                ''' % { "reg" : reg }
4937639Sgblack@eecs.umich.edu            microUnpackAllNeonCode = '''
49413544Sgabeblack@google.com            const unsigned perDReg = (2 * sizeof(uint32_t)) / sizeof(Element);
4957639Sgblack@eecs.umich.edu
4967639Sgblack@eecs.umich.edu            union SourceRegs {
49713544Sgabeblack@google.com                uint32_t fRegs[2 * %(sRegs)d];
4987639Sgblack@eecs.umich.edu                Element elements[%(sRegs)d * perDReg];
4997639Sgblack@eecs.umich.edu            } sourceRegs;
5007639Sgblack@eecs.umich.edu
5017639Sgblack@eecs.umich.edu            union DestReg {
50213544Sgabeblack@google.com                uint32_t fRegs[2];
5037639Sgblack@eecs.umich.edu                Element elements[perDReg];
5047639Sgblack@eecs.umich.edu            } destRegs[%(dRegs)d];
5057639Sgblack@eecs.umich.edu
5067639Sgblack@eecs.umich.edu            %(loadRegs)s
5077639Sgblack@eecs.umich.edu
5087639Sgblack@eecs.umich.edu            for (unsigned i = 0; i < %(dRegs)d; i++) {
5097639Sgblack@eecs.umich.edu                for (unsigned j = 0; j < perDReg; j++)
5107639Sgblack@eecs.umich.edu                    destRegs[i].elements[j] = sourceRegs.elements[i];
5117639Sgblack@eecs.umich.edu            }
5127639Sgblack@eecs.umich.edu
5137639Sgblack@eecs.umich.edu            %(unloadRegs)s
5147639Sgblack@eecs.umich.edu            ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
5157639Sgblack@eecs.umich.edu                    "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
5167639Sgblack@eecs.umich.edu
5177639Sgblack@eecs.umich.edu            microUnpackAllNeonIop = \
5187639Sgblack@eecs.umich.edu                InstObjParams('unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2),
5197639Sgblack@eecs.umich.edu                              'MicroUnpackAllNeon%dto%dUop' %
5207639Sgblack@eecs.umich.edu                                    (sRegs * 2, dRegs * 2),
5217639Sgblack@eecs.umich.edu                              'MicroNeonMixOp',
5227639Sgblack@eecs.umich.edu                              { 'predicate_test': predicateTest,
5237639Sgblack@eecs.umich.edu                                'code' : microUnpackAllNeonCode },
5247639Sgblack@eecs.umich.edu                                ['IsMicroop'])
5257639Sgblack@eecs.umich.edu            header_output += MicroNeonMixDeclare.subst(microUnpackAllNeonIop)
5267639Sgblack@eecs.umich.edu            exec_output += MicroNeonMixExecute.subst(microUnpackAllNeonIop)
5277639Sgblack@eecs.umich.edu
5287639Sgblack@eecs.umich.edu    for dRegs in 1, 2:
5297639Sgblack@eecs.umich.edu        unloadRegs = ''
5307639Sgblack@eecs.umich.edu        for reg in range(dRegs):
5317639Sgblack@eecs.umich.edu            unloadRegs += '''
5328588Sgblack@eecs.umich.edu                FpDestP%(reg0)d_uw = gtoh(destRegs.fRegs[%(reg0)d]);
5338588Sgblack@eecs.umich.edu                FpDestP%(reg1)d_uw = gtoh(destRegs.fRegs[%(reg1)d]);
5347639Sgblack@eecs.umich.edu            ''' % { "reg0" : (2 * reg + 0),
5357639Sgblack@eecs.umich.edu                    "reg1" : (2 * reg + 1) }
5367639Sgblack@eecs.umich.edu        for sRegs in range(dRegs, 5):
5377639Sgblack@eecs.umich.edu            loadRegs = ''
5387639Sgblack@eecs.umich.edu            for reg in range(sRegs):
5397639Sgblack@eecs.umich.edu                loadRegs += '''
5408588Sgblack@eecs.umich.edu                    sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0_uw);
5418588Sgblack@eecs.umich.edu                    sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1_uw);
5427639Sgblack@eecs.umich.edu                ''' % { "reg" : reg }
5437639Sgblack@eecs.umich.edu            microPackNeonCode = '''
54413544Sgabeblack@google.com            const unsigned perDReg =
54513544Sgabeblack@google.com                (2 * sizeof(uint32_t)) / sizeof(Element);
5467639Sgblack@eecs.umich.edu
5477639Sgblack@eecs.umich.edu            union SourceReg {
54813544Sgabeblack@google.com                uint32_t fRegs[2];
5497639Sgblack@eecs.umich.edu                Element elements[perDReg];
5507639Sgblack@eecs.umich.edu            } sourceRegs[%(sRegs)d];
5517639Sgblack@eecs.umich.edu
5527639Sgblack@eecs.umich.edu            union DestRegs {
55313544Sgabeblack@google.com                uint32_t fRegs[2 * %(dRegs)d];
5547639Sgblack@eecs.umich.edu                Element elements[%(dRegs)d * perDReg];
5557639Sgblack@eecs.umich.edu            } destRegs;
5567639Sgblack@eecs.umich.edu
5577639Sgblack@eecs.umich.edu            %(loadRegs)s
5587639Sgblack@eecs.umich.edu
5597639Sgblack@eecs.umich.edu            for (unsigned i = 0; i < %(sRegs)d; i++) {
5607639Sgblack@eecs.umich.edu                destRegs.elements[i] = sourceRegs[i].elements[lane];
5617639Sgblack@eecs.umich.edu            }
5628309Snate@binkert.org            for (unsigned i = %(sRegs)d; i < %(dRegs)d * perDReg; ++i) {
5638309Snate@binkert.org                destRegs.elements[i] = 0;
5648309Snate@binkert.org            }
5657639Sgblack@eecs.umich.edu
5667639Sgblack@eecs.umich.edu            %(unloadRegs)s
5677639Sgblack@eecs.umich.edu            ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
5687639Sgblack@eecs.umich.edu                    "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
5697639Sgblack@eecs.umich.edu
5707639Sgblack@eecs.umich.edu            microPackNeonIop = \
5717639Sgblack@eecs.umich.edu                InstObjParams('packneon%dto%duop' % (sRegs * 2, dRegs * 2),
5727639Sgblack@eecs.umich.edu                              'MicroPackNeon%dto%dUop' %
5737639Sgblack@eecs.umich.edu                                    (sRegs * 2, dRegs * 2),
5747639Sgblack@eecs.umich.edu                              'MicroNeonMixLaneOp',
5757639Sgblack@eecs.umich.edu                              { 'predicate_test': predicateTest,
5767639Sgblack@eecs.umich.edu                                'code' : microPackNeonCode },
5777639Sgblack@eecs.umich.edu                                ['IsMicroop'])
5787639Sgblack@eecs.umich.edu            header_output += MicroNeonMixLaneDeclare.subst(microPackNeonIop)
5797639Sgblack@eecs.umich.edu            exec_output += MicroNeonMixExecute.subst(microPackNeonIop)
5807639Sgblack@eecs.umich.edu}};
5817639Sgblack@eecs.umich.edu
5827639Sgblack@eecs.umich.edulet {{
5837639Sgblack@eecs.umich.edu    exec_output = ''
5848607Sgblack@eecs.umich.edu    for typeSize in (8, 16, 32):
5857639Sgblack@eecs.umich.edu        for sRegs in 1, 2:
5868607Sgblack@eecs.umich.edu            for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)):
5877639Sgblack@eecs.umich.edu                for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop",
5887639Sgblack@eecs.umich.edu                               "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop",
5897639Sgblack@eecs.umich.edu                               "MicroPackNeon%(dRegs)dto%(sRegs)dUop"):
5907639Sgblack@eecs.umich.edu                    Name = format % { "sRegs" : sRegs * 2,
5917639Sgblack@eecs.umich.edu                                      "dRegs" : dRegs * 2 }
5928607Sgblack@eecs.umich.edu                    substDict = { "class_name" : Name,
5938607Sgblack@eecs.umich.edu                                  "targs" : "uint%d_t" % typeSize }
5947639Sgblack@eecs.umich.edu                    exec_output += MicroNeonExecDeclare.subst(substDict)
5957639Sgblack@eecs.umich.edu}};
5967639Sgblack@eecs.umich.edu
5976308SN/A////////////////////////////////////////////////////////////////////
5986308SN/A//
5996308SN/A// Integer = Integer op Immediate microops
6006308SN/A//
6016308SN/A
6026308SN/Alet {{
6036308SN/A    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
6047639Sgblack@eecs.umich.edu                                    'MicroIntImmOp',
6058139SMatt.Horsnell@arm.com                                    {'code': 'URa = URb + imm;',
6066308SN/A                                     'predicate_test': predicateTest},
6076308SN/A                                    ['IsMicroop'])
6086308SN/A
6098304SAli.Saidi@ARM.com    microAddUopCode = '''
6108304SAli.Saidi@ARM.com        URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
6118304SAli.Saidi@ARM.com    '''
6128304SAli.Saidi@ARM.com
61310037SARM gem5 Developers    microAddXiUopIop = InstObjParams('addxi_uop', 'MicroAddXiUop',
61410037SARM gem5 Developers                                     'MicroIntImmXOp',
61510037SARM gem5 Developers                                     'XURa = XURb + imm;',
61610037SARM gem5 Developers                                     ['IsMicroop'])
61710037SARM gem5 Developers
61810037SARM gem5 Developers    microAddXiSpAlignUopIop = InstObjParams('addxi_uop', 'MicroAddXiSpAlignUop',
61910037SARM gem5 Developers                                            'MicroIntImmXOp', '''
62010037SARM gem5 Developers        if (isSP((IntRegIndex) urb) && bits(XURb, 3, 0) &&
62110037SARM gem5 Developers            SPAlignmentCheckEnabled(xc->tcBase())) {
62210474Sandreas.hansson@arm.com            return std::make_shared<SPAlignmentFault>();
62310037SARM gem5 Developers        }
62410037SARM gem5 Developers        XURa = XURb + imm;
62510037SARM gem5 Developers    ''', ['IsMicroop'])
62610037SARM gem5 Developers
62710037SARM gem5 Developers    microAddXERegUopIop = InstObjParams('addxr_uop', 'MicroAddXERegUop',
62810037SARM gem5 Developers                                        'MicroIntRegXOp',
62910037SARM gem5 Developers                                        'XURa = XURb + ' + \
63010037SARM gem5 Developers                                            'extendReg64(XURc, type, shiftAmt, 64);',
63110037SARM gem5 Developers                                        ['IsMicroop'])
63210037SARM gem5 Developers
6337639Sgblack@eecs.umich.edu    microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
6347646Sgene.wu@arm.com                                   'MicroIntRegOp',
6358304SAli.Saidi@ARM.com                                   {'code': microAddUopCode,
6368304SAli.Saidi@ARM.com                                    'predicate_test': pickPredicate(microAddUopCode)},
6377639Sgblack@eecs.umich.edu                                   ['IsMicroop'])
6387639Sgblack@eecs.umich.edu
6396308SN/A    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
6407639Sgblack@eecs.umich.edu                                    'MicroIntImmOp',
6418139SMatt.Horsnell@arm.com                                    {'code': 'URa = URb - imm;',
6426308SN/A                                     'predicate_test': predicateTest},
6436308SN/A                                    ['IsMicroop'])
6446308SN/A
64510037SARM gem5 Developers    microSubXiUopIop = InstObjParams('subxi_uop', 'MicroSubXiUop',
64610037SARM gem5 Developers                                     'MicroIntImmXOp',
64710037SARM gem5 Developers                                     'XURa = XURb - imm;',
64810037SARM gem5 Developers                                     ['IsMicroop'])
64910037SARM gem5 Developers
6508304SAli.Saidi@ARM.com    microSubUopCode = '''
6518304SAli.Saidi@ARM.com        URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC);
6528304SAli.Saidi@ARM.com    '''
6537646Sgene.wu@arm.com    microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
6547646Sgene.wu@arm.com                                   'MicroIntRegOp',
6558304SAli.Saidi@ARM.com                                   {'code': microSubUopCode,
6568304SAli.Saidi@ARM.com                                    'predicate_test': pickPredicate(microSubUopCode)},
6577646Sgene.wu@arm.com                                   ['IsMicroop'])
6587646Sgene.wu@arm.com
6597646Sgene.wu@arm.com    microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
6607646Sgene.wu@arm.com                                   'MicroIntMov',
6618139SMatt.Horsnell@arm.com                                   {'code': 'IWRa = URb;',
6627646Sgene.wu@arm.com                                    'predicate_test': predicateTest},
6637646Sgene.wu@arm.com                                   ['IsMicroop'])
6647646Sgene.wu@arm.com
6658148SAli.Saidi@ARM.com    microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet',
6668148SAli.Saidi@ARM.com                                      'MicroIntMov',
6678148SAli.Saidi@ARM.com                                     {'code': microRetUopCode % 'URb',
6688148SAli.Saidi@ARM.com                                      'predicate_test': predicateTest},
6698148SAli.Saidi@ARM.com                                     ['IsMicroop', 'IsNonSpeculative',
67011355Smitch.hayenga@arm.com                                      'IsSerializeAfter', 'IsSquashAfter'])
6718148SAli.Saidi@ARM.com
6728140SMatt.Horsnell@arm.com    setPCCPSRDecl = '''
6738140SMatt.Horsnell@arm.com                    CPSR cpsrOrCondCodes = URc;
6748140SMatt.Horsnell@arm.com                    SCTLR sctlr = Sctlr;
6758140SMatt.Horsnell@arm.com                    pNPC = URa;
6768303SAli.Saidi@ARM.com                    CPSR new_cpsr =
67710037SARM gem5 Developers                    cpsrWriteByInstr(cpsrOrCondCodes, URb, Scr, Nsacr,
67810037SARM gem5 Developers                                     0xF, true, sctlr.nmfi, xc->tcBase());
6798303SAli.Saidi@ARM.com                    Cpsr = ~CondCodesMask & new_cpsr;
6808303SAli.Saidi@ARM.com                    NextThumb = new_cpsr.t;
6818303SAli.Saidi@ARM.com                    NextJazelle = new_cpsr.j;
6828205SAli.Saidi@ARM.com                    NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
6838140SMatt.Horsnell@arm.com                                    | (((CPSR)URb).it1 & 0x3);
6848303SAli.Saidi@ARM.com                    CondCodesNZ = new_cpsr.nz;
6858303SAli.Saidi@ARM.com                    CondCodesC = new_cpsr.c;
6868303SAli.Saidi@ARM.com                    CondCodesV = new_cpsr.v;
6878303SAli.Saidi@ARM.com                    CondCodesGE = new_cpsr.ge;
6888140SMatt.Horsnell@arm.com                    '''
6898140SMatt.Horsnell@arm.com
6908140SMatt.Horsnell@arm.com    microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
6918140SMatt.Horsnell@arm.com                                         'MicroSetPCCPSR',
6928140SMatt.Horsnell@arm.com                                         {'code': setPCCPSRDecl,
6938140SMatt.Horsnell@arm.com                                          'predicate_test': predicateTest},
6948140SMatt.Horsnell@arm.com                                         ['IsMicroop'])
6958140SMatt.Horsnell@arm.com
6967639Sgblack@eecs.umich.edu    header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
69710037SARM gem5 Developers                    MicroIntImmDeclare.subst(microAddXiUopIop) + \
69810037SARM gem5 Developers                    MicroIntImmDeclare.subst(microAddXiSpAlignUopIop) + \
6997639Sgblack@eecs.umich.edu                    MicroIntImmDeclare.subst(microSubiUopIop) + \
70010037SARM gem5 Developers                    MicroIntImmDeclare.subst(microSubXiUopIop) + \
7017646Sgene.wu@arm.com                    MicroIntRegDeclare.subst(microAddUopIop) + \
7027646Sgene.wu@arm.com                    MicroIntRegDeclare.subst(microSubUopIop) + \
70310037SARM gem5 Developers                    MicroIntXERegDeclare.subst(microAddXERegUopIop) + \
7048140SMatt.Horsnell@arm.com                    MicroIntMovDeclare.subst(microUopRegMovIop) + \
7058148SAli.Saidi@ARM.com                    MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
7068140SMatt.Horsnell@arm.com                    MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
7077646Sgene.wu@arm.com
7087639Sgblack@eecs.umich.edu    decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
70910037SARM gem5 Developers                     MicroIntImmXConstructor.subst(microAddXiUopIop) + \
71010037SARM gem5 Developers                     MicroIntImmXConstructor.subst(microAddXiSpAlignUopIop) + \
7117639Sgblack@eecs.umich.edu                     MicroIntImmConstructor.subst(microSubiUopIop) + \
71210037SARM gem5 Developers                     MicroIntImmXConstructor.subst(microSubXiUopIop) + \
7137646Sgene.wu@arm.com                     MicroIntRegConstructor.subst(microAddUopIop) + \
7147646Sgene.wu@arm.com                     MicroIntRegConstructor.subst(microSubUopIop) + \
71510037SARM gem5 Developers                     MicroIntXERegConstructor.subst(microAddXERegUopIop) + \
7168140SMatt.Horsnell@arm.com                     MicroIntMovConstructor.subst(microUopRegMovIop) + \
7178148SAli.Saidi@ARM.com                     MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
7188140SMatt.Horsnell@arm.com                     MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
7197646Sgene.wu@arm.com
7206308SN/A    exec_output = PredOpExecute.subst(microAddiUopIop) + \
72110037SARM gem5 Developers                  BasicExecute.subst(microAddXiUopIop) + \
72210037SARM gem5 Developers                  BasicExecute.subst(microAddXiSpAlignUopIop) + \
7237639Sgblack@eecs.umich.edu                  PredOpExecute.subst(microSubiUopIop) + \
72410037SARM gem5 Developers                  BasicExecute.subst(microSubXiUopIop) + \
7257646Sgene.wu@arm.com                  PredOpExecute.subst(microAddUopIop) + \
7267646Sgene.wu@arm.com                  PredOpExecute.subst(microSubUopIop) + \
72710037SARM gem5 Developers                  BasicExecute.subst(microAddXERegUopIop) + \
7288140SMatt.Horsnell@arm.com                  PredOpExecute.subst(microUopRegMovIop) + \
7298148SAli.Saidi@ARM.com                  PredOpExecute.subst(microUopRegMovRetIop) + \
7308140SMatt.Horsnell@arm.com                  PredOpExecute.subst(microUopSetPCCPSRIop)
7318140SMatt.Horsnell@arm.com
7326308SN/A}};
7336019SN/A
7347134Sgblack@eecs.umich.edulet {{
7357170Sgblack@eecs.umich.edu    iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
7367134Sgblack@eecs.umich.edu    header_output = MacroMemDeclare.subst(iop)
7377134Sgblack@eecs.umich.edu    decoder_output = MacroMemConstructor.subst(iop)
7387179Sgblack@eecs.umich.edu
73910037SARM gem5 Developers    iop = InstObjParams("ldpstp", "LdpStp", 'PairMemOp', "", [])
74010037SARM gem5 Developers    header_output += PairMemDeclare.subst(iop)
74110037SARM gem5 Developers    decoder_output += PairMemConstructor.subst(iop)
74210037SARM gem5 Developers
74310037SARM gem5 Developers    iopImm = InstObjParams("bigfpmemimm", "BigFpMemImm", "BigFpMemImmOp", "")
74410037SARM gem5 Developers    iopPre = InstObjParams("bigfpmempre", "BigFpMemPre", "BigFpMemPreOp", "")
74510037SARM gem5 Developers    iopPost = InstObjParams("bigfpmempost", "BigFpMemPost", "BigFpMemPostOp", "")
74610037SARM gem5 Developers    for iop in (iopImm, iopPre, iopPost):
74710037SARM gem5 Developers        header_output += BigFpMemImmDeclare.subst(iop)
74810037SARM gem5 Developers        decoder_output += BigFpMemImmConstructor.subst(iop)
74910037SARM gem5 Developers
75010037SARM gem5 Developers    iop = InstObjParams("bigfpmemreg", "BigFpMemReg", "BigFpMemRegOp", "")
75110037SARM gem5 Developers    header_output += BigFpMemRegDeclare.subst(iop)
75210037SARM gem5 Developers    decoder_output += BigFpMemRegConstructor.subst(iop)
75310037SARM gem5 Developers
75410037SARM gem5 Developers    iop = InstObjParams("bigfpmemlit", "BigFpMemLit", "BigFpMemLitOp", "")
75510037SARM gem5 Developers    header_output += BigFpMemLitDeclare.subst(iop)
75610037SARM gem5 Developers    decoder_output += BigFpMemLitConstructor.subst(iop)
75710037SARM gem5 Developers
7587639Sgblack@eecs.umich.edu    iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])
7597639Sgblack@eecs.umich.edu    header_output += VMemMultDeclare.subst(iop)
7607639Sgblack@eecs.umich.edu    decoder_output += VMemMultConstructor.subst(iop)
7617639Sgblack@eecs.umich.edu
7627639Sgblack@eecs.umich.edu    iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", [])
7637639Sgblack@eecs.umich.edu    header_output += VMemSingleDeclare.subst(iop)
7647639Sgblack@eecs.umich.edu    decoder_output += VMemSingleConstructor.subst(iop)
7657639Sgblack@eecs.umich.edu
7667639Sgblack@eecs.umich.edu    iop = InstObjParams("vstmult", "VstMult", 'VstMultOp', "", [])
7677639Sgblack@eecs.umich.edu    header_output += VMemMultDeclare.subst(iop)
7687639Sgblack@eecs.umich.edu    decoder_output += VMemMultConstructor.subst(iop)
7697639Sgblack@eecs.umich.edu
7707639Sgblack@eecs.umich.edu    iop = InstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", [])
7717639Sgblack@eecs.umich.edu    header_output += VMemSingleDeclare.subst(iop)
7727639Sgblack@eecs.umich.edu    decoder_output += VMemSingleConstructor.subst(iop)
7737639Sgblack@eecs.umich.edu
7747179Sgblack@eecs.umich.edu    vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", [])
7757179Sgblack@eecs.umich.edu    header_output += MacroVFPMemDeclare.subst(vfpIop)
7767179Sgblack@eecs.umich.edu    decoder_output += MacroVFPMemConstructor.subst(vfpIop)
7776019SN/A}};
778