m5ops.isa revision 9687
1// 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software 9// licensed hereunder. You may use the software subject to the license 10// terms below provided that you ensure that this notice is replicated 11// unmodified and in its entirety in all distributions of the software, 12// modified or unmodified, in source code or in binary form. 13// 14// Redistribution and use in source and binary forms, with or without 15// modification, are permitted provided that the following conditions are 16// met: redistributions of source code must retain the above copyright 17// notice, this list of conditions and the following disclaimer; 18// redistributions in binary form must reproduce the above copyright 19// notice, this list of conditions and the following disclaimer in the 20// documentation and/or other materials provided with the distribution; 21// neither the name of the copyright holders nor the names of its 22// contributors may be used to endorse or promote products derived from 23// this software without specific prior written permission. 24// 25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36// 37// Authors: Gene Wu 38 39 40let {{ 41 header_output = ''' 42 uint64_t join32to64(uint32_t r1, uint32_t r0); 43 ''' 44 decoder_output = ''' 45 uint64_t join32to64(uint32_t r1, uint32_t r0) 46 { 47 uint64_t r = r1; 48 r <<= 32; 49 r |= r0; 50 return r; 51 } 52 ''' 53 exec_output = ''' 54 uint64_t join32to64(uint32_t r1, uint32_t r0); 55 ''' 56 57 58 armCode = ''' 59 PseudoInst::arm(xc->tcBase()); 60 ''' 61 armIop = InstObjParams("arm", "Arm", "PredOp", 62 { "code": armCode, 63 "predicate_test": predicateTest }, 64 ["IsNonSpeculative"]) 65 header_output += BasicDeclare.subst(armIop) 66 decoder_output += BasicConstructor.subst(armIop) 67 exec_output += PredOpExecute.subst(armIop) 68 69 quiesceCode = ''' 70 PseudoInst::quiesce(xc->tcBase()); 71 ''' 72 quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", 73 { "code": quiesceCode, 74 "predicate_test": predicateTest }, 75 ["IsNonSpeculative", "IsQuiesce"]) 76 header_output += BasicDeclare.subst(quiesceIop) 77 decoder_output += BasicConstructor.subst(quiesceIop) 78 exec_output += QuiescePredOpExecute.subst(quiesceIop) 79 80 quiesceNsCode = ''' 81 PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); 82 ''' 83 84 quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", 85 { "code": quiesceNsCode, 86 "predicate_test": predicateTest }, 87 ["IsNonSpeculative", "IsQuiesce"]) 88 header_output += BasicDeclare.subst(quiesceNsIop) 89 decoder_output += BasicConstructor.subst(quiesceNsIop) 90 exec_output += QuiescePredOpExecute.subst(quiesceNsIop) 91 92 quiesceCyclesCode = ''' 93 PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); 94 ''' 95 96 quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", 97 { "code": quiesceCyclesCode, 98 "predicate_test": predicateTest }, 99 ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) 100 header_output += BasicDeclare.subst(quiesceCyclesIop) 101 decoder_output += BasicConstructor.subst(quiesceCyclesIop) 102 exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) 103 104 quiesceTimeCode = ''' 105 uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); 106 R0 = bits(qt_val, 31, 0); 107 R1 = bits(qt_val, 63, 32); 108 ''' 109 110 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", 111 { "code": quiesceTimeCode, 112 "predicate_test": predicateTest }, 113 ["IsNonSpeculative", "IsUnverifiable"]) 114 header_output += BasicDeclare.subst(quiesceTimeIop) 115 decoder_output += BasicConstructor.subst(quiesceTimeIop) 116 exec_output += PredOpExecute.subst(quiesceTimeIop) 117 118 rpnsCode = ''' 119 uint64_t rpns_val = PseudoInst::rpns(xc->tcBase()); 120 R0 = bits(rpns_val, 31, 0); 121 R1 = bits(rpns_val, 63, 32); 122 ''' 123 124 rpnsIop = InstObjParams("rpns", "Rpns", "PredOp", 125 { "code": rpnsCode, 126 "predicate_test": predicateTest }, 127 ["IsNonSpeculative", "IsUnverifiable"]) 128 header_output += BasicDeclare.subst(rpnsIop) 129 decoder_output += BasicConstructor.subst(rpnsIop) 130 exec_output += PredOpExecute.subst(rpnsIop) 131 132 wakeCpuCode = ''' 133 PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0)); 134 ''' 135 136 wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp", 137 { "code": wakeCpuCode, 138 "predicate_test": predicateTest }, 139 ["IsNonSpeculative", "IsUnverifiable"]) 140 header_output += BasicDeclare.subst(wakeCPUIop) 141 decoder_output += BasicConstructor.subst(wakeCPUIop) 142 exec_output += PredOpExecute.subst(wakeCPUIop) 143 144 deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp", 145 { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''', 146 "predicate_test": predicateTest }) 147 header_output += BasicDeclare.subst(deprecated_ivlbIop) 148 decoder_output += BasicConstructor.subst(deprecated_ivlbIop) 149 exec_output += PredOpExecute.subst(deprecated_ivlbIop) 150 151 deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp", 152 { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''', 153 "predicate_test": predicateTest }) 154 header_output += BasicDeclare.subst(deprecated_ivleIop) 155 decoder_output += BasicConstructor.subst(deprecated_ivleIop) 156 exec_output += PredOpExecute.subst(deprecated_ivleIop) 157 158 deprecated_exit_code = ''' 159 warn_once("Obsolete M5 exit instruction encountered.\\n"); 160 PseudoInst::m5exit(xc->tcBase(), 0); 161 ''' 162 163 deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp", 164 { "code": deprecated_exit_code, 165 "predicate_test": predicateTest }, 166 ["No_OpClass", "IsNonSpeculative"]) 167 header_output += BasicDeclare.subst(deprecated_exitIop) 168 decoder_output += BasicConstructor.subst(deprecated_exitIop) 169 exec_output += PredOpExecute.subst(deprecated_exitIop) 170 171 m5exit_code = ''' 172 PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0)); 173 ''' 174 m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp", 175 { "code": m5exit_code, 176 "predicate_test": predicateTest }, 177 ["No_OpClass", "IsNonSpeculative"]) 178 header_output += BasicDeclare.subst(m5exitIop) 179 decoder_output += BasicConstructor.subst(m5exitIop) 180 exec_output += PredOpExecute.subst(m5exitIop) 181 182 m5fail_code = ''' 183 PseudoInst::m5fail(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 184 ''' 185 m5failIop = InstObjParams("m5fail", "M5fail", "PredOp", 186 { "code": m5fail_code, 187 "predicate_test": predicateTest }, 188 ["No_OpClass", "IsNonSpeculative"]) 189 header_output += BasicDeclare.subst(m5failIop) 190 decoder_output += BasicConstructor.subst(m5failIop) 191 exec_output += PredOpExecute.subst(m5failIop) 192 193 loadsymbolCode = ''' 194 PseudoInst::loadsymbol(xc->tcBase()); 195 ''' 196 197 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", 198 { "code": loadsymbolCode, 199 "predicate_test": predicateTest }, 200 ["No_OpClass", "IsNonSpeculative"]) 201 header_output += BasicDeclare.subst(loadsymbolIop) 202 decoder_output += BasicConstructor.subst(loadsymbolIop) 203 exec_output += PredOpExecute.subst(loadsymbolIop) 204 205 initparamCode = ''' 206 uint64_t ip_val = PseudoInst::initParam(xc->tcBase()); 207 R0 = bits(ip_val, 31, 0); 208 R1 = bits(ip_val, 63, 32); 209 ''' 210 211 initparamIop = InstObjParams("initparam", "Initparam", "PredOp", 212 { "code": initparamCode, 213 "predicate_test": predicateTest }, 214 ["IsNonSpeculative"]) 215 header_output += BasicDeclare.subst(initparamIop) 216 decoder_output += BasicConstructor.subst(initparamIop) 217 exec_output += PredOpExecute.subst(initparamIop) 218 219 resetstats_code = ''' 220 PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 221 ''' 222 223 resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp", 224 { "code": resetstats_code, 225 "predicate_test": predicateTest }, 226 ["IsNonSpeculative"]) 227 header_output += BasicDeclare.subst(resetstatsIop) 228 decoder_output += BasicConstructor.subst(resetstatsIop) 229 exec_output += PredOpExecute.subst(resetstatsIop) 230 231 dumpstats_code = ''' 232 PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 233 ''' 234 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp", 235 { "code": dumpstats_code, 236 "predicate_test": predicateTest }, 237 ["IsNonSpeculative"]) 238 header_output += BasicDeclare.subst(dumpstatsIop) 239 decoder_output += BasicConstructor.subst(dumpstatsIop) 240 exec_output += PredOpExecute.subst(dumpstatsIop) 241 242 dumpresetstats_code = ''' 243 PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 244 ''' 245 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp", 246 { "code": dumpresetstats_code, 247 "predicate_test": predicateTest }, 248 ["IsNonSpeculative"]) 249 header_output += BasicDeclare.subst(dumpresetstatsIop) 250 decoder_output += BasicConstructor.subst(dumpresetstatsIop) 251 exec_output += PredOpExecute.subst(dumpresetstatsIop) 252 253 m5checkpoint_code = ''' 254 PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 255 ''' 256 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", 257 { "code": m5checkpoint_code, 258 "predicate_test": predicateTest }, 259 ["IsNonSpeculative", "IsUnverifiable"]) 260 header_output += BasicDeclare.subst(m5checkpointIop) 261 decoder_output += BasicConstructor.subst(m5checkpointIop) 262 exec_output += PredOpExecute.subst(m5checkpointIop) 263 264 m5readfileCode = ''' 265 int n = 4; 266 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 267 R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset); 268 ''' 269 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", 270 { "code": m5readfileCode, 271 "predicate_test": predicateTest }, 272 ["IsNonSpeculative", "IsUnverifiable"]) 273 header_output += BasicDeclare.subst(m5readfileIop) 274 decoder_output += BasicConstructor.subst(m5readfileIop) 275 exec_output += PredOpExecute.subst(m5readfileIop) 276 277 m5writefileCode = ''' 278 int n = 4; 279 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 280 n = 6; 281 Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false); 282 R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset, 283 filenameAddr); 284 ''' 285 m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp", 286 { "code": m5writefileCode, 287 "predicate_test": predicateTest }, 288 ["IsNonSpeculative"]) 289 header_output += BasicDeclare.subst(m5writefileIop) 290 decoder_output += BasicConstructor.subst(m5writefileIop) 291 exec_output += PredOpExecute.subst(m5writefileIop) 292 293 m5breakIop = InstObjParams("m5break", "M5break", "PredOp", 294 { "code": "PseudoInst::debugbreak(xc->tcBase());", 295 "predicate_test": predicateTest }, 296 ["IsNonSpeculative"]) 297 header_output += BasicDeclare.subst(m5breakIop) 298 decoder_output += BasicConstructor.subst(m5breakIop) 299 exec_output += PredOpExecute.subst(m5breakIop) 300 301 m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp", 302 { "code": "PseudoInst::switchcpu(xc->tcBase());", 303 "predicate_test": predicateTest }, 304 ["IsNonSpeculative"]) 305 header_output += BasicDeclare.subst(m5switchcpuIop) 306 decoder_output += BasicConstructor.subst(m5switchcpuIop) 307 exec_output += PredOpExecute.subst(m5switchcpuIop) 308 309 m5addsymbolCode = ''' 310 PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); 311 ''' 312 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", 313 { "code": m5addsymbolCode, 314 "predicate_test": predicateTest }, 315 ["IsNonSpeculative"]) 316 header_output += BasicDeclare.subst(m5addsymbolIop) 317 decoder_output += BasicConstructor.subst(m5addsymbolIop) 318 exec_output += PredOpExecute.subst(m5addsymbolIop) 319 320 m5panicCode = '''panic("M5 panic instruction called at pc=%#x.", 321 xc->pcState().pc());''' 322 m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp", 323 { "code": m5panicCode, 324 "predicate_test": predicateTest }, 325 ["IsNonSpeculative"]) 326 header_output += BasicDeclare.subst(m5panicIop) 327 decoder_output += BasicConstructor.subst(m5panicIop) 328 exec_output += PredOpExecute.subst(m5panicIop) 329 330 m5workbeginCode = '''PseudoInst::workbegin( 331 xc->tcBase(), 332 join32to64(R1, R0), 333 join32to64(R3, R2) 334 );''' 335 m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp", 336 { "code": m5workbeginCode, 337 "predicate_test": predicateTest }, 338 ["IsNonSpeculative"]) 339 header_output += BasicDeclare.subst(m5workbeginIop) 340 decoder_output += BasicConstructor.subst(m5workbeginIop) 341 exec_output += PredOpExecute.subst(m5workbeginIop) 342 343 m5workendCode = '''PseudoInst::workend( 344 xc->tcBase(), 345 join32to64(R1, R0), 346 join32to64(R3, R2) 347 );''' 348 m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp", 349 { "code": m5workendCode, 350 "predicate_test": predicateTest }, 351 ["IsNonSpeculative"]) 352 header_output += BasicDeclare.subst(m5workendIop) 353 decoder_output += BasicConstructor.subst(m5workendIop) 354 exec_output += PredOpExecute.subst(m5workendIop) 355 356}}; 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