m5ops.isa revision 8733
111723Sar4jc@virginia.edu// 211723Sar4jc@virginia.edu// Copyright (c) 2010 ARM Limited 311723Sar4jc@virginia.edu// All rights reserved 411723Sar4jc@virginia.edu// 511723Sar4jc@virginia.edu// The license below extends only to copyright in the software and shall 611723Sar4jc@virginia.edu// not be construed as granting a license to any other intellectual 711723Sar4jc@virginia.edu// property including but not limited to intellectual property relating 811723Sar4jc@virginia.edu// to a hardware implementation of the functionality of the software 911723Sar4jc@virginia.edu// licensed hereunder. You may use the software subject to the license 1011723Sar4jc@virginia.edu// terms below provided that you ensure that this notice is replicated 1111723Sar4jc@virginia.edu// unmodified and in its entirety in all distributions of the software, 1211723Sar4jc@virginia.edu// modified or unmodified, in source code or in binary form. 1311723Sar4jc@virginia.edu// 1411723Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 1511723Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 1611723Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1711723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1811723Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 1911723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 2011723Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 2111723Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 2211723Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 2311723Sar4jc@virginia.edu// this software without specific prior written permission. 2411723Sar4jc@virginia.edu// 2511723Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2611723Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2711723Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2811723Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2911723Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3011723Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3111723Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3211723Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3311723Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3411723Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3511723Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3611723Sar4jc@virginia.edu// 3711723Sar4jc@virginia.edu// Authors: Gene Wu 3811723Sar4jc@virginia.edu 3911723Sar4jc@virginia.edu 4011723Sar4jc@virginia.edulet {{ 4111723Sar4jc@virginia.edu header_output = "" 4211723Sar4jc@virginia.edu decoder_output = ''' 4311723Sar4jc@virginia.edu uint64_t join32to64(uint32_t r1, uint32_t r0) 4411723Sar4jc@virginia.edu { 4511723Sar4jc@virginia.edu uint64_t r = r1; 4611723Sar4jc@virginia.edu r <<= 32; 4711723Sar4jc@virginia.edu r |= r0; 4811723Sar4jc@virginia.edu return r; 4911723Sar4jc@virginia.edu } 5011723Sar4jc@virginia.edu ''' 5111723Sar4jc@virginia.edu exec_output = ''' 5211723Sar4jc@virginia.edu uint64_t join32to64(uint32_t r1, uint32_t r0); 5311723Sar4jc@virginia.edu ''' 5411723Sar4jc@virginia.edu 5511723Sar4jc@virginia.edu 5611723Sar4jc@virginia.edu armCode = ''' 5711723Sar4jc@virginia.edu PseudoInst::arm(xc->tcBase()); 5811723Sar4jc@virginia.edu ''' 5911723Sar4jc@virginia.edu armIop = InstObjParams("arm", "Arm", "PredOp", 6011723Sar4jc@virginia.edu { "code": armCode, 6111723Sar4jc@virginia.edu "predicate_test": predicateTest }, 6211723Sar4jc@virginia.edu ["IsNonSpeculative"]) 6311723Sar4jc@virginia.edu header_output += BasicDeclare.subst(armIop) 6411723Sar4jc@virginia.edu decoder_output += BasicConstructor.subst(armIop) 6511723Sar4jc@virginia.edu exec_output += PredOpExecute.subst(armIop) 6611723Sar4jc@virginia.edu 6711723Sar4jc@virginia.edu quiesceCode = ''' 6811723Sar4jc@virginia.edu PseudoInst::quiesce(xc->tcBase()); 6911723Sar4jc@virginia.edu ''' 7011723Sar4jc@virginia.edu quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", 7111723Sar4jc@virginia.edu { "code": quiesceCode, 7211723Sar4jc@virginia.edu "predicate_test": predicateTest }, 7311723Sar4jc@virginia.edu ["IsNonSpeculative", "IsQuiesce"]) 7411723Sar4jc@virginia.edu header_output += BasicDeclare.subst(quiesceIop) 7511723Sar4jc@virginia.edu decoder_output += BasicConstructor.subst(quiesceIop) 7611723Sar4jc@virginia.edu exec_output += QuiescePredOpExecute.subst(quiesceIop) 7711723Sar4jc@virginia.edu 7811723Sar4jc@virginia.edu quiesceNsCode = ''' 7911723Sar4jc@virginia.edu PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); 8011723Sar4jc@virginia.edu ''' 8111723Sar4jc@virginia.edu 8211723Sar4jc@virginia.edu quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", 8311723Sar4jc@virginia.edu { "code": quiesceNsCode, 8411723Sar4jc@virginia.edu "predicate_test": predicateTest }, 8511723Sar4jc@virginia.edu ["IsNonSpeculative", "IsQuiesce"]) 8611723Sar4jc@virginia.edu header_output += BasicDeclare.subst(quiesceNsIop) 8711723Sar4jc@virginia.edu decoder_output += BasicConstructor.subst(quiesceNsIop) 8811723Sar4jc@virginia.edu exec_output += QuiescePredOpExecute.subst(quiesceNsIop) 8911723Sar4jc@virginia.edu 9011723Sar4jc@virginia.edu quiesceCyclesCode = ''' 9111723Sar4jc@virginia.edu PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); 9211723Sar4jc@virginia.edu ''' 9311723Sar4jc@virginia.edu 9411723Sar4jc@virginia.edu quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", 9511723Sar4jc@virginia.edu { "code": quiesceCyclesCode, 9611723Sar4jc@virginia.edu "predicate_test": predicateTest }, 9711723Sar4jc@virginia.edu ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) 9811723Sar4jc@virginia.edu header_output += BasicDeclare.subst(quiesceCyclesIop) 9911723Sar4jc@virginia.edu decoder_output += BasicConstructor.subst(quiesceCyclesIop) 10011723Sar4jc@virginia.edu exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) 10111723Sar4jc@virginia.edu 10211723Sar4jc@virginia.edu quiesceTimeCode = ''' 10311723Sar4jc@virginia.edu uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); 10411723Sar4jc@virginia.edu R0 = bits(qt_val, 31, 0); 10511723Sar4jc@virginia.edu R1 = bits(qt_val, 63, 32); 10611723Sar4jc@virginia.edu ''' 10711723Sar4jc@virginia.edu 10811723Sar4jc@virginia.edu quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", 10911723Sar4jc@virginia.edu { "code": quiesceTimeCode, 11011723Sar4jc@virginia.edu "predicate_test": predicateTest }, 11111723Sar4jc@virginia.edu ["IsNonSpeculative", "IsUnverifiable"]) 11211723Sar4jc@virginia.edu header_output += BasicDeclare.subst(quiesceTimeIop) 11311723Sar4jc@virginia.edu decoder_output += BasicConstructor.subst(quiesceTimeIop) 11411723Sar4jc@virginia.edu exec_output += PredOpExecute.subst(quiesceTimeIop) 11511723Sar4jc@virginia.edu 11611723Sar4jc@virginia.edu rpnsCode = ''' 11711723Sar4jc@virginia.edu uint64_t rpns_val = PseudoInst::rpns(xc->tcBase()); 11811723Sar4jc@virginia.edu R0 = bits(rpns_val, 31, 0); 11911723Sar4jc@virginia.edu R1 = bits(rpns_val, 63, 32); 12011723Sar4jc@virginia.edu ''' 12111723Sar4jc@virginia.edu 12211723Sar4jc@virginia.edu rpnsIop = InstObjParams("rpns", "Rpns", "PredOp", 12311723Sar4jc@virginia.edu { "code": rpnsCode, 12411723Sar4jc@virginia.edu "predicate_test": predicateTest }, 12511723Sar4jc@virginia.edu ["IsNonSpeculative", "IsUnverifiable"]) 12611723Sar4jc@virginia.edu header_output += BasicDeclare.subst(rpnsIop) 12711723Sar4jc@virginia.edu decoder_output += BasicConstructor.subst(rpnsIop) 12811723Sar4jc@virginia.edu exec_output += PredOpExecute.subst(rpnsIop) 12911723Sar4jc@virginia.edu 13011723Sar4jc@virginia.edu wakeCpuCode = ''' 13111723Sar4jc@virginia.edu PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0)); 13211723Sar4jc@virginia.edu ''' 13311723Sar4jc@virginia.edu 13411723Sar4jc@virginia.edu wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp", 13511723Sar4jc@virginia.edu { "code": wakeCpuCode, 13611723Sar4jc@virginia.edu "predicate_test": predicateTest }, 13711723Sar4jc@virginia.edu ["IsNonSpeculative", "IsUnverifiable"]) 13811723Sar4jc@virginia.edu header_output += BasicDeclare.subst(wakeCPUIop) 13911723Sar4jc@virginia.edu decoder_output += BasicConstructor.subst(wakeCPUIop) 14011723Sar4jc@virginia.edu exec_output += PredOpExecute.subst(wakeCPUIop) 141 142 deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp", 143 { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''', 144 "predicate_test": predicateTest }) 145 header_output += BasicDeclare.subst(deprecated_ivlbIop) 146 decoder_output += BasicConstructor.subst(deprecated_ivlbIop) 147 exec_output += PredOpExecute.subst(deprecated_ivlbIop) 148 149 deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp", 150 { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''', 151 "predicate_test": predicateTest }) 152 header_output += BasicDeclare.subst(deprecated_ivleIop) 153 decoder_output += BasicConstructor.subst(deprecated_ivleIop) 154 exec_output += PredOpExecute.subst(deprecated_ivleIop) 155 156 deprecated_exit_code = ''' 157 warn_once("Obsolete M5 exit instruction encountered.\\n"); 158 PseudoInst::m5exit(xc->tcBase(), 0); 159 ''' 160 161 deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp", 162 { "code": deprecated_exit_code, 163 "predicate_test": predicateTest }, 164 ["No_OpClass", "IsNonSpeculative"]) 165 header_output += BasicDeclare.subst(deprecated_exitIop) 166 decoder_output += BasicConstructor.subst(deprecated_exitIop) 167 exec_output += PredOpExecute.subst(deprecated_exitIop) 168 169 m5exit_code = ''' 170 PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0)); 171 ''' 172 m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp", 173 { "code": m5exit_code, 174 "predicate_test": predicateTest }, 175 ["No_OpClass", "IsNonSpeculative"]) 176 header_output += BasicDeclare.subst(m5exitIop) 177 decoder_output += BasicConstructor.subst(m5exitIop) 178 exec_output += PredOpExecute.subst(m5exitIop) 179 180 loadsymbolCode = ''' 181 PseudoInst::loadsymbol(xc->tcBase()); 182 ''' 183 184 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", 185 { "code": loadsymbolCode, 186 "predicate_test": predicateTest }, 187 ["No_OpClass", "IsNonSpeculative"]) 188 header_output += BasicDeclare.subst(loadsymbolIop) 189 decoder_output += BasicConstructor.subst(loadsymbolIop) 190 exec_output += PredOpExecute.subst(loadsymbolIop) 191 192 initparamCode = ''' 193#if FULL_SYSTEM 194 uint64_t ip_val = PseudoInst::initParam(xc->tcBase()); 195 R0 = bits(ip_val, 31, 0); 196 R1 = bits(ip_val, 63, 32); 197#else 198 PseudoInst::panicFsOnlyPseudoInst("initparam"); 199#endif 200 ''' 201 202 initparamIop = InstObjParams("initparam", "Initparam", "PredOp", 203 { "code": initparamCode, 204 "predicate_test": predicateTest }, 205 ["IsNonSpeculative"]) 206 header_output += BasicDeclare.subst(initparamIop) 207 decoder_output += BasicConstructor.subst(initparamIop) 208 exec_output += PredOpExecute.subst(initparamIop) 209 210 resetstats_code = ''' 211 PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 212 ''' 213 214 resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp", 215 { "code": resetstats_code, 216 "predicate_test": predicateTest }, 217 ["IsNonSpeculative"]) 218 header_output += BasicDeclare.subst(resetstatsIop) 219 decoder_output += BasicConstructor.subst(resetstatsIop) 220 exec_output += PredOpExecute.subst(resetstatsIop) 221 222 dumpstats_code = ''' 223 PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 224 ''' 225 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp", 226 { "code": dumpstats_code, 227 "predicate_test": predicateTest }, 228 ["IsNonSpeculative"]) 229 header_output += BasicDeclare.subst(dumpstatsIop) 230 decoder_output += BasicConstructor.subst(dumpstatsIop) 231 exec_output += PredOpExecute.subst(dumpstatsIop) 232 233 dumpresetstats_code = ''' 234 PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 235 ''' 236 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp", 237 { "code": dumpresetstats_code, 238 "predicate_test": predicateTest }, 239 ["IsNonSpeculative"]) 240 header_output += BasicDeclare.subst(dumpresetstatsIop) 241 decoder_output += BasicConstructor.subst(dumpresetstatsIop) 242 exec_output += PredOpExecute.subst(dumpresetstatsIop) 243 244 m5checkpoint_code = ''' 245 PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 246 ''' 247 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", 248 { "code": m5checkpoint_code, 249 "predicate_test": predicateTest }, 250 ["IsNonSpeculative", "IsUnverifiable"]) 251 header_output += BasicDeclare.subst(m5checkpointIop) 252 decoder_output += BasicConstructor.subst(m5checkpointIop) 253 exec_output += PredOpExecute.subst(m5checkpointIop) 254 255 m5readfileCode = ''' 256 int n = 4; 257 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 258 R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset); 259 ''' 260 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", 261 { "code": m5readfileCode, 262 "predicate_test": predicateTest }, 263 ["IsNonSpeculative", "IsUnverifiable"]) 264 header_output += BasicDeclare.subst(m5readfileIop) 265 decoder_output += BasicConstructor.subst(m5readfileIop) 266 exec_output += PredOpExecute.subst(m5readfileIop) 267 268 m5breakIop = InstObjParams("m5break", "M5break", "PredOp", 269 { "code": "PseudoInst::debugbreak(xc->tcBase());", 270 "predicate_test": predicateTest }, 271 ["IsNonSpeculative"]) 272 header_output += BasicDeclare.subst(m5breakIop) 273 decoder_output += BasicConstructor.subst(m5breakIop) 274 exec_output += PredOpExecute.subst(m5breakIop) 275 276 m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp", 277 { "code": "PseudoInst::switchcpu(xc->tcBase());", 278 "predicate_test": predicateTest }, 279 ["IsNonSpeculative"]) 280 header_output += BasicDeclare.subst(m5switchcpuIop) 281 decoder_output += BasicConstructor.subst(m5switchcpuIop) 282 exec_output += PredOpExecute.subst(m5switchcpuIop) 283 284 m5addsymbolCode = ''' 285 PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); 286 ''' 287 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", 288 { "code": m5addsymbolCode, 289 "predicate_test": predicateTest }, 290 ["IsNonSpeculative"]) 291 header_output += BasicDeclare.subst(m5addsymbolIop) 292 decoder_output += BasicConstructor.subst(m5addsymbolIop) 293 exec_output += PredOpExecute.subst(m5addsymbolIop) 294 295 m5panicCode = '''panic("M5 panic instruction called at pc=%#x.", 296 xc->pcState().pc());''' 297 m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp", 298 { "code": m5panicCode, 299 "predicate_test": predicateTest }, 300 ["IsNonSpeculative"]) 301 header_output += BasicDeclare.subst(m5panicIop) 302 decoder_output += BasicConstructor.subst(m5panicIop) 303 exec_output += PredOpExecute.subst(m5panicIop) 304 305 m5workbeginCode = '''PseudoInst::workbegin( 306 xc->tcBase(), 307 join32to64(R1, R0), 308 join32to64(R3, R2) 309 );''' 310 m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp", 311 { "code": m5workbeginCode, 312 "predicate_test": predicateTest }, 313 ["IsNonSpeculative"]) 314 header_output += BasicDeclare.subst(m5workbeginIop) 315 decoder_output += BasicConstructor.subst(m5workbeginIop) 316 exec_output += PredOpExecute.subst(m5workbeginIop) 317 318 m5workendCode = '''PseudoInst::workend( 319 xc->tcBase(), 320 join32to64(R1, R0), 321 join32to64(R3, R2) 322 );''' 323 m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp", 324 { "code": m5workendCode, 325 "predicate_test": predicateTest }, 326 ["IsNonSpeculative"]) 327 header_output += BasicDeclare.subst(m5workendIop) 328 decoder_output += BasicConstructor.subst(m5workendIop) 329 exec_output += PredOpExecute.subst(m5workendIop) 330 331}}; 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