m5ops.isa revision 8142
17732SAli.Saidi@ARM.com// 27732SAli.Saidi@ARM.com// Copyright (c) 2010 ARM Limited 37732SAli.Saidi@ARM.com// All rights reserved 47732SAli.Saidi@ARM.com// 57732SAli.Saidi@ARM.com// The license below extends only to copyright in the software and shall 67732SAli.Saidi@ARM.com// not be construed as granting a license to any other intellectual 77732SAli.Saidi@ARM.com// property including but not limited to intellectual property relating 87732SAli.Saidi@ARM.com// to a hardware implementation of the functionality of the software 97732SAli.Saidi@ARM.com// licensed hereunder. You may use the software subject to the license 107732SAli.Saidi@ARM.com// terms below provided that you ensure that this notice is replicated 117732SAli.Saidi@ARM.com// unmodified and in its entirety in all distributions of the software, 127732SAli.Saidi@ARM.com// modified or unmodified, in source code or in binary form. 137732SAli.Saidi@ARM.com// 147732SAli.Saidi@ARM.com// Redistribution and use in source and binary forms, with or without 157732SAli.Saidi@ARM.com// modification, are permitted provided that the following conditions are 167732SAli.Saidi@ARM.com// met: redistributions of source code must retain the above copyright 177732SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer; 187732SAli.Saidi@ARM.com// redistributions in binary form must reproduce the above copyright 197732SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the 207732SAli.Saidi@ARM.com// documentation and/or other materials provided with the distribution; 217732SAli.Saidi@ARM.com// neither the name of the copyright holders nor the names of its 227732SAli.Saidi@ARM.com// contributors may be used to endorse or promote products derived from 237732SAli.Saidi@ARM.com// this software without specific prior written permission. 247732SAli.Saidi@ARM.com// 257732SAli.Saidi@ARM.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267732SAli.Saidi@ARM.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277732SAli.Saidi@ARM.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287732SAli.Saidi@ARM.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297732SAli.Saidi@ARM.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307732SAli.Saidi@ARM.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317732SAli.Saidi@ARM.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327732SAli.Saidi@ARM.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337732SAli.Saidi@ARM.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347732SAli.Saidi@ARM.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357732SAli.Saidi@ARM.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367732SAli.Saidi@ARM.com// 377732SAli.Saidi@ARM.com// Authors: Gene Wu 387732SAli.Saidi@ARM.com 397732SAli.Saidi@ARM.com 407732SAli.Saidi@ARM.comlet {{ 417732SAli.Saidi@ARM.com header_output = "" 427732SAli.Saidi@ARM.com decoder_output = "" 437732SAli.Saidi@ARM.com exec_output = "" 447732SAli.Saidi@ARM.com 457732SAli.Saidi@ARM.com armCode = ''' 467732SAli.Saidi@ARM.com#if FULL_SYSTEM 477732SAli.Saidi@ARM.com PseudoInst::arm(xc->tcBase()); 487732SAli.Saidi@ARM.com#endif 497732SAli.Saidi@ARM.com ''' 507732SAli.Saidi@ARM.com armIop = InstObjParams("arm", "Arm", "PredOp", 517732SAli.Saidi@ARM.com { "code": armCode, 527732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 537732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 547732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(armIop) 557732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(armIop) 567732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(armIop) 577732SAli.Saidi@ARM.com 587732SAli.Saidi@ARM.com quiesceCode = ''' 597732SAli.Saidi@ARM.com#if FULL_SYSTEM 607732SAli.Saidi@ARM.com PseudoInst::quiesceNs(xc->tcBase(), R0); 617732SAli.Saidi@ARM.com#endif 627732SAli.Saidi@ARM.com ''' 637732SAli.Saidi@ARM.com quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", 647732SAli.Saidi@ARM.com { "code": quiesceCode, 657732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 667732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce"]) 677732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceIop) 687732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceIop) 698142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceIop) 707732SAli.Saidi@ARM.com 717732SAli.Saidi@ARM.com quiesceNsCode = ''' 727732SAli.Saidi@ARM.com#if FULL_SYSTEM 737732SAli.Saidi@ARM.com PseudoInst::quiesceNs(xc->tcBase(), R0); 747732SAli.Saidi@ARM.com#endif 757732SAli.Saidi@ARM.com ''' 767732SAli.Saidi@ARM.com 777732SAli.Saidi@ARM.com quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", 787732SAli.Saidi@ARM.com { "code": quiesceNsCode, 797732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 807732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce"]) 817732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceNsIop) 827732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceNsIop) 838142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceNsIop) 847732SAli.Saidi@ARM.com 857732SAli.Saidi@ARM.com quiesceCyclesCode = ''' 867732SAli.Saidi@ARM.com#if FULL_SYSTEM 877732SAli.Saidi@ARM.com PseudoInst::quiesceCycles(xc->tcBase(), R0); 887732SAli.Saidi@ARM.com#endif 897732SAli.Saidi@ARM.com ''' 907732SAli.Saidi@ARM.com 917732SAli.Saidi@ARM.com quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", 927732SAli.Saidi@ARM.com { "code": quiesceCyclesCode, 937732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 947732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) 957732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceCyclesIop) 967732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceCyclesIop) 978142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) 987732SAli.Saidi@ARM.com 997732SAli.Saidi@ARM.com quiesceTimeCode = ''' 1007732SAli.Saidi@ARM.com#if FULL_SYSTEM 1017732SAli.Saidi@ARM.com R0 = PseudoInst::quiesceTime(xc->tcBase()); 1027732SAli.Saidi@ARM.com#endif 1037732SAli.Saidi@ARM.com ''' 1047732SAli.Saidi@ARM.com 1057732SAli.Saidi@ARM.com quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", 1067732SAli.Saidi@ARM.com { "code": quiesceTimeCode, 1077732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1087732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1097732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceTimeIop) 1107732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceTimeIop) 1117732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(quiesceTimeIop) 1127732SAli.Saidi@ARM.com 1137732SAli.Saidi@ARM.com rpnsIop = InstObjParams("rpns", "Rpns", "PredOp", 1147732SAli.Saidi@ARM.com { "code": "R0 = PseudoInst::rpns(xc->tcBase());", 1157732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1167732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1177732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(rpnsIop) 1187732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(rpnsIop) 1197732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(rpnsIop) 1207732SAli.Saidi@ARM.com 1217732SAli.Saidi@ARM.com wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp", 1227732SAli.Saidi@ARM.com { "code": "PseudoInst::wakeCPU(xc->tcBase(), R0);", 1237732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1247732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1257732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(wakeCPUIop) 1267732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(wakeCPUIop) 1277732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(wakeCPUIop) 1287732SAli.Saidi@ARM.com 1297732SAli.Saidi@ARM.com deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp", 1307732SAli.Saidi@ARM.com { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''', 1317732SAli.Saidi@ARM.com "predicate_test": predicateTest }) 1327732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_ivlbIop) 1337732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_ivlbIop) 1347732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_ivlbIop) 1357732SAli.Saidi@ARM.com 1367732SAli.Saidi@ARM.com deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp", 1377732SAli.Saidi@ARM.com { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''', 1387732SAli.Saidi@ARM.com "predicate_test": predicateTest }) 1397732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_ivleIop) 1407732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_ivleIop) 1417732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_ivleIop) 1427732SAli.Saidi@ARM.com 1437732SAli.Saidi@ARM.com deprecated_exit_code = ''' 1447732SAli.Saidi@ARM.com warn_once("Obsolete M5 exit instruction encountered.\\n"); 1457732SAli.Saidi@ARM.com PseudoInst::m5exit(xc->tcBase(), 0); 1467732SAli.Saidi@ARM.com ''' 1477732SAli.Saidi@ARM.com 1487732SAli.Saidi@ARM.com deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp", 1497732SAli.Saidi@ARM.com { "code": deprecated_exit_code, 1507732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1517732SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 1527732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_exitIop) 1537732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_exitIop) 1547732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_exitIop) 1557732SAli.Saidi@ARM.com 1567732SAli.Saidi@ARM.com m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp", 1577732SAli.Saidi@ARM.com { "code": "PseudoInst::m5exit(xc->tcBase(), R0)", 1587732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1597732SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 1607732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5exitIop) 1617732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5exitIop) 1627732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5exitIop) 1637732SAli.Saidi@ARM.com 1647732SAli.Saidi@ARM.com loadsymbolCode = ''' 1657732SAli.Saidi@ARM.com#if FULL_SYSTEM 1667732SAli.Saidi@ARM.com PseudoInst::loadsymbol(xc->tcBase()); 1677732SAli.Saidi@ARM.com#endif 1687732SAli.Saidi@ARM.com ''' 1697732SAli.Saidi@ARM.com 1707732SAli.Saidi@ARM.com loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", 1717732SAli.Saidi@ARM.com { "code": loadsymbolCode, 1727732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1737732SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 1747732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(loadsymbolIop) 1757732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(loadsymbolIop) 1767732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(loadsymbolIop) 1777732SAli.Saidi@ARM.com 1787732SAli.Saidi@ARM.com initparamCode = ''' 1797732SAli.Saidi@ARM.com#if FULL_SYSTEM 1807732SAli.Saidi@ARM.com Rt = xc->tcBase()->getCpuPtr()->system->init_param; 1817732SAli.Saidi@ARM.com#endif 1827732SAli.Saidi@ARM.com ''' 1837732SAli.Saidi@ARM.com 1847732SAli.Saidi@ARM.com initparamIop = InstObjParams("initparam", "Initparam", "PredOp", 1857732SAli.Saidi@ARM.com { "code": initparamCode, 1867732SAli.Saidi@ARM.com "predicate_test": predicateTest }) 1877732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(initparamIop) 1887732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(initparamIop) 1897732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(initparamIop) 1907732SAli.Saidi@ARM.com 1917732SAli.Saidi@ARM.com resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp", 1927732SAli.Saidi@ARM.com { "code": "PseudoInst::resetstats(xc->tcBase(), R0, R1);", 1937732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1947732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 1957732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(resetstatsIop) 1967732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(resetstatsIop) 1977732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(resetstatsIop) 1987732SAli.Saidi@ARM.com 1997732SAli.Saidi@ARM.com dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp", 2007732SAli.Saidi@ARM.com { "code": "PseudoInst::dumpstats(xc->tcBase(), R0, R1);", 2017732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2027732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2037732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(dumpstatsIop) 2047732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(dumpstatsIop) 2057732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(dumpstatsIop) 2067732SAli.Saidi@ARM.com 2077732SAli.Saidi@ARM.com dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp", 2087732SAli.Saidi@ARM.com { "code": "PseudoInst::dumpresetstats(xc->tcBase(), R0, R1);", 2097732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2107732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2117732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(dumpresetstatsIop) 2127732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(dumpresetstatsIop) 2137732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(dumpresetstatsIop) 2147732SAli.Saidi@ARM.com 2157732SAli.Saidi@ARM.com m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", 2167732SAli.Saidi@ARM.com { "code": "PseudoInst::m5checkpoint(xc->tcBase(), R0, R1);", 2177732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2187732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2197732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5checkpointIop) 2207732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5checkpointIop) 2217732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5checkpointIop) 2227732SAli.Saidi@ARM.com 2237732SAli.Saidi@ARM.com m5readfileCode = ''' 2247732SAli.Saidi@ARM.com#if FULL_SYSTEM 2257732SAli.Saidi@ARM.com R0 = PseudoInst::readfile(xc->tcBase(), R0, R1, R2); 2267732SAli.Saidi@ARM.com#endif 2277732SAli.Saidi@ARM.com ''' 2287732SAli.Saidi@ARM.com m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", 2297732SAli.Saidi@ARM.com { "code": m5readfileCode, 2307732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2317732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2327732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5readfileIop) 2337732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5readfileIop) 2347732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5readfileIop) 2357732SAli.Saidi@ARM.com 2367732SAli.Saidi@ARM.com m5breakIop = InstObjParams("m5break", "M5break", "PredOp", 2377732SAli.Saidi@ARM.com { "code": "PseudoInst::debugbreak(xc->tcBase());", 2387732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2397732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2407732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5breakIop) 2417732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5breakIop) 2427732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5breakIop) 2437732SAli.Saidi@ARM.com 2447732SAli.Saidi@ARM.com m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp", 2457732SAli.Saidi@ARM.com { "code": "PseudoInst::switchcpu(xc->tcBase());", 2467732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2477732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2487732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5switchcpuIop) 2497732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5switchcpuIop) 2507732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5switchcpuIop) 2517732SAli.Saidi@ARM.com 2527732SAli.Saidi@ARM.com m5addsymbolCode = ''' 2537732SAli.Saidi@ARM.com#if FULL_SYSTEM 2547732SAli.Saidi@ARM.com PseudoInst::addsymbol(xc->tcBase(), R0, R1); 2557732SAli.Saidi@ARM.com#endif 2567732SAli.Saidi@ARM.com ''' 2577732SAli.Saidi@ARM.com m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", 2587732SAli.Saidi@ARM.com { "code": m5addsymbolCode, 2597732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2607732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2617732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5addsymbolIop) 2627732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5addsymbolIop) 2637732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5addsymbolIop) 2647732SAli.Saidi@ARM.com 2657732SAli.Saidi@ARM.com m5panicCode = '''panic("M5 panic instruction called at pc=%#x.", 2667732SAli.Saidi@ARM.com xc->pcState().pc());''' 2677732SAli.Saidi@ARM.com m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp", 2687732SAli.Saidi@ARM.com { "code": m5panicCode, 2697732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2707732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2717732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5panicIop) 2727732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5panicIop) 2737732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5panicIop) 2747732SAli.Saidi@ARM.com 2757732SAli.Saidi@ARM.com}}; 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