pred.isa revision 8301
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43let {{ 44 45 calcCcCode = ''' 46 if (%(canOverflow)s){ 47 cprintf("canOverflow: %%d\\n", Rd < resTemp); 48 CpsrQ = (Rd < resTemp) ? 1 << 27 : 0; 49 } else { 50 uint16_t _ic, _iv, _iz, _in; 51 _in = (resTemp >> %(negBit)d) & 1; 52 _iz = (resTemp == 0); 53 _iv = %(ivValue)s & 1; 54 _ic = %(icValue)s & 1; 55 56 CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28; 57 58 DPRINTF(Arm, "in = %%d\\n", _in); 59 DPRINTF(Arm, "iz = %%d\\n", _iz); 60 DPRINTF(Arm, "ic = %%d\\n", _ic); 61 DPRINTF(Arm, "iv = %%d\\n", _iv); 62 } 63 ''' 64}}; 65 66let {{ 67 def getCcCode(flagtype): 68 icReg = icImm = iv = '' 69 negBit = 31 70 canOverflow = 'false' 71 72 if flagtype == "none": 73 icReg = icImm = 'CondCodesF<29:>' 74 iv = 'CondCodesF<28:>' 75 elif flagtype == "llbit": 76 icReg = icImm = 'CondCodesF<29:>' 77 iv = 'CondCodesF<28:>' 78 negBit = 63 79 elif flagtype == "overflow": 80 canOverflow = "true" 81 icReg = icImm = iv = '0' 82 elif flagtype == "add": 83 icReg = icImm = 'findCarry(32, resTemp, Rn, op2)' 84 iv = 'findOverflow(32, resTemp, Rn, op2)' 85 elif flagtype == "sub": 86 icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)' 87 iv = 'findOverflow(32, resTemp, Rn, ~op2)' 88 elif flagtype == "rsb": 89 icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)' 90 iv = 'findOverflow(32, resTemp, op2, ~Rn)' 91 else: 92 icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesF<29:>)' 93 icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesF<29:>)' 94 iv = 'CondCodesF<28:>' 95 return (calcCcCode % {"icValue" : icReg, 96 "ivValue" : iv, 97 "negBit" : negBit, 98 "canOverflow" : canOverflow }, 99 calcCcCode % {"icValue" : icImm, 100 "ivValue" : iv, 101 "negBit" : negBit, 102 "canOverflow" : canOverflow }) 103 104 def getImmCcCode(flagtype): 105 ivValue = icValue = '' 106 negBit = 31 107 canOverflow = 'false' 108 if flagtype == "none": 109 icValue = 'CondCodesF<29:>' 110 ivValue = 'CondCodesF<28:>' 111 elif flagtype == "llbit": 112 icValue = 'CondCodesF<29:>' 113 ivValue = 'CondCodesF<28:>' 114 negBit = 63 115 elif flagtype == "overflow": 116 icVaule = ivValue = '0' 117 canOverflow = "true" 118 elif flagtype == "add": 119 icValue = 'findCarry(32, resTemp, Rn, rotated_imm)' 120 ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)' 121 elif flagtype == "sub": 122 icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)' 123 ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)' 124 elif flagtype == "rsb": 125 icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)' 126 ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)' 127 elif flagtype == "modImm": 128 icValue = 'rotated_carry' 129 ivValue = 'CondCodesF<28:>' 130 else: 131 icValue = '(rotate ? rotated_carry:CondCodesF<29:>)' 132 ivValue = 'CondCodesF<28:>' 133 return calcCcCode % vars() 134}}; 135 136def format DataOp(code, flagtype = logic) {{ 137 (regCcCode, immCcCode) = getCcCode(flagtype) 138 regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>, 139 shift, CondCodesF<29:>); 140 op2 = op2;''' + code 141 immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size, 142 shift, CondCodesF<29:>); 143 op2 = op2;''' + code 144 regIop = InstObjParams(name, Name, 'PredIntOp', 145 {"code": regCode, 146 "predicate_test": predicateTest}) 147 immIop = InstObjParams(name, Name + "Imm", 'PredIntOp', 148 {"code": immCode, 149 "predicate_test": predicateTest}) 150 regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp', 151 {"code": regCode + regCcCode, 152 "predicate_test": condPredicateTest}) 153 immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp', 154 {"code": immCode + immCcCode, 155 "predicate_test": condPredicateTest}) 156 header_output = BasicDeclare.subst(regIop) + \ 157 BasicDeclare.subst(immIop) + \ 158 BasicDeclare.subst(regCcIop) + \ 159 BasicDeclare.subst(immCcIop) 160 decoder_output = BasicConstructor.subst(regIop) + \ 161 BasicConstructor.subst(immIop) + \ 162 BasicConstructor.subst(regCcIop) + \ 163 BasicConstructor.subst(immCcIop) 164 exec_output = PredOpExecute.subst(regIop) + \ 165 PredOpExecute.subst(immIop) + \ 166 PredOpExecute.subst(regCcIop) + \ 167 PredOpExecute.subst(immCcIop) 168 decode_block = DataDecode.subst(regIop) 169}}; 170 171def format DataImmOp(code, flagtype = logic) {{ 172 code += "resTemp = resTemp;" 173 iop = InstObjParams(name, Name, 'PredImmOp', 174 {"code": code, 175 "predicate_test": predicateTest}) 176 ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp', 177 {"code": code + getImmCcCode(flagtype), 178 "predicate_test": condPredicateTest}) 179 header_output = BasicDeclare.subst(iop) + \ 180 BasicDeclare.subst(ccIop) 181 decoder_output = BasicConstructor.subst(iop) + \ 182 BasicConstructor.subst(ccIop) 183 exec_output = PredOpExecute.subst(iop) + \ 184 PredOpExecute.subst(ccIop) 185 decode_block = DataImmDecode.subst(iop) 186}}; 187 188def format PredOp(code, *opt_flags) {{ 189 iop = InstObjParams(name, Name, 'PredOp', 190 {"code": code, 191 "predicate_test": predicateTest}, 192 opt_flags) 193 header_output = BasicDeclare.subst(iop) 194 decoder_output = BasicConstructor.subst(iop) 195 decode_block = BasicDecode.subst(iop) 196 exec_output = PredOpExecute.subst(iop) 197}}; 198 199def format PredImmOp(code, *opt_flags) {{ 200 iop = InstObjParams(name, Name, 'PredImmOp', 201 {"code": code, 202 "predicate_test": predicateTest}, 203 opt_flags) 204 header_output = BasicDeclare.subst(iop) 205 decoder_output = BasicConstructor.subst(iop) 206 decode_block = BasicDecode.subst(iop) 207 exec_output = PredOpExecute.subst(iop) 208}}; 209 210