data.isa revision 7216
1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Gabe Black 37 38def format ArmDataProcReg() {{ 39 pclr = ''' 40 return new %(className)ssRegPclr(machInst, %(dest)s, 41 %(op1)s, rm, imm5, 42 type); 43 ''' 44 instDecode = ''' 45 case %(opcode)#x: 46 if (immShift) { 47 if (setCc) { 48 if (%(dest)s == INTREG_PC) { 49 %(pclr)s 50 } else { 51 return new %(className)sRegCc(machInst, %(dest)s, 52 %(op1)s, rm, imm5, type); 53 } 54 } else { 55 return new %(className)sReg(machInst, %(dest)s, %(op1)s, 56 rm, imm5, type); 57 } 58 } else { 59 if (setCc) { 60 return new %(className)sRegRegCc(machInst, %(dest)s, 61 %(op1)s, rm, rs, type); 62 } else { 63 return new %(className)sRegReg(machInst, %(dest)s, 64 %(op1)s, rm, rs, type); 65 } 66 } 67 break; 68 ''' 69 70 def instCode(opcode, mnem, useDest = True, useOp1 = True): 71 global pclr 72 if useDest: 73 dest = "rd" 74 else: 75 dest = "INTREG_ZERO" 76 if useOp1: 77 op1 = "rn" 78 else: 79 op1 = "INTREG_ZERO" 80 global instDecode, pclrCode 81 substDict = { "className": mnem.capitalize(), 82 "opcode": opcode, 83 "dest": dest, 84 "op1": op1 } 85 if useDest: 86 substDict["pclr"] = pclr % substDict 87 else: 88 substDict["pclr"] = "" 89 return instDecode % substDict 90 91 decode_block = ''' 92 { 93 const bool immShift = (bits(machInst, 4) == 0); 94 const bool setCc = (bits(machInst, 20) == 1); 95 const uint32_t imm5 = bits(machInst, 11, 7); 96 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 97 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 98 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 99 const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 100 const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 101 switch (OPCODE) { 102 ''' 103 decode_block += instCode(0x0, "and") 104 decode_block += instCode(0x1, "eor") 105 decode_block += instCode(0x2, "sub") 106 decode_block += instCode(0x3, "rsb") 107 decode_block += instCode(0x4, "add") 108 decode_block += instCode(0x5, "adc") 109 decode_block += instCode(0x6, "sbc") 110 decode_block += instCode(0x7, "rsc") 111 decode_block += instCode(0x8, "tst", useDest = False) 112 decode_block += instCode(0x9, "teq", useDest = False) 113 decode_block += instCode(0xa, "cmp", useDest = False) 114 decode_block += instCode(0xb, "cmn", useDest = False) 115 decode_block += instCode(0xc, "orr") 116 decode_block += instCode(0xd, "mov", useOp1 = False) 117 decode_block += instCode(0xe, "bic") 118 decode_block += instCode(0xf, "mvn", useOp1 = False) 119 decode_block += ''' 120 default: 121 return new Unknown(machInst); 122 } 123 } 124 ''' 125}}; 126 127def format ArmPackUnpackSatReverse() {{ 128 decode_block = ''' 129 { 130 const uint32_t op1 = bits(machInst, 22, 20); 131 const uint32_t a = bits(machInst, 19, 16); 132 const uint32_t op2 = bits(machInst, 7, 5); 133 if (bits(op2, 0) == 0) { 134 if (op1 == 0) { 135 return new WarnUnimplemented("pkh", machInst); 136 } else if (bits(op1, 2, 1) == 1) { 137 return new WarnUnimplemented("ssat", machInst); 138 } else if (bits(op1, 2, 1) == 3) { 139 return new WarnUnimplemented("usat", machInst); 140 } 141 return new Unknown(machInst); 142 } 143 switch (op1) { 144 case 0x0: 145 if (op2 == 0x3) { 146 if (a == 0xf) { 147 return new WarnUnimplemented("sxtb16", machInst); 148 } else { 149 return new WarnUnimplemented("sxtab16", machInst); 150 } 151 } else if (op2 == 0x5) { 152 return new WarnUnimplemented("sel", machInst); 153 } 154 break; 155 case 0x2: 156 if (op2 == 0x1) { 157 return new WarnUnimplemented("ssat16", machInst); 158 } else if (op2 == 0x3) { 159 if (a == 0xf) { 160 return new WarnUnimplemented("sxtb", machInst); 161 } else { 162 return new WarnUnimplemented("sxtab", machInst); 163 } 164 } 165 break; 166 case 0x3: 167 if (op2 == 0x1) { 168 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 169 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 170 return new Rev(machInst, rd, rm); 171 } else if (op2 == 0x3) { 172 if (a == 0xf) { 173 return new WarnUnimplemented("sxth", machInst); 174 } else { 175 return new WarnUnimplemented("sxtah", machInst); 176 } 177 } else if (op2 == 0x5) { 178 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 179 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 180 return new Rev16(machInst, rd, rm); 181 } 182 break; 183 case 0x4: 184 if (op2 == 0x3) { 185 if (a == 0xf) { 186 return new WarnUnimplemented("uxtb16", machInst); 187 } else { 188 return new WarnUnimplemented("uxtab16", machInst); 189 } 190 } 191 break; 192 case 0x6: 193 if (op2 == 0x1) { 194 return new WarnUnimplemented("usat16", machInst); 195 } else if (op2 == 0x3) { 196 if (a == 0xf) { 197 return new WarnUnimplemented("uxtb", machInst); 198 } else { 199 return new WarnUnimplemented("uxtab", machInst); 200 } 201 } 202 break; 203 case 0x7: 204 if (op2 == 0x1) { 205 return new WarnUnimplemented("rbit", machInst); 206 } else if (op2 == 0x3) { 207 if (a == 0xf) { 208 return new WarnUnimplemented("uxth", machInst); 209 } else { 210 return new WarnUnimplemented("uxtah", machInst); 211 } 212 } else if (op2 == 0x5) { 213 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 214 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 215 return new Revsh(machInst, rd, rm); 216 } 217 break; 218 } 219 return new Unknown(machInst); 220 } 221 ''' 222}}; 223 224def format ArmParallelAddSubtract() {{ 225 decode_block=''' 226 { 227 const uint32_t op1 = bits(machInst, 21, 20); 228 const uint32_t op2 = bits(machInst, 7, 5); 229 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 230 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 231 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 232 if (bits(machInst, 22) == 0) { 233 switch (op1) { 234 case 0x1: 235 switch (op2) { 236 case 0x0: 237 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 238 case 0x1: 239 return new WarnUnimplemented("sasx", machInst); 240 case 0x2: 241 return new WarnUnimplemented("ssax", machInst); 242 case 0x3: 243 return new WarnUnimplemented("ssub16", machInst); 244 case 0x4: 245 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 246 case 0x7: 247 return new WarnUnimplemented("ssub8", machInst); 248 } 249 break; 250 case 0x2: 251 switch (op2) { 252 case 0x0: 253 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 254 case 0x1: 255 return new QasxReg(machInst, rd, rn, rm, 0, LSL); 256 case 0x2: 257 return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 258 case 0x3: 259 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 260 case 0x4: 261 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 262 case 0x7: 263 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 264 } 265 break; 266 case 0x3: 267 switch (op2) { 268 case 0x0: 269 return new WarnUnimplemented("shadd16", machInst); 270 case 0x1: 271 return new WarnUnimplemented("shasx", machInst); 272 case 0x2: 273 return new WarnUnimplemented("shsax", machInst); 274 case 0x3: 275 return new WarnUnimplemented("shsub16", machInst); 276 case 0x4: 277 return new WarnUnimplemented("shadd8", machInst); 278 case 0x7: 279 return new WarnUnimplemented("shsub8", machInst); 280 } 281 break; 282 } 283 } else { 284 switch (op1) { 285 case 0x1: 286 switch (op2) { 287 case 0x0: 288 return new WarnUnimplemented("uadd16", machInst); 289 case 0x1: 290 return new WarnUnimplemented("uasx", machInst); 291 case 0x2: 292 return new WarnUnimplemented("usax", machInst); 293 case 0x3: 294 return new WarnUnimplemented("usub16", machInst); 295 case 0x4: 296 return new WarnUnimplemented("uadd8", machInst); 297 case 0x7: 298 return new WarnUnimplemented("usub8", machInst); 299 } 300 break; 301 case 0x2: 302 switch (op2) { 303 case 0x0: 304 return new WarnUnimplemented("uqadd16", machInst); 305 case 0x1: 306 return new WarnUnimplemented("uqasx", machInst); 307 case 0x2: 308 return new WarnUnimplemented("uqsax", machInst); 309 case 0x3: 310 return new WarnUnimplemented("uqsub16", machInst); 311 case 0x4: 312 return new WarnUnimplemented("uqadd8", machInst); 313 case 0x7: 314 return new WarnUnimplemented("uqsub8", machInst); 315 } 316 break; 317 case 0x3: 318 switch (op2) { 319 case 0x0: 320 return new WarnUnimplemented("uhadd16", machInst); 321 case 0x1: 322 return new WarnUnimplemented("uhasx", machInst); 323 case 0x2: 324 return new WarnUnimplemented("uhsax", machInst); 325 case 0x3: 326 return new WarnUnimplemented("uhsub16", machInst); 327 case 0x4: 328 return new WarnUnimplemented("uhadd8", machInst); 329 case 0x7: 330 return new WarnUnimplemented("uhsub8", machInst); 331 } 332 break; 333 } 334 } 335 return new Unknown(machInst); 336 } 337 ''' 338}}; 339 340def format ArmDataProcImm() {{ 341 pclr = ''' 342 return new %(className)ssImmPclr(machInst, %(dest)s, 343 %(op1)s, imm, false); 344 ''' 345 adr = ''' 346 return new AdrImm(machInst, %(dest)s, %(add)s, 347 imm, false); 348 ''' 349 instDecode = ''' 350 case %(opcode)#x: 351 if (setCc) { 352 if (%(pclrInst)s && %(dest)s == INTREG_PC) { 353 %(pclr)s 354 } else { 355 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 356 imm, rotC); 357 } 358 } else { 359 if (%(adrInst)s && %(op1)s == INTREG_PC) { 360 %(adr)s 361 } else { 362 return new %(className)sImm(machInst, %(dest)s, %(op1)s, 363 imm, rotC); 364 } 365 } 366 break; 367 ''' 368 369 def instCode(opcode, mnem, useDest = True, useOp1 = True): 370 global instDecode, pclr, adr 371 if useDest: 372 dest = "rd" 373 else: 374 dest = "INTREG_ZERO" 375 if useOp1: 376 op1 = "rn" 377 else: 378 op1 = "INTREG_ZERO" 379 substDict = { "className": mnem.capitalize(), 380 "opcode": opcode, 381 "dest": dest, 382 "op1": op1, 383 "adr": "", 384 "adrInst": "false" } 385 if useDest: 386 substDict["pclrInst"] = "true" 387 substDict["pclr"] = pclr % substDict 388 else: 389 substDict["pclrInst"] = "false" 390 substDict["pclr"] = "" 391 return instDecode % substDict 392 393 def adrCode(opcode, mnem, add="1"): 394 global instDecode, pclr, adr 395 substDict = { "className": mnem.capitalize(), 396 "opcode": opcode, 397 "dest": "rd", 398 "op1": "rn", 399 "add": add, 400 "pclrInst": "true", 401 "adrInst": "true" } 402 substDict["pclr"] = pclr % substDict 403 substDict["adr"] = adr % substDict 404 return instDecode % substDict 405 406 decode_block = ''' 407 { 408 const bool setCc = (bits(machInst, 20) == 1); 409 const uint32_t unrotated = bits(machInst, 7, 0); 410 const uint32_t rotation = (bits(machInst, 11, 8) << 1); 411 const bool rotC = (rotation != 0); 412 const uint32_t imm = rotate_imm(unrotated, rotation); 413 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 414 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 415 switch (OPCODE) { 416 ''' 417 decode_block += instCode(0x0, "and") 418 decode_block += instCode(0x1, "eor") 419 decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 420 decode_block += instCode(0x3, "rsb") 421 decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 422 decode_block += instCode(0x5, "adc") 423 decode_block += instCode(0x6, "sbc") 424 decode_block += instCode(0x7, "rsc") 425 decode_block += instCode(0x8, "tst", useDest = False) 426 decode_block += instCode(0x9, "teq", useDest = False) 427 decode_block += instCode(0xa, "cmp", useDest = False) 428 decode_block += instCode(0xb, "cmn", useDest = False) 429 decode_block += instCode(0xc, "orr") 430 decode_block += instCode(0xd, "mov", useOp1 = False) 431 decode_block += instCode(0xe, "bic") 432 decode_block += instCode(0xf, "mvn", useOp1 = False) 433 decode_block += ''' 434 default: 435 return new Unknown(machInst); 436 } 437 } 438 ''' 439}}; 440 441def format ArmSatAddSub() {{ 442 decode_block = ''' 443 { 444 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 445 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 446 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 447 switch (OPCODE) { 448 case 0x8: 449 return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 450 case 0x9: 451 return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 452 case 0xa: 453 return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 454 case 0xb: 455 return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 456 default: 457 return new Unknown(machInst); 458 } 459 } 460 ''' 461}}; 462 463def format Thumb32DataProcReg() {{ 464 decode_block = ''' 465 { 466 const uint32_t op1 = bits(machInst, 23, 20); 467 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 468 const uint32_t op2 = bits(machInst, 7, 4); 469 if (bits(op1, 3) != 1) { 470 if (op2 == 0) { 471 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 472 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 473 switch (bits(op1, 2, 0)) { 474 case 0x0: 475 return new MovRegReg(machInst, rd, 476 INTREG_ZERO, rn, rm, LSL); 477 case 0x1: 478 return new MovRegRegCc(machInst, rd, 479 INTREG_ZERO, rn, rm, LSL); 480 case 0x2: 481 return new MovRegReg(machInst, rd, 482 INTREG_ZERO, rn, rm, LSR); 483 case 0x3: 484 return new MovRegRegCc(machInst, rd, 485 INTREG_ZERO, rn, rm, LSR); 486 case 0x4: 487 return new MovRegReg(machInst, rd, 488 INTREG_ZERO, rn, rm, ASR); 489 case 0x5: 490 return new MovRegRegCc(machInst, rd, 491 INTREG_ZERO, rn, rm, ASR); 492 case 0x6: 493 return new MovRegReg(machInst, rd, 494 INTREG_ZERO, rn, rm, ROR); 495 case 0x7: 496 return new MovRegRegCc(machInst, rd, 497 INTREG_ZERO, rn, rm, ROR); 498 } 499 } 500 switch (bits(op1, 2, 0)) { 501 case 0x0: 502 if (rn == 0xf) { 503 return new WarnUnimplemented("sxth", machInst); 504 } else { 505 return new WarnUnimplemented("sxtah", machInst); 506 } 507 case 0x1: 508 if (rn == 0xf) { 509 return new WarnUnimplemented("uxth", machInst); 510 } else { 511 return new WarnUnimplemented("uxtah", machInst); 512 } 513 case 0x2: 514 if (rn == 0xf) { 515 return new WarnUnimplemented("sxtb16", machInst); 516 } else { 517 return new WarnUnimplemented("sxtab16", machInst); 518 } 519 case 0x3: 520 if (rn == 0xf) { 521 return new WarnUnimplemented("uxtb16", machInst); 522 } else { 523 return new WarnUnimplemented("uxtab16", machInst); 524 } 525 case 0x4: 526 if (rn == 0xf) { 527 return new WarnUnimplemented("sxtb", machInst); 528 } else { 529 return new WarnUnimplemented("sxtab", machInst); 530 } 531 case 0x5: 532 if (rn == 0xf) { 533 return new WarnUnimplemented("uxtb", machInst); 534 } else { 535 return new WarnUnimplemented("uxtab", machInst); 536 } 537 default: 538 return new Unknown(machInst); 539 } 540 } else { 541 if (bits(op2, 3) == 0) { 542 if (bits(op2, 2) == 0x0) { 543 const uint32_t op1 = bits(machInst, 22, 20); 544 const uint32_t op2 = bits(machInst, 5, 4); 545 const IntRegIndex rd = 546 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 547 const IntRegIndex rm = 548 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 549 switch (op2) { 550 case 0x0: 551 switch (op1) { 552 case 0x1: 553 return new Sadd16RegCc(machInst, rd, 554 rn, rm, 0, LSL); 555 case 0x2: 556 return new WarnUnimplemented("sasx", machInst); 557 case 0x6: 558 return new WarnUnimplemented("ssax", machInst); 559 case 0x5: 560 return new WarnUnimplemented("ssub16", machInst); 561 case 0x0: 562 return new Sadd8RegCc(machInst, rd, 563 rn, rm, 0, LSL); 564 case 0x4: 565 return new WarnUnimplemented("ssub8", machInst); 566 } 567 break; 568 case 0x1: 569 switch (op1) { 570 case 0x1: 571 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 572 case 0x2: 573 return new QasxReg(machInst, rd, rn, rm, 0, LSL); 574 case 0x6: 575 return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 576 case 0x5: 577 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 578 case 0x0: 579 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 580 case 0x4: 581 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 582 } 583 break; 584 case 0x2: 585 switch (op1) { 586 case 0x1: 587 return new WarnUnimplemented("shadd16", machInst); 588 case 0x2: 589 return new WarnUnimplemented("shasx", machInst); 590 case 0x6: 591 return new WarnUnimplemented("shsax", machInst); 592 case 0x5: 593 return new WarnUnimplemented("shsub16", machInst); 594 case 0x0: 595 return new WarnUnimplemented("shadd8", machInst); 596 case 0x4: 597 return new WarnUnimplemented("shsub8", machInst); 598 } 599 break; 600 } 601 } else { 602 const uint32_t op1 = bits(machInst, 22, 20); 603 const uint32_t op2 = bits(machInst, 5, 4); 604 switch (op2) { 605 case 0x0: 606 switch (op1) { 607 case 0x1: 608 return new WarnUnimplemented("uadd16", machInst); 609 case 0x2: 610 return new WarnUnimplemented("uasx", machInst); 611 case 0x6: 612 return new WarnUnimplemented("usax", machInst); 613 case 0x5: 614 return new WarnUnimplemented("usub16", machInst); 615 case 0x0: 616 return new WarnUnimplemented("uadd8", machInst); 617 case 0x4: 618 return new WarnUnimplemented("usub8", machInst); 619 } 620 break; 621 case 0x1: 622 switch (op1) { 623 case 0x1: 624 return new WarnUnimplemented("uqadd16", machInst); 625 case 0x2: 626 return new WarnUnimplemented("uqasx", machInst); 627 case 0x6: 628 return new WarnUnimplemented("uqsax", machInst); 629 case 0x5: 630 return new WarnUnimplemented("uqsub16", machInst); 631 case 0x0: 632 return new WarnUnimplemented("uqadd8", machInst); 633 case 0x4: 634 return new WarnUnimplemented("uqsub8", machInst); 635 } 636 break; 637 case 0x2: 638 switch (op1) { 639 case 0x1: 640 return new WarnUnimplemented("uhadd16", machInst); 641 case 0x2: 642 return new WarnUnimplemented("uhasx", machInst); 643 case 0x6: 644 return new WarnUnimplemented("uhsax", machInst); 645 case 0x5: 646 return new WarnUnimplemented("uhsub16", machInst); 647 case 0x0: 648 return new WarnUnimplemented("uhadd8", machInst); 649 case 0x4: 650 return new WarnUnimplemented("uhsub8", machInst); 651 } 652 break; 653 } 654 } 655 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 656 const uint32_t op1 = bits(machInst, 21, 20); 657 const uint32_t op2 = bits(machInst, 5, 4); 658 switch (op1) { 659 case 0x0: 660 { 661 IntRegIndex rd = 662 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 663 IntRegIndex rm = 664 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 665 switch (op2) { 666 case 0x0: 667 return new QaddRegCc(machInst, rd, 668 rm, rn, 0, LSL); 669 case 0x1: 670 return new QdaddRegCc(machInst, rd, 671 rm, rn, 0, LSL); 672 case 0x2: 673 return new QsubRegCc(machInst, rd, 674 rm, rn, 0, LSL); 675 case 0x3: 676 return new QdsubRegCc(machInst, rd, 677 rm, rn, 0, LSL); 678 } 679 } 680 break; 681 case 0x1: 682 { 683 IntRegIndex rd = 684 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 685 IntRegIndex rm = rn; 686 switch (op2) { 687 case 0x0: 688 return new Rev(machInst, rd, rm); 689 case 0x1: 690 return new Rev16(machInst, rd, rm); 691 case 0x2: 692 return new WarnUnimplemented("rbit", machInst); 693 case 0x3: 694 return new Revsh(machInst, rd, rm); 695 } 696 } 697 break; 698 case 0x2: 699 if (op2 == 0) { 700 return new WarnUnimplemented("sel", machInst); 701 } 702 break; 703 case 0x3: 704 if (op2 == 0) { 705 return new WarnUnimplemented("clz", machInst); 706 } 707 } 708 } 709 return new Unknown(machInst); 710 } 711 } 712 ''' 713}}; 714 715def format Thumb16ShiftAddSubMoveCmp() {{ 716 decode_block = ''' 717 { 718 const uint32_t imm5 = bits(machInst, 10, 6); 719 const uint32_t imm3 = bits(machInst, 8, 6); 720 const uint32_t imm8 = bits(machInst, 7, 0); 721 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 722 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 723 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 724 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 725 switch (bits(machInst, 13, 11)) { 726 case 0x0: // lsl 727 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 728 case 0x1: // lsr 729 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 730 case 0x2: // asr 731 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 732 case 0x3: 733 switch (bits(machInst, 10, 9)) { 734 case 0x0: 735 return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 736 case 0x1: 737 return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 738 case 0x2: 739 return new AddImmCc(machInst, rd, rn, imm3, true); 740 case 0x3: 741 return new SubImmCc(machInst, rd, rn, imm3, true); 742 } 743 case 0x4: 744 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 745 case 0x5: 746 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 747 case 0x6: 748 return new AddImmCc(machInst, rd8, rd8, imm8, true); 749 case 0x7: 750 return new SubImmCc(machInst, rd8, rd8, imm8, true); 751 } 752 } 753 ''' 754}}; 755 756def format Thumb16DataProcessing() {{ 757 decode_block = ''' 758 { 759 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 760 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 761 switch (bits(machInst, 9, 6)) { 762 case 0x0: 763 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 764 case 0x1: 765 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 766 case 0x2: //lsl 767 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL); 768 case 0x3: //lsr 769 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR); 770 case 0x4: //asr 771 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR); 772 case 0x5: 773 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 774 case 0x6: 775 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 776 case 0x7: // ror 777 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR); 778 case 0x8: 779 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 780 case 0x9: 781 return new RsbImmCc(machInst, rdn, rm, 0, true); 782 case 0xa: 783 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 784 case 0xb: 785 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 786 case 0xc: 787 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 788 case 0xd: 789 return new MulCc(machInst, rdn, rm, rdn); 790 case 0xe: 791 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 792 case 0xf: 793 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 794 } 795 } 796 ''' 797}}; 798 799def format Thumb16SpecDataAndBx() {{ 800 decode_block = ''' 801 { 802 const IntRegIndex rdn = 803 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 804 (bits(machInst, 7) << 3)); 805 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 806 switch (bits(machInst, 9, 8)) { 807 case 0x0: 808 return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 809 case 0x1: 810 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 811 case 0x2: 812 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 813 case 0x3: 814 if (bits(machInst, 7) == 0) { 815 return new BxReg(machInst, 816 (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 817 COND_UC); 818 } else { 819 return new BlxReg(machInst, 820 (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 821 COND_UC); 822 } 823 } 824 } 825 ''' 826}}; 827 828def format Thumb16Adr() {{ 829 decode_block = ''' 830 { 831 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 832 const uint32_t imm8 = bits(machInst, 7, 0) << 2; 833 return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 834 } 835 ''' 836}}; 837 838def format Thumb16AddSp() {{ 839 decode_block = ''' 840 { 841 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 842 const uint32_t imm8 = bits(machInst, 7, 0) << 2; 843 return new AddImm(machInst, rd, INTREG_SP, imm8, true); 844 } 845 ''' 846}}; 847 848def format Thumb16Misc() {{ 849 decode_block = ''' 850 { 851 switch (bits(machInst, 11, 8)) { 852 case 0x0: 853 if (bits(machInst, 7)) { 854 return new SubImm(machInst, INTREG_SP, INTREG_SP, 855 bits(machInst, 6, 0) << 2, true); 856 } else { 857 return new AddImm(machInst, INTREG_SP, INTREG_SP, 858 bits(machInst, 6, 0) << 2, true); 859 } 860 case 0x1: 861 return new Cbz(machInst, 862 (bits(machInst, 9) << 6) | 863 (bits(machInst, 7, 3) << 1), 864 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 865 case 0x2: 866 switch (bits(machInst, 7, 6)) { 867 case 0x0: 868 return new WarnUnimplemented("sxth", machInst); 869 case 0x1: 870 return new WarnUnimplemented("sxtb", machInst); 871 case 0x2: 872 return new WarnUnimplemented("uxth", machInst); 873 case 0x3: 874 return new WarnUnimplemented("uxtb", machInst); 875 } 876 case 0x3: 877 return new Cbz(machInst, 878 (bits(machInst, 9) << 6) | 879 (bits(machInst, 7, 3) << 1), 880 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 881 case 0x4: 882 case 0x5: 883 { 884 const uint32_t m = bits(machInst, 8); 885 const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 886 return new LdmStm(machInst, INTREG_SP, false, false, false, 887 true, false, regList); 888 } 889 case 0x6: 890 { 891 const uint32_t opBits = bits(machInst, 7, 5); 892 if (opBits == 2) { 893 return new WarnUnimplemented("setend", machInst); 894 } else if (opBits == 3) { 895 return new WarnUnimplemented("cps", machInst); 896 } 897 } 898 case 0x9: 899 return new Cbnz(machInst, 900 (bits(machInst, 9) << 6) | 901 (bits(machInst, 7, 3) << 1), 902 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 903 case 0xa: 904 { 905 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 906 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 907 switch (bits(machInst, 7, 6)) { 908 case 0x0: 909 return new Rev(machInst, rd, rm); 910 case 0x1: 911 return new Rev16(machInst, rd, rm); 912 case 0x3: 913 return new Revsh(machInst, rd, rm); 914 default: 915 break; 916 } 917 } 918 break; 919 case 0xb: 920 return new Cbnz(machInst, 921 (bits(machInst, 9) << 6) | 922 (bits(machInst, 7, 3) << 1), 923 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 924 case 0xc: 925 case 0xd: 926 { 927 const uint32_t p = bits(machInst, 8); 928 const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 929 return new LdmStm(machInst, INTREG_SP, true, true, false, 930 true, true, regList); 931 } 932 case 0xe: 933 return new WarnUnimplemented("bkpt", machInst); 934 case 0xf: 935 if (bits(machInst, 3, 0) != 0) 936 return new WarnUnimplemented("it", machInst); 937 switch (bits(machInst, 7, 4)) { 938 case 0x0: 939 return new WarnUnimplemented("nop", machInst); 940 case 0x1: 941 return new WarnUnimplemented("yield", machInst); 942 case 0x2: 943 return new WarnUnimplemented("wfe", machInst); 944 case 0x3: 945 return new WarnUnimplemented("wfi", machInst); 946 case 0x4: 947 return new WarnUnimplemented("sev", machInst); 948 default: 949 return new WarnUnimplemented("unallocated_hint", machInst); 950 } 951 default: 952 break; 953 } 954 return new Unknown(machInst); 955 } 956 ''' 957}}; 958 959def format Thumb32DataProcModImm() {{ 960 961 def decInst(mnem, dest="rd", op1="rn"): 962 return ''' 963 if (s) { 964 return new %(mnem)sImmCc(machInst, %(dest)s, 965 %(op1)s, imm, rotC); 966 } else { 967 return new %(mnem)sImm(machInst, %(dest)s, 968 %(op1)s, imm, rotC); 969 } 970 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 971 972 decode_block = ''' 973 { 974 const uint32_t op = bits(machInst, 24, 21); 975 const bool s = (bits(machInst, 20) == 1); 976 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 977 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 978 const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 979 bits(machInst, 14, 12); 980 const bool rotC = ctrlImm > 3; 981 const uint32_t dataImm = bits(machInst, 7, 0); 982 const uint32_t imm = modified_imm(ctrlImm, dataImm); 983 switch (op) { 984 case 0x0: 985 if (rd == INTREG_PC) { 986 %(tst)s 987 } else { 988 %(and)s 989 } 990 case 0x1: 991 %(bic)s 992 case 0x2: 993 if (rn == INTREG_PC) { 994 %(mov)s 995 } else { 996 %(orr)s 997 } 998 case 0x3: 999 if (rn == INTREG_PC) { 1000 %(mvn)s 1001 } else { 1002 %(orn)s 1003 } 1004 case 0x4: 1005 if (rd == INTREG_PC) { 1006 %(teq)s 1007 } else { 1008 %(eor)s 1009 } 1010 case 0x8: 1011 if (rd == INTREG_PC) { 1012 %(cmn)s 1013 } else { 1014 %(add)s 1015 } 1016 case 0xa: 1017 %(adc)s 1018 case 0xb: 1019 %(sbc)s 1020 case 0xd: 1021 if (rd == INTREG_PC) { 1022 %(cmp)s 1023 } else { 1024 %(sub)s 1025 } 1026 case 0xe: 1027 %(rsb)s 1028 default: 1029 return new Unknown(machInst); 1030 } 1031 } 1032 ''' % { 1033 "tst" : decInst("Tst", "INTREG_ZERO"), 1034 "and" : decInst("And"), 1035 "bic" : decInst("Bic"), 1036 "mov" : decInst("Mov", op1="INTREG_ZERO"), 1037 "orr" : decInst("Orr"), 1038 "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 1039 "orn" : decInst("Orn"), 1040 "teq" : decInst("Teq", dest="INTREG_ZERO"), 1041 "eor" : decInst("Eor"), 1042 "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 1043 "add" : decInst("Add"), 1044 "adc" : decInst("Adc"), 1045 "sbc" : decInst("Sbc"), 1046 "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 1047 "sub" : decInst("Sub"), 1048 "rsb" : decInst("Rsb") 1049 } 1050}}; 1051 1052def format Thumb32DataProcPlainBin() {{ 1053 decode_block = ''' 1054 { 1055 const uint32_t op = bits(machInst, 24, 20); 1056 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1057 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 1058 switch (op) { 1059 case 0x0: 1060 { 1061 const uint32_t imm = bits(machInst, 7, 0) | 1062 (bits(machInst, 14, 12) << 8) | 1063 (bits(machInst, 26) << 11); 1064 if (rn == 0xf) { 1065 return new AdrImm(machInst, rd, (IntRegIndex)1, 1066 imm, false); 1067 } else { 1068 return new AddImm(machInst, rd, rn, imm, true); 1069 } 1070 } 1071 case 0x4: 1072 { 1073 const uint32_t imm = bits(machInst, 7, 0) | 1074 (bits(machInst, 14, 12) << 8) | 1075 (bits(machInst, 26) << 11) | 1076 (bits(machInst, 19, 16) << 12); 1077 return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 1078 } 1079 case 0xa: 1080 { 1081 const uint32_t imm = bits(machInst, 7, 0) | 1082 (bits(machInst, 14, 12) << 8) | 1083 (bits(machInst, 26) << 11); 1084 if (rn == 0xf) { 1085 return new AdrImm(machInst, rd, (IntRegIndex)0, 1086 imm, false); 1087 } else { 1088 return new SubImm(machInst, rd, rn, imm, true); 1089 } 1090 } 1091 case 0xc: 1092 { 1093 const uint32_t imm = bits(machInst, 7, 0) | 1094 (bits(machInst, 14, 12) << 8) | 1095 (bits(machInst, 26) << 11) | 1096 (bits(machInst, 19, 16) << 12); 1097 return new MovtImm(machInst, rd, rd, imm, true); 1098 } 1099 case 0x12: 1100 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 1101 return new WarnUnimplemented("ssat16", machInst); 1102 } 1103 // Fall through on purpose... 1104 case 0x10: 1105 return new WarnUnimplemented("ssat", machInst); 1106 case 0x14: 1107 return new WarnUnimplemented("sbfx", machInst); 1108 case 0x16: 1109 if (rn == 0xf) { 1110 return new WarnUnimplemented("bfc", machInst); 1111 } else { 1112 return new WarnUnimplemented("bfi", machInst); 1113 } 1114 case 0x1a: 1115 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 1116 return new WarnUnimplemented("usat16", machInst); 1117 } 1118 // Fall through on purpose... 1119 case 0x18: 1120 return new WarnUnimplemented("usat", machInst); 1121 case 0x1c: 1122 return new WarnUnimplemented("ubfx", machInst); 1123 default: 1124 return new Unknown(machInst); 1125 } 1126 } 1127 ''' 1128}}; 1129 1130def format Thumb32DataProcShiftReg() {{ 1131 1132 def decInst(mnem, dest="rd", op1="rn"): 1133 return ''' 1134 if (s) { 1135 return new %(mnem)sRegCc(machInst, %(dest)s, 1136 %(op1)s, rm, amt, type); 1137 } else { 1138 return new %(mnem)sReg(machInst, %(dest)s, 1139 %(op1)s, rm, amt, type); 1140 } 1141 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 1142 1143 decode_block = ''' 1144 { 1145 const uint32_t op = bits(machInst, 24, 21); 1146 const bool s = (bits(machInst, 20) == 1); 1147 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1148 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 1149 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1150 const uint32_t amt = (bits(machInst, 14, 12) << 2) | 1151 bits(machInst, 7, 6); 1152 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 1153 switch (op) { 1154 case 0x0: 1155 if (rd == INTREG_PC) { 1156 %(tst)s 1157 } else { 1158 %(and)s 1159 } 1160 case 0x1: 1161 %(bic)s 1162 case 0x2: 1163 if (rn == INTREG_PC) { 1164 %(mov)s 1165 } else { 1166 %(orr)s 1167 } 1168 case 0x3: 1169 if (rn == INTREG_PC) { 1170 %(mvn)s 1171 } else { 1172 %(orn)s 1173 } 1174 case 0x4: 1175 if (rd == INTREG_PC) { 1176 %(teq)s 1177 } else { 1178 %(eor)s 1179 } 1180 case 0x6: 1181 return new WarnUnimplemented("pkh", machInst); 1182 case 0x8: 1183 if (rd == INTREG_PC) { 1184 %(cmn)s 1185 } else { 1186 %(add)s 1187 } 1188 case 0xa: 1189 %(adc)s 1190 case 0xb: 1191 %(sbc)s 1192 case 0xd: 1193 if (rd == INTREG_PC) { 1194 %(cmp)s 1195 } else { 1196 %(sub)s 1197 } 1198 case 0xe: 1199 %(rsb)s 1200 default: 1201 return new Unknown(machInst); 1202 } 1203 } 1204 ''' % { 1205 "tst" : decInst("Tst", "INTREG_ZERO"), 1206 "and" : decInst("And"), 1207 "bic" : decInst("Bic"), 1208 "mov" : decInst("Mov", op1="INTREG_ZERO"), 1209 "orr" : decInst("Orr"), 1210 "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 1211 "orn" : decInst("Orn"), 1212 "teq" : decInst("Teq", "INTREG_ZERO"), 1213 "eor" : decInst("Eor"), 1214 "cmn" : decInst("Cmn", "INTREG_ZERO"), 1215 "add" : decInst("Add"), 1216 "adc" : decInst("Adc"), 1217 "sbc" : decInst("Sbc"), 1218 "cmp" : decInst("Cmp", "INTREG_ZERO"), 1219 "sub" : decInst("Sub"), 1220 "rsb" : decInst("Rsb") 1221 } 1222}}; 1223