data.isa revision 7139
1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Gabe Black 37 38def format ArmDataProcReg() {{ 39 instDecode = ''' 40 case %(opcode)#x: 41 if (immShift) { 42 if (setCc) { 43 return new %(className)sDRegCc(machInst, 44 rd, rn, rm, imm5, type); 45 } else { 46 return new %(className)sDReg(machInst, 47 rd, rn, rm, imm5, type); 48 } 49 } else { 50 if (setCc) { 51 return new %(className)sDRegRegCc(machInst, 52 rd, rn, rm, rs, type); 53 } else { 54 return new %(className)sDRegReg(machInst, 55 rd, rn, rm, rs, type); 56 } 57 } 58 break; 59 ''' 60 61 def instCode(opcode, mnem): 62 global instDecode 63 return instDecode % { "className": mnem.capitalize(), 64 "opcode": opcode } 65 66 decode_block = ''' 67 { 68 const bool immShift = (bits(machInst, 4) == 0); 69 const bool setCc = (bits(machInst, 20) == 1); 70 const uint32_t imm5 = bits(machInst, 11, 7); 71 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 72 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 73 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 74 const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 75 const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 76 switch (OPCODE) { 77 ''' 78 decode_block += instCode(0x0, "and") 79 decode_block += instCode(0x1, "eor") 80 decode_block += instCode(0x2, "sub") 81 decode_block += instCode(0x3, "rsb") 82 decode_block += instCode(0x4, "add") 83 decode_block += instCode(0x5, "adc") 84 decode_block += instCode(0x6, "sbc") 85 decode_block += instCode(0x7, "rsc") 86 decode_block += instCode(0x8, "tst") 87 decode_block += instCode(0x9, "teq") 88 decode_block += instCode(0xa, "cmp") 89 decode_block += instCode(0xb, "cmn") 90 decode_block += instCode(0xc, "orr") 91 decode_block += instCode(0xd, "mov") 92 decode_block += instCode(0xe, "bic") 93 decode_block += instCode(0xf, "mvn") 94 decode_block += ''' 95 default: 96 return new Unknown(machInst); 97 } 98 } 99 ''' 100}}; 101 102def format ArmDataProcImm() {{ 103 instDecode = ''' 104 case %(opcode)#x: 105 if (setCc) { 106 return new %(className)sDImmCc(machInst, rd, rn, imm, rotC); 107 } else { 108 return new %(className)sDImm(machInst, rd, rn, imm, rotC); 109 } 110 break; 111 ''' 112 113 def instCode(opcode, mnem): 114 global instDecode 115 return instDecode % { "className": mnem.capitalize(), 116 "opcode": opcode } 117 118 decode_block = ''' 119 { 120 const bool setCc = (bits(machInst, 20) == 1); 121 const uint32_t unrotated = bits(machInst, 7, 0); 122 const uint32_t rotation = (bits(machInst, 11, 8) << 1); 123 const bool rotC = (rotation != 0); 124 const uint32_t imm = rotate_imm(unrotated, rotation); 125 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 126 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 127 switch (OPCODE) { 128 ''' 129 decode_block += instCode(0x0, "and") 130 decode_block += instCode(0x1, "eor") 131 decode_block += instCode(0x2, "sub") 132 decode_block += instCode(0x3, "rsb") 133 decode_block += instCode(0x4, "add") 134 decode_block += instCode(0x5, "adc") 135 decode_block += instCode(0x6, "sbc") 136 decode_block += instCode(0x7, "rsc") 137 decode_block += instCode(0x8, "tst") 138 decode_block += instCode(0x9, "teq") 139 decode_block += instCode(0xa, "cmp") 140 decode_block += instCode(0xb, "cmn") 141 decode_block += instCode(0xc, "orr") 142 decode_block += instCode(0xd, "mov") 143 decode_block += instCode(0xe, "bic") 144 decode_block += instCode(0xf, "mvn") 145 decode_block += ''' 146 default: 147 return new Unknown(machInst); 148 } 149 } 150 ''' 151}}; 152