data.isa revision 7240
17139Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 27139Sgblack@eecs.umich.edu// All rights reserved 37139Sgblack@eecs.umich.edu// 47139Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 57139Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 67139Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 77139Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 87139Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 97139Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 107139Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 117139Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 127139Sgblack@eecs.umich.edu// 137139Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 147139Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 157139Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 167139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 177139Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 187139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 197139Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 207139Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 217139Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227139Sgblack@eecs.umich.edu// this software without specific prior written permission. 237139Sgblack@eecs.umich.edu// 247139Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 257139Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267139Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277139Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287139Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 297139Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317139Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327139Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 337139Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 347139Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357139Sgblack@eecs.umich.edu// 367139Sgblack@eecs.umich.edu// Authors: Gabe Black 377139Sgblack@eecs.umich.edu 387139Sgblack@eecs.umich.edudef format ArmDataProcReg() {{ 397188Sgblack@eecs.umich.edu pclr = ''' 407188Sgblack@eecs.umich.edu return new %(className)ssRegPclr(machInst, %(dest)s, 417188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, 427188Sgblack@eecs.umich.edu type); 437188Sgblack@eecs.umich.edu ''' 447139Sgblack@eecs.umich.edu instDecode = ''' 457139Sgblack@eecs.umich.edu case %(opcode)#x: 467139Sgblack@eecs.umich.edu if (immShift) { 477139Sgblack@eecs.umich.edu if (setCc) { 487188Sgblack@eecs.umich.edu if (%(dest)s == INTREG_PC) { 497188Sgblack@eecs.umich.edu %(pclr)s 507188Sgblack@eecs.umich.edu } else { 517188Sgblack@eecs.umich.edu return new %(className)sRegCc(machInst, %(dest)s, 527188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, type); 537188Sgblack@eecs.umich.edu } 547139Sgblack@eecs.umich.edu } else { 557146Sgblack@eecs.umich.edu return new %(className)sReg(machInst, %(dest)s, %(op1)s, 567141Sgblack@eecs.umich.edu rm, imm5, type); 577139Sgblack@eecs.umich.edu } 587139Sgblack@eecs.umich.edu } else { 597139Sgblack@eecs.umich.edu if (setCc) { 607146Sgblack@eecs.umich.edu return new %(className)sRegRegCc(machInst, %(dest)s, 617141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 627139Sgblack@eecs.umich.edu } else { 637146Sgblack@eecs.umich.edu return new %(className)sRegReg(machInst, %(dest)s, 647141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 657139Sgblack@eecs.umich.edu } 667139Sgblack@eecs.umich.edu } 677139Sgblack@eecs.umich.edu break; 687139Sgblack@eecs.umich.edu ''' 697139Sgblack@eecs.umich.edu 707188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 717188Sgblack@eecs.umich.edu global pclr 727188Sgblack@eecs.umich.edu if useDest: 737188Sgblack@eecs.umich.edu dest = "rd" 747188Sgblack@eecs.umich.edu else: 757188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 767188Sgblack@eecs.umich.edu if useOp1: 777188Sgblack@eecs.umich.edu op1 = "rn" 787188Sgblack@eecs.umich.edu else: 797188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 807188Sgblack@eecs.umich.edu global instDecode, pclrCode 817188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 827188Sgblack@eecs.umich.edu "opcode": opcode, 837188Sgblack@eecs.umich.edu "dest": dest, 847188Sgblack@eecs.umich.edu "op1": op1 } 857188Sgblack@eecs.umich.edu if useDest: 867188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 877188Sgblack@eecs.umich.edu else: 887188Sgblack@eecs.umich.edu substDict["pclr"] = "" 897188Sgblack@eecs.umich.edu return instDecode % substDict 907139Sgblack@eecs.umich.edu 917139Sgblack@eecs.umich.edu decode_block = ''' 927139Sgblack@eecs.umich.edu { 937139Sgblack@eecs.umich.edu const bool immShift = (bits(machInst, 4) == 0); 947139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 957139Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 967139Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 977139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 987139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 997139Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 1007139Sgblack@eecs.umich.edu const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 1017139Sgblack@eecs.umich.edu switch (OPCODE) { 1027139Sgblack@eecs.umich.edu ''' 1037139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 1047139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 1057139Sgblack@eecs.umich.edu decode_block += instCode(0x2, "sub") 1067139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 1077139Sgblack@eecs.umich.edu decode_block += instCode(0x4, "add") 1087139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 1097139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 1107139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 1117188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 1127188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 1137188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 1147188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 1157139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 1167188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 1177139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 1187188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 1197139Sgblack@eecs.umich.edu decode_block += ''' 1207139Sgblack@eecs.umich.edu default: 1217139Sgblack@eecs.umich.edu return new Unknown(machInst); 1227139Sgblack@eecs.umich.edu } 1237139Sgblack@eecs.umich.edu } 1247139Sgblack@eecs.umich.edu ''' 1257139Sgblack@eecs.umich.edu}}; 1267139Sgblack@eecs.umich.edu 1277210Sgblack@eecs.umich.edudef format ArmPackUnpackSatReverse() {{ 1287210Sgblack@eecs.umich.edu decode_block = ''' 1297210Sgblack@eecs.umich.edu { 1307210Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 1317210Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 19, 16); 1327210Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 1337210Sgblack@eecs.umich.edu if (bits(op2, 0) == 0) { 1347227Sgblack@eecs.umich.edu const IntRegIndex rn = 1357227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1367227Sgblack@eecs.umich.edu const IntRegIndex rd = 1377227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1387227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 1397227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 11, 7); 1407227Sgblack@eecs.umich.edu const ArmShiftType type = 1417227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1427210Sgblack@eecs.umich.edu if (op1 == 0) { 1437237Sgblack@eecs.umich.edu if (type) { 1447237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, (IntRegIndex)a, 1457237Sgblack@eecs.umich.edu rn, imm, type); 1467237Sgblack@eecs.umich.edu } else { 1477237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, (IntRegIndex)a, 1487237Sgblack@eecs.umich.edu rn, imm, type); 1497237Sgblack@eecs.umich.edu } 1507210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 1) { 1517227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 1527210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 3) { 1537227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 1547210Sgblack@eecs.umich.edu } 1557210Sgblack@eecs.umich.edu return new Unknown(machInst); 1567210Sgblack@eecs.umich.edu } 1577210Sgblack@eecs.umich.edu switch (op1) { 1587210Sgblack@eecs.umich.edu case 0x0: 1597240Sgblack@eecs.umich.edu { 1607235Sgblack@eecs.umich.edu const IntRegIndex rn = 1617235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1627235Sgblack@eecs.umich.edu const IntRegIndex rd = 1637235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1647235Sgblack@eecs.umich.edu const IntRegIndex rm = 1657235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1667240Sgblack@eecs.umich.edu if (op2 == 0x3) { 1677240Sgblack@eecs.umich.edu const uint32_t rotation = 1687240Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 1697240Sgblack@eecs.umich.edu if (a == 0xf) { 1707240Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 1717240Sgblack@eecs.umich.edu } else { 1727240Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 1737240Sgblack@eecs.umich.edu } 1747240Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 1757240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 1767210Sgblack@eecs.umich.edu } 1777210Sgblack@eecs.umich.edu } 1787210Sgblack@eecs.umich.edu break; 1797210Sgblack@eecs.umich.edu case 0x2: 1807210Sgblack@eecs.umich.edu if (op2 == 0x1) { 1817227Sgblack@eecs.umich.edu const IntRegIndex rn = 1827227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1837227Sgblack@eecs.umich.edu const IntRegIndex rd = 1847227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1857227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 1867227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 1877210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 1887235Sgblack@eecs.umich.edu const IntRegIndex rn = 1897235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1907235Sgblack@eecs.umich.edu const IntRegIndex rd = 1917235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1927235Sgblack@eecs.umich.edu const IntRegIndex rm = 1937235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1947235Sgblack@eecs.umich.edu const uint32_t rotation = 1957235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 1967210Sgblack@eecs.umich.edu if (a == 0xf) { 1977235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 1987210Sgblack@eecs.umich.edu } else { 1997235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 2007210Sgblack@eecs.umich.edu } 2017210Sgblack@eecs.umich.edu } 2027210Sgblack@eecs.umich.edu break; 2037210Sgblack@eecs.umich.edu case 0x3: 2047210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2057211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2067211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2077211Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 2087210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2097235Sgblack@eecs.umich.edu const IntRegIndex rn = 2107235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2117235Sgblack@eecs.umich.edu const IntRegIndex rd = 2127235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2137235Sgblack@eecs.umich.edu const IntRegIndex rm = 2147235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2157235Sgblack@eecs.umich.edu const uint32_t rotation = 2167235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2177210Sgblack@eecs.umich.edu if (a == 0xf) { 2187235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 2197210Sgblack@eecs.umich.edu } else { 2207235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 2217210Sgblack@eecs.umich.edu } 2227210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2237211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2247211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2257211Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 2267210Sgblack@eecs.umich.edu } 2277210Sgblack@eecs.umich.edu break; 2287210Sgblack@eecs.umich.edu case 0x4: 2297210Sgblack@eecs.umich.edu if (op2 == 0x3) { 2307235Sgblack@eecs.umich.edu const IntRegIndex rn = 2317235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2327235Sgblack@eecs.umich.edu const IntRegIndex rd = 2337235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2347235Sgblack@eecs.umich.edu const IntRegIndex rm = 2357235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2367235Sgblack@eecs.umich.edu const uint32_t rotation = 2377235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2387210Sgblack@eecs.umich.edu if (a == 0xf) { 2397235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 2407210Sgblack@eecs.umich.edu } else { 2417235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 2427210Sgblack@eecs.umich.edu } 2437210Sgblack@eecs.umich.edu } 2447210Sgblack@eecs.umich.edu break; 2457210Sgblack@eecs.umich.edu case 0x6: 2467210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2477227Sgblack@eecs.umich.edu const IntRegIndex rn = 2487227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2497227Sgblack@eecs.umich.edu const IntRegIndex rd = 2507227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2517227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2527227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 2537210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2547235Sgblack@eecs.umich.edu const IntRegIndex rn = 2557235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2567235Sgblack@eecs.umich.edu const IntRegIndex rd = 2577235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2587235Sgblack@eecs.umich.edu const IntRegIndex rm = 2597235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2607235Sgblack@eecs.umich.edu const uint32_t rotation = 2617235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2627210Sgblack@eecs.umich.edu if (a == 0xf) { 2637235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 2647210Sgblack@eecs.umich.edu } else { 2657235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 2667210Sgblack@eecs.umich.edu } 2677210Sgblack@eecs.umich.edu } 2687210Sgblack@eecs.umich.edu break; 2697210Sgblack@eecs.umich.edu case 0x7: 2707210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2717210Sgblack@eecs.umich.edu return new WarnUnimplemented("rbit", machInst); 2727210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2737235Sgblack@eecs.umich.edu const IntRegIndex rn = 2747235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2757235Sgblack@eecs.umich.edu const IntRegIndex rd = 2767235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2777235Sgblack@eecs.umich.edu const IntRegIndex rm = 2787235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2797235Sgblack@eecs.umich.edu const uint32_t rotation = 2807235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2817210Sgblack@eecs.umich.edu if (a == 0xf) { 2827235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 2837210Sgblack@eecs.umich.edu } else { 2847235Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 2857210Sgblack@eecs.umich.edu } 2867210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2877211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2887211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2897211Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 2907210Sgblack@eecs.umich.edu } 2917210Sgblack@eecs.umich.edu break; 2927210Sgblack@eecs.umich.edu } 2937210Sgblack@eecs.umich.edu return new Unknown(machInst); 2947210Sgblack@eecs.umich.edu } 2957210Sgblack@eecs.umich.edu ''' 2967210Sgblack@eecs.umich.edu}}; 2977210Sgblack@eecs.umich.edu 2987194Sgblack@eecs.umich.edudef format ArmParallelAddSubtract() {{ 2997194Sgblack@eecs.umich.edu decode_block=''' 3007194Sgblack@eecs.umich.edu { 3017194Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 3027194Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 3037194Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3047194Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3057194Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3067194Sgblack@eecs.umich.edu if (bits(machInst, 22) == 0) { 3077194Sgblack@eecs.umich.edu switch (op1) { 3087194Sgblack@eecs.umich.edu case 0x1: 3097194Sgblack@eecs.umich.edu switch (op2) { 3107194Sgblack@eecs.umich.edu case 0x0: 3117216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3127194Sgblack@eecs.umich.edu case 0x1: 3137224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); 3147194Sgblack@eecs.umich.edu case 0x2: 3157224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); 3167194Sgblack@eecs.umich.edu case 0x3: 3177218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); 3187194Sgblack@eecs.umich.edu case 0x4: 3197216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 3207194Sgblack@eecs.umich.edu case 0x7: 3217218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); 3227194Sgblack@eecs.umich.edu } 3237194Sgblack@eecs.umich.edu break; 3247194Sgblack@eecs.umich.edu case 0x2: 3257194Sgblack@eecs.umich.edu switch (op2) { 3267194Sgblack@eecs.umich.edu case 0x0: 3277194Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 3287194Sgblack@eecs.umich.edu case 0x1: 3297194Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 3307194Sgblack@eecs.umich.edu case 0x2: 3317194Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 3327194Sgblack@eecs.umich.edu case 0x3: 3337194Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 3347194Sgblack@eecs.umich.edu case 0x4: 3357194Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 3367194Sgblack@eecs.umich.edu case 0x7: 3377194Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 3387194Sgblack@eecs.umich.edu } 3397194Sgblack@eecs.umich.edu break; 3407194Sgblack@eecs.umich.edu case 0x3: 3417194Sgblack@eecs.umich.edu switch (op2) { 3427194Sgblack@eecs.umich.edu case 0x0: 3437231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 3447194Sgblack@eecs.umich.edu case 0x1: 3457231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 3467194Sgblack@eecs.umich.edu case 0x2: 3477231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 3487194Sgblack@eecs.umich.edu case 0x3: 3497231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 3507194Sgblack@eecs.umich.edu case 0x4: 3517231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 3527194Sgblack@eecs.umich.edu case 0x7: 3537231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 3547194Sgblack@eecs.umich.edu } 3557194Sgblack@eecs.umich.edu break; 3567194Sgblack@eecs.umich.edu } 3577194Sgblack@eecs.umich.edu } else { 3587194Sgblack@eecs.umich.edu switch (op1) { 3597194Sgblack@eecs.umich.edu case 0x1: 3607194Sgblack@eecs.umich.edu switch (op2) { 3617194Sgblack@eecs.umich.edu case 0x0: 3627222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3637194Sgblack@eecs.umich.edu case 0x1: 3647222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, rn, rm, 0, LSL); 3657194Sgblack@eecs.umich.edu case 0x2: 3667222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL); 3677194Sgblack@eecs.umich.edu case 0x3: 3687222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL); 3697194Sgblack@eecs.umich.edu case 0x4: 3707222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL); 3717194Sgblack@eecs.umich.edu case 0x7: 3727222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL); 3737194Sgblack@eecs.umich.edu } 3747194Sgblack@eecs.umich.edu break; 3757194Sgblack@eecs.umich.edu case 0x2: 3767194Sgblack@eecs.umich.edu switch (op2) { 3777194Sgblack@eecs.umich.edu case 0x0: 3787220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 3797194Sgblack@eecs.umich.edu case 0x1: 3807220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 3817194Sgblack@eecs.umich.edu case 0x2: 3827220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 3837194Sgblack@eecs.umich.edu case 0x3: 3847220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 3857194Sgblack@eecs.umich.edu case 0x4: 3867220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 3877194Sgblack@eecs.umich.edu case 0x7: 3887220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 3897194Sgblack@eecs.umich.edu } 3907194Sgblack@eecs.umich.edu break; 3917194Sgblack@eecs.umich.edu case 0x3: 3927194Sgblack@eecs.umich.edu switch (op2) { 3937194Sgblack@eecs.umich.edu case 0x0: 3947231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 3957194Sgblack@eecs.umich.edu case 0x1: 3967231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 3977194Sgblack@eecs.umich.edu case 0x2: 3987231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 3997194Sgblack@eecs.umich.edu case 0x3: 4007231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 4017194Sgblack@eecs.umich.edu case 0x4: 4027231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 4037194Sgblack@eecs.umich.edu case 0x7: 4047231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 4057194Sgblack@eecs.umich.edu } 4067194Sgblack@eecs.umich.edu break; 4077194Sgblack@eecs.umich.edu } 4087194Sgblack@eecs.umich.edu } 4097194Sgblack@eecs.umich.edu return new Unknown(machInst); 4107194Sgblack@eecs.umich.edu } 4117194Sgblack@eecs.umich.edu ''' 4127194Sgblack@eecs.umich.edu}}; 4137194Sgblack@eecs.umich.edu 4147139Sgblack@eecs.umich.edudef format ArmDataProcImm() {{ 4157188Sgblack@eecs.umich.edu pclr = ''' 4167188Sgblack@eecs.umich.edu return new %(className)ssImmPclr(machInst, %(dest)s, 4177188Sgblack@eecs.umich.edu %(op1)s, imm, false); 4187188Sgblack@eecs.umich.edu ''' 4197188Sgblack@eecs.umich.edu adr = ''' 4207188Sgblack@eecs.umich.edu return new AdrImm(machInst, %(dest)s, %(add)s, 4217188Sgblack@eecs.umich.edu imm, false); 4227188Sgblack@eecs.umich.edu ''' 4237139Sgblack@eecs.umich.edu instDecode = ''' 4247188Sgblack@eecs.umich.edu case %(opcode)#x: 4257139Sgblack@eecs.umich.edu if (setCc) { 4267188Sgblack@eecs.umich.edu if (%(pclrInst)s && %(dest)s == INTREG_PC) { 4277188Sgblack@eecs.umich.edu %(pclr)s 4287188Sgblack@eecs.umich.edu } else { 4297188Sgblack@eecs.umich.edu return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 4307188Sgblack@eecs.umich.edu imm, rotC); 4317188Sgblack@eecs.umich.edu } 4327139Sgblack@eecs.umich.edu } else { 4337188Sgblack@eecs.umich.edu if (%(adrInst)s && %(op1)s == INTREG_PC) { 4347188Sgblack@eecs.umich.edu %(adr)s 4357188Sgblack@eecs.umich.edu } else { 4367188Sgblack@eecs.umich.edu return new %(className)sImm(machInst, %(dest)s, %(op1)s, 4377188Sgblack@eecs.umich.edu imm, rotC); 4387188Sgblack@eecs.umich.edu } 4397139Sgblack@eecs.umich.edu } 4407139Sgblack@eecs.umich.edu break; 4417139Sgblack@eecs.umich.edu ''' 4427139Sgblack@eecs.umich.edu 4437188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 4447188Sgblack@eecs.umich.edu global instDecode, pclr, adr 4457188Sgblack@eecs.umich.edu if useDest: 4467188Sgblack@eecs.umich.edu dest = "rd" 4477188Sgblack@eecs.umich.edu else: 4487188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 4497188Sgblack@eecs.umich.edu if useOp1: 4507188Sgblack@eecs.umich.edu op1 = "rn" 4517188Sgblack@eecs.umich.edu else: 4527188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 4537188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 4547188Sgblack@eecs.umich.edu "opcode": opcode, 4557188Sgblack@eecs.umich.edu "dest": dest, 4567188Sgblack@eecs.umich.edu "op1": op1, 4577188Sgblack@eecs.umich.edu "adr": "", 4587188Sgblack@eecs.umich.edu "adrInst": "false" } 4597188Sgblack@eecs.umich.edu if useDest: 4607188Sgblack@eecs.umich.edu substDict["pclrInst"] = "true" 4617188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 4627188Sgblack@eecs.umich.edu else: 4637188Sgblack@eecs.umich.edu substDict["pclrInst"] = "false" 4647188Sgblack@eecs.umich.edu substDict["pclr"] = "" 4657188Sgblack@eecs.umich.edu return instDecode % substDict 4667185Sgblack@eecs.umich.edu 4677188Sgblack@eecs.umich.edu def adrCode(opcode, mnem, add="1"): 4687188Sgblack@eecs.umich.edu global instDecode, pclr, adr 4697188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 4707188Sgblack@eecs.umich.edu "opcode": opcode, 4717188Sgblack@eecs.umich.edu "dest": "rd", 4727188Sgblack@eecs.umich.edu "op1": "rn", 4737188Sgblack@eecs.umich.edu "add": add, 4747188Sgblack@eecs.umich.edu "pclrInst": "true", 4757188Sgblack@eecs.umich.edu "adrInst": "true" } 4767188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 4777188Sgblack@eecs.umich.edu substDict["adr"] = adr % substDict 4787188Sgblack@eecs.umich.edu return instDecode % substDict 4797139Sgblack@eecs.umich.edu 4807139Sgblack@eecs.umich.edu decode_block = ''' 4817139Sgblack@eecs.umich.edu { 4827139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 4837139Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 4847139Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 4857139Sgblack@eecs.umich.edu const bool rotC = (rotation != 0); 4867139Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 4877139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 4887139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 4897139Sgblack@eecs.umich.edu switch (OPCODE) { 4907139Sgblack@eecs.umich.edu ''' 4917139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 4927139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 4937185Sgblack@eecs.umich.edu decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 4947139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 4957185Sgblack@eecs.umich.edu decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 4967139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 4977139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 4987139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 4997188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 5007188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 5017188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 5027188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 5037139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 5047188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 5057139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 5067188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 5077139Sgblack@eecs.umich.edu decode_block += ''' 5087139Sgblack@eecs.umich.edu default: 5097139Sgblack@eecs.umich.edu return new Unknown(machInst); 5107139Sgblack@eecs.umich.edu } 5117139Sgblack@eecs.umich.edu } 5127139Sgblack@eecs.umich.edu ''' 5137139Sgblack@eecs.umich.edu}}; 5147141Sgblack@eecs.umich.edu 5157195Sgblack@eecs.umich.edudef format ArmSatAddSub() {{ 5167195Sgblack@eecs.umich.edu decode_block = ''' 5177195Sgblack@eecs.umich.edu { 5187195Sgblack@eecs.umich.edu IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5197195Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 5207195Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5217195Sgblack@eecs.umich.edu switch (OPCODE) { 5227195Sgblack@eecs.umich.edu case 0x8: 5237195Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 5247195Sgblack@eecs.umich.edu case 0x9: 5257195Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 5267195Sgblack@eecs.umich.edu case 0xa: 5277195Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 5287195Sgblack@eecs.umich.edu case 0xb: 5297195Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 5307195Sgblack@eecs.umich.edu default: 5317195Sgblack@eecs.umich.edu return new Unknown(machInst); 5327195Sgblack@eecs.umich.edu } 5337195Sgblack@eecs.umich.edu } 5347195Sgblack@eecs.umich.edu ''' 5357195Sgblack@eecs.umich.edu}}; 5367195Sgblack@eecs.umich.edu 5377213Sgblack@eecs.umich.edudef format Thumb32DataProcReg() {{ 5387213Sgblack@eecs.umich.edu decode_block = ''' 5397213Sgblack@eecs.umich.edu { 5407213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 23, 20); 5417213Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5427213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 4); 5437213Sgblack@eecs.umich.edu if (bits(op1, 3) != 1) { 5447213Sgblack@eecs.umich.edu if (op2 == 0) { 5457213Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 5467213Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5477213Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 5487213Sgblack@eecs.umich.edu case 0x0: 5497213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5507213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5517213Sgblack@eecs.umich.edu case 0x1: 5527213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5537213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5547213Sgblack@eecs.umich.edu case 0x2: 5557213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5567213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5577213Sgblack@eecs.umich.edu case 0x3: 5587213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5597213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5607213Sgblack@eecs.umich.edu case 0x4: 5617213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5627213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 5637213Sgblack@eecs.umich.edu case 0x5: 5647213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5657213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 5667213Sgblack@eecs.umich.edu case 0x6: 5677213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5687213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 5697213Sgblack@eecs.umich.edu case 0x7: 5707213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5717213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 5727213Sgblack@eecs.umich.edu } 5737213Sgblack@eecs.umich.edu } 5747235Sgblack@eecs.umich.edu { 5757235Sgblack@eecs.umich.edu const IntRegIndex rd = 5767235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 5777235Sgblack@eecs.umich.edu const IntRegIndex rm = 5787235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5797235Sgblack@eecs.umich.edu const uint32_t rotation = 5807235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 5, 4) << 3; 5817235Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 5827235Sgblack@eecs.umich.edu case 0x0: 5837235Sgblack@eecs.umich.edu if (rn == 0xf) { 5847235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 5857235Sgblack@eecs.umich.edu } else { 5867235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 5877235Sgblack@eecs.umich.edu } 5887235Sgblack@eecs.umich.edu case 0x1: 5897235Sgblack@eecs.umich.edu if (rn == 0xf) { 5907235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 5917235Sgblack@eecs.umich.edu } else { 5927235Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 5937235Sgblack@eecs.umich.edu } 5947235Sgblack@eecs.umich.edu case 0x2: 5957235Sgblack@eecs.umich.edu if (rn == 0xf) { 5967235Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 5977235Sgblack@eecs.umich.edu } else { 5987235Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 5997235Sgblack@eecs.umich.edu } 6007235Sgblack@eecs.umich.edu case 0x3: 6017235Sgblack@eecs.umich.edu if (rn == 0xf) { 6027235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 6037235Sgblack@eecs.umich.edu } else { 6047235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 6057235Sgblack@eecs.umich.edu } 6067235Sgblack@eecs.umich.edu case 0x4: 6077235Sgblack@eecs.umich.edu if (rn == 0xf) { 6087235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 6097235Sgblack@eecs.umich.edu } else { 6107235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 6117235Sgblack@eecs.umich.edu } 6127235Sgblack@eecs.umich.edu case 0x5: 6137235Sgblack@eecs.umich.edu if (rn == 0xf) { 6147235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 6157235Sgblack@eecs.umich.edu } else { 6167235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 6177235Sgblack@eecs.umich.edu } 6187235Sgblack@eecs.umich.edu default: 6197235Sgblack@eecs.umich.edu return new Unknown(machInst); 6207213Sgblack@eecs.umich.edu } 6217213Sgblack@eecs.umich.edu } 6227213Sgblack@eecs.umich.edu } else { 6237213Sgblack@eecs.umich.edu if (bits(op2, 3) == 0) { 6247220Sgblack@eecs.umich.edu const IntRegIndex rd = 6257220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6267220Sgblack@eecs.umich.edu const IntRegIndex rm = 6277220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6287213Sgblack@eecs.umich.edu if (bits(op2, 2) == 0x0) { 6297213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 6307213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 6317213Sgblack@eecs.umich.edu switch (op2) { 6327213Sgblack@eecs.umich.edu case 0x0: 6337213Sgblack@eecs.umich.edu switch (op1) { 6347213Sgblack@eecs.umich.edu case 0x1: 6357216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, 6367216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6377213Sgblack@eecs.umich.edu case 0x2: 6387224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, 6397224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6407213Sgblack@eecs.umich.edu case 0x6: 6417224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, 6427224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6437213Sgblack@eecs.umich.edu case 0x5: 6447218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, 6457218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6467213Sgblack@eecs.umich.edu case 0x0: 6477216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, 6487216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6497213Sgblack@eecs.umich.edu case 0x4: 6507218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, 6517218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6527213Sgblack@eecs.umich.edu } 6537213Sgblack@eecs.umich.edu break; 6547213Sgblack@eecs.umich.edu case 0x1: 6557216Sgblack@eecs.umich.edu switch (op1) { 6567216Sgblack@eecs.umich.edu case 0x1: 6577216Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 6587216Sgblack@eecs.umich.edu case 0x2: 6597216Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 6607216Sgblack@eecs.umich.edu case 0x6: 6617216Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 6627216Sgblack@eecs.umich.edu case 0x5: 6637216Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 6647216Sgblack@eecs.umich.edu case 0x0: 6657216Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 6667216Sgblack@eecs.umich.edu case 0x4: 6677216Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 6687213Sgblack@eecs.umich.edu } 6697213Sgblack@eecs.umich.edu break; 6707213Sgblack@eecs.umich.edu case 0x2: 6717213Sgblack@eecs.umich.edu switch (op1) { 6727213Sgblack@eecs.umich.edu case 0x1: 6737231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 6747213Sgblack@eecs.umich.edu case 0x2: 6757231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 6767213Sgblack@eecs.umich.edu case 0x6: 6777231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 6787213Sgblack@eecs.umich.edu case 0x5: 6797231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 6807213Sgblack@eecs.umich.edu case 0x0: 6817231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 6827213Sgblack@eecs.umich.edu case 0x4: 6837231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 6847213Sgblack@eecs.umich.edu } 6857213Sgblack@eecs.umich.edu break; 6867213Sgblack@eecs.umich.edu } 6877213Sgblack@eecs.umich.edu } else { 6887213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 6897213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 6907213Sgblack@eecs.umich.edu switch (op2) { 6917213Sgblack@eecs.umich.edu case 0x0: 6927213Sgblack@eecs.umich.edu switch (op1) { 6937213Sgblack@eecs.umich.edu case 0x1: 6947222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, 6957222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6967213Sgblack@eecs.umich.edu case 0x2: 6977222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, 6987222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6997213Sgblack@eecs.umich.edu case 0x6: 7007222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, 7017222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7027213Sgblack@eecs.umich.edu case 0x5: 7037222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, 7047222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7057213Sgblack@eecs.umich.edu case 0x0: 7067222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, 7077222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7087213Sgblack@eecs.umich.edu case 0x4: 7097222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, 7107222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7117213Sgblack@eecs.umich.edu } 7127213Sgblack@eecs.umich.edu break; 7137213Sgblack@eecs.umich.edu case 0x1: 7147213Sgblack@eecs.umich.edu switch (op1) { 7157213Sgblack@eecs.umich.edu case 0x1: 7167220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 7177213Sgblack@eecs.umich.edu case 0x2: 7187220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 7197213Sgblack@eecs.umich.edu case 0x6: 7207220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 7217213Sgblack@eecs.umich.edu case 0x5: 7227220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 7237213Sgblack@eecs.umich.edu case 0x0: 7247220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 7257213Sgblack@eecs.umich.edu case 0x4: 7267220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 7277213Sgblack@eecs.umich.edu } 7287213Sgblack@eecs.umich.edu break; 7297213Sgblack@eecs.umich.edu case 0x2: 7307213Sgblack@eecs.umich.edu switch (op1) { 7317213Sgblack@eecs.umich.edu case 0x1: 7327231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 7337213Sgblack@eecs.umich.edu case 0x2: 7347231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 7357213Sgblack@eecs.umich.edu case 0x6: 7367231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 7377213Sgblack@eecs.umich.edu case 0x5: 7387231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 7397213Sgblack@eecs.umich.edu case 0x0: 7407231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 7417213Sgblack@eecs.umich.edu case 0x4: 7427231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 7437213Sgblack@eecs.umich.edu } 7447213Sgblack@eecs.umich.edu break; 7457213Sgblack@eecs.umich.edu } 7467213Sgblack@eecs.umich.edu } 7477213Sgblack@eecs.umich.edu } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 7487213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 7497213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7507240Sgblack@eecs.umich.edu const IntRegIndex rd = 7517240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 7527240Sgblack@eecs.umich.edu const IntRegIndex rm = 7537240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 7547213Sgblack@eecs.umich.edu switch (op1) { 7557213Sgblack@eecs.umich.edu case 0x0: 7567240Sgblack@eecs.umich.edu switch (op2) { 7577240Sgblack@eecs.umich.edu case 0x0: 7587240Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, 7597240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7607240Sgblack@eecs.umich.edu case 0x1: 7617240Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, 7627240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7637240Sgblack@eecs.umich.edu case 0x2: 7647240Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, 7657240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7667240Sgblack@eecs.umich.edu case 0x3: 7677240Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, 7687240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7697213Sgblack@eecs.umich.edu } 7707213Sgblack@eecs.umich.edu break; 7717213Sgblack@eecs.umich.edu case 0x1: 7727240Sgblack@eecs.umich.edu switch (op2) { 7737240Sgblack@eecs.umich.edu case 0x0: 7747240Sgblack@eecs.umich.edu return new Rev(machInst, rd, rn); 7757240Sgblack@eecs.umich.edu case 0x1: 7767240Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rn); 7777240Sgblack@eecs.umich.edu case 0x2: 7787240Sgblack@eecs.umich.edu return new WarnUnimplemented("rbit", machInst); 7797240Sgblack@eecs.umich.edu case 0x3: 7807240Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rn); 7817213Sgblack@eecs.umich.edu } 7827213Sgblack@eecs.umich.edu break; 7837213Sgblack@eecs.umich.edu case 0x2: 7847213Sgblack@eecs.umich.edu if (op2 == 0) { 7857240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 7867213Sgblack@eecs.umich.edu } 7877213Sgblack@eecs.umich.edu break; 7887213Sgblack@eecs.umich.edu case 0x3: 7897213Sgblack@eecs.umich.edu if (op2 == 0) { 7907213Sgblack@eecs.umich.edu return new WarnUnimplemented("clz", machInst); 7917213Sgblack@eecs.umich.edu } 7927213Sgblack@eecs.umich.edu } 7937213Sgblack@eecs.umich.edu } 7947213Sgblack@eecs.umich.edu return new Unknown(machInst); 7957213Sgblack@eecs.umich.edu } 7967213Sgblack@eecs.umich.edu } 7977213Sgblack@eecs.umich.edu ''' 7987213Sgblack@eecs.umich.edu}}; 7997213Sgblack@eecs.umich.edu 8007141Sgblack@eecs.umich.edudef format Thumb16ShiftAddSubMoveCmp() {{ 8017141Sgblack@eecs.umich.edu decode_block = ''' 8027141Sgblack@eecs.umich.edu { 8037141Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 10, 6); 8047141Sgblack@eecs.umich.edu const uint32_t imm3 = bits(machInst, 8, 6); 8057141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 8067141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8077141Sgblack@eecs.umich.edu const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 8087141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8097141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 8107141Sgblack@eecs.umich.edu switch (bits(machInst, 13, 11)) { 8117141Sgblack@eecs.umich.edu case 0x0: // lsl 8127183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 8137141Sgblack@eecs.umich.edu case 0x1: // lsr 8147183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 8157141Sgblack@eecs.umich.edu case 0x2: // asr 8167183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 8177141Sgblack@eecs.umich.edu case 0x3: 8187141Sgblack@eecs.umich.edu switch (bits(machInst, 10, 9)) { 8197141Sgblack@eecs.umich.edu case 0x0: 8207183Sgblack@eecs.umich.edu return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 8217141Sgblack@eecs.umich.edu case 0x1: 8227183Sgblack@eecs.umich.edu return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 8237141Sgblack@eecs.umich.edu case 0x2: 8247183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd, rn, imm3, true); 8257141Sgblack@eecs.umich.edu case 0x3: 8267183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd, rn, imm3, true); 8277141Sgblack@eecs.umich.edu } 8287141Sgblack@eecs.umich.edu case 0x4: 8297183Sgblack@eecs.umich.edu return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 8307141Sgblack@eecs.umich.edu case 0x5: 8317146Sgblack@eecs.umich.edu return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 8327141Sgblack@eecs.umich.edu case 0x6: 8337183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd8, rd8, imm8, true); 8347141Sgblack@eecs.umich.edu case 0x7: 8357183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd8, rd8, imm8, true); 8367141Sgblack@eecs.umich.edu } 8377141Sgblack@eecs.umich.edu } 8387141Sgblack@eecs.umich.edu ''' 8397141Sgblack@eecs.umich.edu}}; 8407141Sgblack@eecs.umich.edu 8417141Sgblack@eecs.umich.edudef format Thumb16DataProcessing() {{ 8427141Sgblack@eecs.umich.edu decode_block = ''' 8437141Sgblack@eecs.umich.edu { 8447141Sgblack@eecs.umich.edu const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8457141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8467141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 6)) { 8477141Sgblack@eecs.umich.edu case 0x0: 8487183Sgblack@eecs.umich.edu return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 8497141Sgblack@eecs.umich.edu case 0x1: 8507183Sgblack@eecs.umich.edu return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 8517141Sgblack@eecs.umich.edu case 0x2: //lsl 8527183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL); 8537141Sgblack@eecs.umich.edu case 0x3: //lsr 8547183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR); 8557141Sgblack@eecs.umich.edu case 0x4: //asr 8567183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR); 8577141Sgblack@eecs.umich.edu case 0x5: 8587183Sgblack@eecs.umich.edu return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 8597141Sgblack@eecs.umich.edu case 0x6: 8607183Sgblack@eecs.umich.edu return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 8617141Sgblack@eecs.umich.edu case 0x7: // ror 8627183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR); 8637141Sgblack@eecs.umich.edu case 0x8: 8647183Sgblack@eecs.umich.edu return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 8657141Sgblack@eecs.umich.edu case 0x9: 8667183Sgblack@eecs.umich.edu return new RsbImmCc(machInst, rdn, rm, 0, true); 8677141Sgblack@eecs.umich.edu case 0xa: 8687183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 8697141Sgblack@eecs.umich.edu case 0xb: 8707183Sgblack@eecs.umich.edu return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 8717141Sgblack@eecs.umich.edu case 0xc: 8727183Sgblack@eecs.umich.edu return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 8737141Sgblack@eecs.umich.edu case 0xd: 8747183Sgblack@eecs.umich.edu return new MulCc(machInst, rdn, rm, rdn); 8757141Sgblack@eecs.umich.edu case 0xe: 8767183Sgblack@eecs.umich.edu return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 8777141Sgblack@eecs.umich.edu case 0xf: 8787183Sgblack@eecs.umich.edu return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 8797141Sgblack@eecs.umich.edu } 8807141Sgblack@eecs.umich.edu } 8817141Sgblack@eecs.umich.edu ''' 8827141Sgblack@eecs.umich.edu}}; 8837141Sgblack@eecs.umich.edu 8847141Sgblack@eecs.umich.edudef format Thumb16SpecDataAndBx() {{ 8857141Sgblack@eecs.umich.edu decode_block = ''' 8867141Sgblack@eecs.umich.edu { 8877141Sgblack@eecs.umich.edu const IntRegIndex rdn = 8887141Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 8897141Sgblack@eecs.umich.edu (bits(machInst, 7) << 3)); 8907141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 8917141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 8)) { 8927141Sgblack@eecs.umich.edu case 0x0: 8937146Sgblack@eecs.umich.edu return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 8947141Sgblack@eecs.umich.edu case 0x1: 8957183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 8967141Sgblack@eecs.umich.edu case 0x2: 8977146Sgblack@eecs.umich.edu return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 8987141Sgblack@eecs.umich.edu case 0x3: 8997154Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 9007154Sgblack@eecs.umich.edu return new BxReg(machInst, 9017154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 9027154Sgblack@eecs.umich.edu COND_UC); 9037154Sgblack@eecs.umich.edu } else { 9047154Sgblack@eecs.umich.edu return new BlxReg(machInst, 9057154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 9067154Sgblack@eecs.umich.edu COND_UC); 9077154Sgblack@eecs.umich.edu } 9087141Sgblack@eecs.umich.edu } 9097141Sgblack@eecs.umich.edu } 9107141Sgblack@eecs.umich.edu ''' 9117141Sgblack@eecs.umich.edu}}; 9127141Sgblack@eecs.umich.edu 9137141Sgblack@eecs.umich.edudef format Thumb16Adr() {{ 9147141Sgblack@eecs.umich.edu decode_block = ''' 9157141Sgblack@eecs.umich.edu { 9167141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 9177141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 9187185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 9197141Sgblack@eecs.umich.edu } 9207141Sgblack@eecs.umich.edu ''' 9217141Sgblack@eecs.umich.edu}}; 9227141Sgblack@eecs.umich.edu 9237141Sgblack@eecs.umich.edudef format Thumb16AddSp() {{ 9247141Sgblack@eecs.umich.edu decode_block = ''' 9257141Sgblack@eecs.umich.edu { 9267141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 9277141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 9287146Sgblack@eecs.umich.edu return new AddImm(machInst, rd, INTREG_SP, imm8, true); 9297141Sgblack@eecs.umich.edu } 9307141Sgblack@eecs.umich.edu ''' 9317141Sgblack@eecs.umich.edu}}; 9327141Sgblack@eecs.umich.edu 9337141Sgblack@eecs.umich.edudef format Thumb16Misc() {{ 9347141Sgblack@eecs.umich.edu decode_block = ''' 9357141Sgblack@eecs.umich.edu { 9367141Sgblack@eecs.umich.edu switch (bits(machInst, 11, 8)) { 9377141Sgblack@eecs.umich.edu case 0x0: 9387141Sgblack@eecs.umich.edu if (bits(machInst, 7)) { 9397146Sgblack@eecs.umich.edu return new SubImm(machInst, INTREG_SP, INTREG_SP, 9407141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 9417141Sgblack@eecs.umich.edu } else { 9427146Sgblack@eecs.umich.edu return new AddImm(machInst, INTREG_SP, INTREG_SP, 9437141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 9447141Sgblack@eecs.umich.edu } 9457141Sgblack@eecs.umich.edu case 0x1: 9467154Sgblack@eecs.umich.edu return new Cbz(machInst, 9477154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 9487154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 9497154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 9507141Sgblack@eecs.umich.edu case 0x2: 9517235Sgblack@eecs.umich.edu { 9527235Sgblack@eecs.umich.edu const IntRegIndex rd = 9537235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 9547235Sgblack@eecs.umich.edu const IntRegIndex rm = 9557235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 9567235Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 9577235Sgblack@eecs.umich.edu case 0x0: 9587235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, 0, rm); 9597235Sgblack@eecs.umich.edu case 0x1: 9607235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, 0, rm); 9617235Sgblack@eecs.umich.edu case 0x2: 9627235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, 0, rm); 9637235Sgblack@eecs.umich.edu case 0x3: 9647235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, 0, rm); 9657235Sgblack@eecs.umich.edu } 9667141Sgblack@eecs.umich.edu } 9677141Sgblack@eecs.umich.edu case 0x3: 9687154Sgblack@eecs.umich.edu return new Cbz(machInst, 9697154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 9707154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 9717154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 9727141Sgblack@eecs.umich.edu case 0x4: 9737141Sgblack@eecs.umich.edu case 0x5: 9747201Sgblack@eecs.umich.edu { 9757201Sgblack@eecs.umich.edu const uint32_t m = bits(machInst, 8); 9767201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 9777201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, false, false, false, 9787201Sgblack@eecs.umich.edu true, false, regList); 9797201Sgblack@eecs.umich.edu } 9807141Sgblack@eecs.umich.edu case 0x6: 9817141Sgblack@eecs.umich.edu { 9827141Sgblack@eecs.umich.edu const uint32_t opBits = bits(machInst, 7, 5); 9837141Sgblack@eecs.umich.edu if (opBits == 2) { 9847141Sgblack@eecs.umich.edu return new WarnUnimplemented("setend", machInst); 9857141Sgblack@eecs.umich.edu } else if (opBits == 3) { 9867141Sgblack@eecs.umich.edu return new WarnUnimplemented("cps", machInst); 9877141Sgblack@eecs.umich.edu } 9887141Sgblack@eecs.umich.edu } 9897141Sgblack@eecs.umich.edu case 0x9: 9907154Sgblack@eecs.umich.edu return new Cbnz(machInst, 9917154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 9927154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 9937154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 9947141Sgblack@eecs.umich.edu case 0xa: 9957212Sgblack@eecs.umich.edu { 9967212Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 9977212Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 9987212Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 9997212Sgblack@eecs.umich.edu case 0x0: 10007212Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 10017212Sgblack@eecs.umich.edu case 0x1: 10027212Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 10037212Sgblack@eecs.umich.edu case 0x3: 10047212Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 10057212Sgblack@eecs.umich.edu default: 10067212Sgblack@eecs.umich.edu break; 10077212Sgblack@eecs.umich.edu } 10087141Sgblack@eecs.umich.edu } 10097141Sgblack@eecs.umich.edu break; 10107141Sgblack@eecs.umich.edu case 0xb: 10117154Sgblack@eecs.umich.edu return new Cbnz(machInst, 10127154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10137154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10147154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10157141Sgblack@eecs.umich.edu case 0xc: 10167141Sgblack@eecs.umich.edu case 0xd: 10177201Sgblack@eecs.umich.edu { 10187201Sgblack@eecs.umich.edu const uint32_t p = bits(machInst, 8); 10197201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 10207201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, true, true, false, 10217201Sgblack@eecs.umich.edu true, true, regList); 10227201Sgblack@eecs.umich.edu } 10237141Sgblack@eecs.umich.edu case 0xe: 10247141Sgblack@eecs.umich.edu return new WarnUnimplemented("bkpt", machInst); 10257141Sgblack@eecs.umich.edu case 0xf: 10267141Sgblack@eecs.umich.edu if (bits(machInst, 3, 0) != 0) 10277141Sgblack@eecs.umich.edu return new WarnUnimplemented("it", machInst); 10287141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 4)) { 10297141Sgblack@eecs.umich.edu case 0x0: 10307141Sgblack@eecs.umich.edu return new WarnUnimplemented("nop", machInst); 10317141Sgblack@eecs.umich.edu case 0x1: 10327141Sgblack@eecs.umich.edu return new WarnUnimplemented("yield", machInst); 10337141Sgblack@eecs.umich.edu case 0x2: 10347141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfe", machInst); 10357141Sgblack@eecs.umich.edu case 0x3: 10367141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfi", machInst); 10377141Sgblack@eecs.umich.edu case 0x4: 10387141Sgblack@eecs.umich.edu return new WarnUnimplemented("sev", machInst); 10397141Sgblack@eecs.umich.edu default: 10407141Sgblack@eecs.umich.edu return new WarnUnimplemented("unallocated_hint", machInst); 10417141Sgblack@eecs.umich.edu } 10427141Sgblack@eecs.umich.edu default: 10437141Sgblack@eecs.umich.edu break; 10447141Sgblack@eecs.umich.edu } 10457141Sgblack@eecs.umich.edu return new Unknown(machInst); 10467141Sgblack@eecs.umich.edu } 10477141Sgblack@eecs.umich.edu ''' 10487141Sgblack@eecs.umich.edu}}; 10497141Sgblack@eecs.umich.edu 10507141Sgblack@eecs.umich.edudef format Thumb32DataProcModImm() {{ 10517141Sgblack@eecs.umich.edu 10527141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 10537141Sgblack@eecs.umich.edu return ''' 10547141Sgblack@eecs.umich.edu if (s) { 10557146Sgblack@eecs.umich.edu return new %(mnem)sImmCc(machInst, %(dest)s, 10567183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 10577141Sgblack@eecs.umich.edu } else { 10587146Sgblack@eecs.umich.edu return new %(mnem)sImm(machInst, %(dest)s, 10597183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 10607141Sgblack@eecs.umich.edu } 10617141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 10627141Sgblack@eecs.umich.edu 10637141Sgblack@eecs.umich.edu decode_block = ''' 10647141Sgblack@eecs.umich.edu { 10657141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 10667141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 10677141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 10687141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 10697141Sgblack@eecs.umich.edu const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 10707141Sgblack@eecs.umich.edu bits(machInst, 14, 12); 10717183Sgblack@eecs.umich.edu const bool rotC = ctrlImm > 3; 10727141Sgblack@eecs.umich.edu const uint32_t dataImm = bits(machInst, 7, 0); 10737141Sgblack@eecs.umich.edu const uint32_t imm = modified_imm(ctrlImm, dataImm); 10747141Sgblack@eecs.umich.edu switch (op) { 10757141Sgblack@eecs.umich.edu case 0x0: 10767141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 10777141Sgblack@eecs.umich.edu %(tst)s 10787141Sgblack@eecs.umich.edu } else { 10797141Sgblack@eecs.umich.edu %(and)s 10807141Sgblack@eecs.umich.edu } 10817141Sgblack@eecs.umich.edu case 0x1: 10827141Sgblack@eecs.umich.edu %(bic)s 10837141Sgblack@eecs.umich.edu case 0x2: 10847141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 10857141Sgblack@eecs.umich.edu %(mov)s 10867141Sgblack@eecs.umich.edu } else { 10877141Sgblack@eecs.umich.edu %(orr)s 10887141Sgblack@eecs.umich.edu } 10897141Sgblack@eecs.umich.edu case 0x3: 10907141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 10917141Sgblack@eecs.umich.edu %(mvn)s 10927141Sgblack@eecs.umich.edu } else { 10937141Sgblack@eecs.umich.edu %(orn)s 10947141Sgblack@eecs.umich.edu } 10957141Sgblack@eecs.umich.edu case 0x4: 10967141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 10977141Sgblack@eecs.umich.edu %(teq)s 10987141Sgblack@eecs.umich.edu } else { 10997141Sgblack@eecs.umich.edu %(eor)s 11007141Sgblack@eecs.umich.edu } 11017141Sgblack@eecs.umich.edu case 0x8: 11027141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11037141Sgblack@eecs.umich.edu %(cmn)s 11047141Sgblack@eecs.umich.edu } else { 11057141Sgblack@eecs.umich.edu %(add)s 11067141Sgblack@eecs.umich.edu } 11077141Sgblack@eecs.umich.edu case 0xa: 11087141Sgblack@eecs.umich.edu %(adc)s 11097141Sgblack@eecs.umich.edu case 0xb: 11107141Sgblack@eecs.umich.edu %(sbc)s 11117141Sgblack@eecs.umich.edu case 0xd: 11127141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11137141Sgblack@eecs.umich.edu %(cmp)s 11147141Sgblack@eecs.umich.edu } else { 11157141Sgblack@eecs.umich.edu %(sub)s 11167141Sgblack@eecs.umich.edu } 11177141Sgblack@eecs.umich.edu case 0xe: 11187141Sgblack@eecs.umich.edu %(rsb)s 11197141Sgblack@eecs.umich.edu default: 11207141Sgblack@eecs.umich.edu return new Unknown(machInst); 11217141Sgblack@eecs.umich.edu } 11227141Sgblack@eecs.umich.edu } 11237141Sgblack@eecs.umich.edu ''' % { 11247141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 11257141Sgblack@eecs.umich.edu "and" : decInst("And"), 11267141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 11277141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 11287141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 11297141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 11307141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 11317141Sgblack@eecs.umich.edu "teq" : decInst("Teq", dest="INTREG_ZERO"), 11327141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 11337141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 11347141Sgblack@eecs.umich.edu "add" : decInst("Add"), 11357141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 11367141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 11377141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 11387141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 11397141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 11407141Sgblack@eecs.umich.edu } 11417141Sgblack@eecs.umich.edu}}; 11427141Sgblack@eecs.umich.edu 11437157Sgblack@eecs.umich.edudef format Thumb32DataProcPlainBin() {{ 11447157Sgblack@eecs.umich.edu decode_block = ''' 11457157Sgblack@eecs.umich.edu { 11467157Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 20); 11477157Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 11487157Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 11497157Sgblack@eecs.umich.edu switch (op) { 11507157Sgblack@eecs.umich.edu case 0x0: 11517157Sgblack@eecs.umich.edu { 11527157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 11537157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 11547157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 11557185Sgblack@eecs.umich.edu if (rn == 0xf) { 11567185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, 11577185Sgblack@eecs.umich.edu imm, false); 11587185Sgblack@eecs.umich.edu } else { 11597185Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm, true); 11607185Sgblack@eecs.umich.edu } 11617157Sgblack@eecs.umich.edu } 11627157Sgblack@eecs.umich.edu case 0x4: 11637157Sgblack@eecs.umich.edu { 11647157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 11657157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 11667157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 11677157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 11687157Sgblack@eecs.umich.edu return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 11697157Sgblack@eecs.umich.edu } 11707157Sgblack@eecs.umich.edu case 0xa: 11717157Sgblack@eecs.umich.edu { 11727157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 11737157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 11747157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 11757185Sgblack@eecs.umich.edu if (rn == 0xf) { 11767185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)0, 11777185Sgblack@eecs.umich.edu imm, false); 11787185Sgblack@eecs.umich.edu } else { 11797185Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm, true); 11807185Sgblack@eecs.umich.edu } 11817157Sgblack@eecs.umich.edu } 11827157Sgblack@eecs.umich.edu case 0xc: 11837157Sgblack@eecs.umich.edu { 11847157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 11857157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 11867157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 11877157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 11887157Sgblack@eecs.umich.edu return new MovtImm(machInst, rd, rd, imm, true); 11897157Sgblack@eecs.umich.edu } 11907157Sgblack@eecs.umich.edu case 0x12: 11917157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 11927227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 11937227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 11947157Sgblack@eecs.umich.edu } 11957157Sgblack@eecs.umich.edu // Fall through on purpose... 11967157Sgblack@eecs.umich.edu case 0x10: 11977227Sgblack@eecs.umich.edu { 11987227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 11997227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 12007227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12017227Sgblack@eecs.umich.edu const ArmShiftType type = 12027227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 12037227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 12047227Sgblack@eecs.umich.edu } 12057157Sgblack@eecs.umich.edu case 0x14: 12067157Sgblack@eecs.umich.edu return new WarnUnimplemented("sbfx", machInst); 12077157Sgblack@eecs.umich.edu case 0x16: 12087157Sgblack@eecs.umich.edu if (rn == 0xf) { 12097157Sgblack@eecs.umich.edu return new WarnUnimplemented("bfc", machInst); 12107157Sgblack@eecs.umich.edu } else { 12117157Sgblack@eecs.umich.edu return new WarnUnimplemented("bfi", machInst); 12127157Sgblack@eecs.umich.edu } 12137157Sgblack@eecs.umich.edu case 0x1a: 12147157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 12157227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12167227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 12177157Sgblack@eecs.umich.edu } 12187157Sgblack@eecs.umich.edu // Fall through on purpose... 12197157Sgblack@eecs.umich.edu case 0x18: 12207227Sgblack@eecs.umich.edu { 12217227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12227227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 12237227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12247227Sgblack@eecs.umich.edu const ArmShiftType type = 12257227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 12267227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 12277227Sgblack@eecs.umich.edu } 12287157Sgblack@eecs.umich.edu case 0x1c: 12297157Sgblack@eecs.umich.edu return new WarnUnimplemented("ubfx", machInst); 12307157Sgblack@eecs.umich.edu default: 12317157Sgblack@eecs.umich.edu return new Unknown(machInst); 12327157Sgblack@eecs.umich.edu } 12337157Sgblack@eecs.umich.edu } 12347157Sgblack@eecs.umich.edu ''' 12357157Sgblack@eecs.umich.edu}}; 12367157Sgblack@eecs.umich.edu 12377141Sgblack@eecs.umich.edudef format Thumb32DataProcShiftReg() {{ 12387141Sgblack@eecs.umich.edu 12397141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 12407141Sgblack@eecs.umich.edu return ''' 12417141Sgblack@eecs.umich.edu if (s) { 12427146Sgblack@eecs.umich.edu return new %(mnem)sRegCc(machInst, %(dest)s, 12437141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 12447141Sgblack@eecs.umich.edu } else { 12457146Sgblack@eecs.umich.edu return new %(mnem)sReg(machInst, %(dest)s, 12467141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 12477141Sgblack@eecs.umich.edu } 12487141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 12497141Sgblack@eecs.umich.edu 12507141Sgblack@eecs.umich.edu decode_block = ''' 12517141Sgblack@eecs.umich.edu { 12527141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 12537141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 12547141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 12557141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 12567141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 12577141Sgblack@eecs.umich.edu const uint32_t amt = (bits(machInst, 14, 12) << 2) | 12587141Sgblack@eecs.umich.edu bits(machInst, 7, 6); 12597141Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 12607141Sgblack@eecs.umich.edu switch (op) { 12617141Sgblack@eecs.umich.edu case 0x0: 12627141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 12637141Sgblack@eecs.umich.edu %(tst)s 12647141Sgblack@eecs.umich.edu } else { 12657141Sgblack@eecs.umich.edu %(and)s 12667141Sgblack@eecs.umich.edu } 12677141Sgblack@eecs.umich.edu case 0x1: 12687141Sgblack@eecs.umich.edu %(bic)s 12697141Sgblack@eecs.umich.edu case 0x2: 12707141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 12717141Sgblack@eecs.umich.edu %(mov)s 12727141Sgblack@eecs.umich.edu } else { 12737141Sgblack@eecs.umich.edu %(orr)s 12747141Sgblack@eecs.umich.edu } 12757141Sgblack@eecs.umich.edu case 0x3: 12767141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 12777141Sgblack@eecs.umich.edu %(mvn)s 12787141Sgblack@eecs.umich.edu } else { 12797141Sgblack@eecs.umich.edu %(orn)s 12807141Sgblack@eecs.umich.edu } 12817141Sgblack@eecs.umich.edu case 0x4: 12827141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 12837141Sgblack@eecs.umich.edu %(teq)s 12847141Sgblack@eecs.umich.edu } else { 12857141Sgblack@eecs.umich.edu %(eor)s 12867141Sgblack@eecs.umich.edu } 12877141Sgblack@eecs.umich.edu case 0x6: 12887237Sgblack@eecs.umich.edu if (type) { 12897237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, rn, rm, amt, type); 12907237Sgblack@eecs.umich.edu } else { 12917237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, rn, rm, amt, type); 12927237Sgblack@eecs.umich.edu } 12937141Sgblack@eecs.umich.edu case 0x8: 12947141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 12957141Sgblack@eecs.umich.edu %(cmn)s 12967141Sgblack@eecs.umich.edu } else { 12977141Sgblack@eecs.umich.edu %(add)s 12987141Sgblack@eecs.umich.edu } 12997141Sgblack@eecs.umich.edu case 0xa: 13007141Sgblack@eecs.umich.edu %(adc)s 13017141Sgblack@eecs.umich.edu case 0xb: 13027141Sgblack@eecs.umich.edu %(sbc)s 13037141Sgblack@eecs.umich.edu case 0xd: 13047141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13057141Sgblack@eecs.umich.edu %(cmp)s 13067141Sgblack@eecs.umich.edu } else { 13077141Sgblack@eecs.umich.edu %(sub)s 13087141Sgblack@eecs.umich.edu } 13097141Sgblack@eecs.umich.edu case 0xe: 13107141Sgblack@eecs.umich.edu %(rsb)s 13117141Sgblack@eecs.umich.edu default: 13127141Sgblack@eecs.umich.edu return new Unknown(machInst); 13137141Sgblack@eecs.umich.edu } 13147141Sgblack@eecs.umich.edu } 13157141Sgblack@eecs.umich.edu ''' % { 13167141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 13177141Sgblack@eecs.umich.edu "and" : decInst("And"), 13187141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 13197141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 13207141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 13217141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 13227141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 13237141Sgblack@eecs.umich.edu "teq" : decInst("Teq", "INTREG_ZERO"), 13247141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 13257141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", "INTREG_ZERO"), 13267141Sgblack@eecs.umich.edu "add" : decInst("Add"), 13277141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 13287141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 13297141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", "INTREG_ZERO"), 13307141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 13317141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 13327141Sgblack@eecs.umich.edu } 13337141Sgblack@eecs.umich.edu}}; 1334