data.isa revision 7210
17139Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 27139Sgblack@eecs.umich.edu// All rights reserved 37139Sgblack@eecs.umich.edu// 47139Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 57139Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 67139Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 77139Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 87139Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 97139Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 107139Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 117139Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 127139Sgblack@eecs.umich.edu// 137139Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 147139Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 157139Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 167139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 177139Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 187139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 197139Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 207139Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 217139Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227139Sgblack@eecs.umich.edu// this software without specific prior written permission. 237139Sgblack@eecs.umich.edu// 247139Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 257139Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267139Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277139Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287139Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 297139Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317139Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327139Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 337139Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 347139Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357139Sgblack@eecs.umich.edu// 367139Sgblack@eecs.umich.edu// Authors: Gabe Black 377139Sgblack@eecs.umich.edu 387139Sgblack@eecs.umich.edudef format ArmDataProcReg() {{ 397188Sgblack@eecs.umich.edu pclr = ''' 407188Sgblack@eecs.umich.edu return new %(className)ssRegPclr(machInst, %(dest)s, 417188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, 427188Sgblack@eecs.umich.edu type); 437188Sgblack@eecs.umich.edu ''' 447139Sgblack@eecs.umich.edu instDecode = ''' 457139Sgblack@eecs.umich.edu case %(opcode)#x: 467139Sgblack@eecs.umich.edu if (immShift) { 477139Sgblack@eecs.umich.edu if (setCc) { 487188Sgblack@eecs.umich.edu if (%(dest)s == INTREG_PC) { 497188Sgblack@eecs.umich.edu %(pclr)s 507188Sgblack@eecs.umich.edu } else { 517188Sgblack@eecs.umich.edu return new %(className)sRegCc(machInst, %(dest)s, 527188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, type); 537188Sgblack@eecs.umich.edu } 547139Sgblack@eecs.umich.edu } else { 557146Sgblack@eecs.umich.edu return new %(className)sReg(machInst, %(dest)s, %(op1)s, 567141Sgblack@eecs.umich.edu rm, imm5, type); 577139Sgblack@eecs.umich.edu } 587139Sgblack@eecs.umich.edu } else { 597139Sgblack@eecs.umich.edu if (setCc) { 607146Sgblack@eecs.umich.edu return new %(className)sRegRegCc(machInst, %(dest)s, 617141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 627139Sgblack@eecs.umich.edu } else { 637146Sgblack@eecs.umich.edu return new %(className)sRegReg(machInst, %(dest)s, 647141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 657139Sgblack@eecs.umich.edu } 667139Sgblack@eecs.umich.edu } 677139Sgblack@eecs.umich.edu break; 687139Sgblack@eecs.umich.edu ''' 697139Sgblack@eecs.umich.edu 707188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 717188Sgblack@eecs.umich.edu global pclr 727188Sgblack@eecs.umich.edu if useDest: 737188Sgblack@eecs.umich.edu dest = "rd" 747188Sgblack@eecs.umich.edu else: 757188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 767188Sgblack@eecs.umich.edu if useOp1: 777188Sgblack@eecs.umich.edu op1 = "rn" 787188Sgblack@eecs.umich.edu else: 797188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 807188Sgblack@eecs.umich.edu global instDecode, pclrCode 817188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 827188Sgblack@eecs.umich.edu "opcode": opcode, 837188Sgblack@eecs.umich.edu "dest": dest, 847188Sgblack@eecs.umich.edu "op1": op1 } 857188Sgblack@eecs.umich.edu if useDest: 867188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 877188Sgblack@eecs.umich.edu else: 887188Sgblack@eecs.umich.edu substDict["pclr"] = "" 897188Sgblack@eecs.umich.edu return instDecode % substDict 907139Sgblack@eecs.umich.edu 917139Sgblack@eecs.umich.edu decode_block = ''' 927139Sgblack@eecs.umich.edu { 937139Sgblack@eecs.umich.edu const bool immShift = (bits(machInst, 4) == 0); 947139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 957139Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 967139Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 977139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 987139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 997139Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 1007139Sgblack@eecs.umich.edu const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 1017139Sgblack@eecs.umich.edu switch (OPCODE) { 1027139Sgblack@eecs.umich.edu ''' 1037139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 1047139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 1057139Sgblack@eecs.umich.edu decode_block += instCode(0x2, "sub") 1067139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 1077139Sgblack@eecs.umich.edu decode_block += instCode(0x4, "add") 1087139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 1097139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 1107139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 1117188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 1127188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 1137188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 1147188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 1157139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 1167188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 1177139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 1187188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 1197139Sgblack@eecs.umich.edu decode_block += ''' 1207139Sgblack@eecs.umich.edu default: 1217139Sgblack@eecs.umich.edu return new Unknown(machInst); 1227139Sgblack@eecs.umich.edu } 1237139Sgblack@eecs.umich.edu } 1247139Sgblack@eecs.umich.edu ''' 1257139Sgblack@eecs.umich.edu}}; 1267139Sgblack@eecs.umich.edu 1277210Sgblack@eecs.umich.edudef format ArmPackUnpackSatReverse() {{ 1287210Sgblack@eecs.umich.edu decode_block = ''' 1297210Sgblack@eecs.umich.edu { 1307210Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 1317210Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 19, 16); 1327210Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 1337210Sgblack@eecs.umich.edu if (bits(op2, 0) == 0) { 1347210Sgblack@eecs.umich.edu if (op1 == 0) { 1357210Sgblack@eecs.umich.edu return new WarnUnimplemented("pkh", machInst); 1367210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 1) { 1377210Sgblack@eecs.umich.edu return new WarnUnimplemented("ssat", machInst); 1387210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 3) { 1397210Sgblack@eecs.umich.edu return new WarnUnimplemented("usat", machInst); 1407210Sgblack@eecs.umich.edu } 1417210Sgblack@eecs.umich.edu return new Unknown(machInst); 1427210Sgblack@eecs.umich.edu } 1437210Sgblack@eecs.umich.edu switch (op1) { 1447210Sgblack@eecs.umich.edu case 0x0: 1457210Sgblack@eecs.umich.edu if (op2 == 0x3) { 1467210Sgblack@eecs.umich.edu if (a == 0xf) { 1477210Sgblack@eecs.umich.edu return new WarnUnimplemented("sxtb16", machInst); 1487210Sgblack@eecs.umich.edu } else { 1497210Sgblack@eecs.umich.edu return new WarnUnimplemented("sxtab16", machInst); 1507210Sgblack@eecs.umich.edu } 1517210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 1527210Sgblack@eecs.umich.edu return new WarnUnimplemented("sel", machInst); 1537210Sgblack@eecs.umich.edu } 1547210Sgblack@eecs.umich.edu break; 1557210Sgblack@eecs.umich.edu case 0x2: 1567210Sgblack@eecs.umich.edu if (op2 == 0x1) { 1577210Sgblack@eecs.umich.edu return new WarnUnimplemented("ssat16", machInst); 1587210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 1597210Sgblack@eecs.umich.edu if (a == 0xf) { 1607210Sgblack@eecs.umich.edu return new WarnUnimplemented("sxtb", machInst); 1617210Sgblack@eecs.umich.edu } else { 1627210Sgblack@eecs.umich.edu return new WarnUnimplemented("sxtab", machInst); 1637210Sgblack@eecs.umich.edu } 1647210Sgblack@eecs.umich.edu } 1657210Sgblack@eecs.umich.edu break; 1667210Sgblack@eecs.umich.edu case 0x3: 1677210Sgblack@eecs.umich.edu if (op2 == 0x1) { 1687210Sgblack@eecs.umich.edu return new WarnUnimplemented("rev", machInst); 1697210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 1707210Sgblack@eecs.umich.edu if (a == 0xf) { 1717210Sgblack@eecs.umich.edu return new WarnUnimplemented("sxth", machInst); 1727210Sgblack@eecs.umich.edu } else { 1737210Sgblack@eecs.umich.edu return new WarnUnimplemented("sxtah", machInst); 1747210Sgblack@eecs.umich.edu } 1757210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 1767210Sgblack@eecs.umich.edu return new WarnUnimplemented("rev16", machInst); 1777210Sgblack@eecs.umich.edu } 1787210Sgblack@eecs.umich.edu break; 1797210Sgblack@eecs.umich.edu case 0x4: 1807210Sgblack@eecs.umich.edu if (op2 == 0x3) { 1817210Sgblack@eecs.umich.edu if (a == 0xf) { 1827210Sgblack@eecs.umich.edu return new WarnUnimplemented("uxtb16", machInst); 1837210Sgblack@eecs.umich.edu } else { 1847210Sgblack@eecs.umich.edu return new WarnUnimplemented("uxtab16", machInst); 1857210Sgblack@eecs.umich.edu } 1867210Sgblack@eecs.umich.edu } 1877210Sgblack@eecs.umich.edu break; 1887210Sgblack@eecs.umich.edu case 0x6: 1897210Sgblack@eecs.umich.edu if (op2 == 0x1) { 1907210Sgblack@eecs.umich.edu return new WarnUnimplemented("usat16", machInst); 1917210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 1927210Sgblack@eecs.umich.edu if (a == 0xf) { 1937210Sgblack@eecs.umich.edu return new WarnUnimplemented("uxtb", machInst); 1947210Sgblack@eecs.umich.edu } else { 1957210Sgblack@eecs.umich.edu return new WarnUnimplemented("uxtab", machInst); 1967210Sgblack@eecs.umich.edu } 1977210Sgblack@eecs.umich.edu } 1987210Sgblack@eecs.umich.edu break; 1997210Sgblack@eecs.umich.edu case 0x7: 2007210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2017210Sgblack@eecs.umich.edu return new WarnUnimplemented("rbit", machInst); 2027210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2037210Sgblack@eecs.umich.edu if (a == 0xf) { 2047210Sgblack@eecs.umich.edu return new WarnUnimplemented("uxth", machInst); 2057210Sgblack@eecs.umich.edu } else { 2067210Sgblack@eecs.umich.edu return new WarnUnimplemented("uxtah", machInst); 2077210Sgblack@eecs.umich.edu } 2087210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2097210Sgblack@eecs.umich.edu return new WarnUnimplemented("revsh", machInst); 2107210Sgblack@eecs.umich.edu } 2117210Sgblack@eecs.umich.edu break; 2127210Sgblack@eecs.umich.edu } 2137210Sgblack@eecs.umich.edu return new Unknown(machInst); 2147210Sgblack@eecs.umich.edu } 2157210Sgblack@eecs.umich.edu ''' 2167210Sgblack@eecs.umich.edu}}; 2177210Sgblack@eecs.umich.edu 2187194Sgblack@eecs.umich.edudef format ArmParallelAddSubtract() {{ 2197194Sgblack@eecs.umich.edu decode_block=''' 2207194Sgblack@eecs.umich.edu { 2217194Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 2227194Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 2237194Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2247194Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2257194Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2267194Sgblack@eecs.umich.edu if (bits(machInst, 22) == 0) { 2277194Sgblack@eecs.umich.edu switch (op1) { 2287194Sgblack@eecs.umich.edu case 0x1: 2297194Sgblack@eecs.umich.edu switch (op2) { 2307194Sgblack@eecs.umich.edu case 0x0: 2317194Sgblack@eecs.umich.edu return new WarnUnimplemented("sadd16", machInst); 2327194Sgblack@eecs.umich.edu case 0x1: 2337194Sgblack@eecs.umich.edu return new WarnUnimplemented("sasx", machInst); 2347194Sgblack@eecs.umich.edu case 0x2: 2357194Sgblack@eecs.umich.edu return new WarnUnimplemented("ssax", machInst); 2367194Sgblack@eecs.umich.edu case 0x3: 2377194Sgblack@eecs.umich.edu return new WarnUnimplemented("ssub16", machInst); 2387194Sgblack@eecs.umich.edu case 0x4: 2397194Sgblack@eecs.umich.edu return new WarnUnimplemented("sadd8", machInst); 2407194Sgblack@eecs.umich.edu case 0x7: 2417194Sgblack@eecs.umich.edu return new WarnUnimplemented("ssub8", machInst); 2427194Sgblack@eecs.umich.edu } 2437194Sgblack@eecs.umich.edu break; 2447194Sgblack@eecs.umich.edu case 0x2: 2457194Sgblack@eecs.umich.edu switch (op2) { 2467194Sgblack@eecs.umich.edu case 0x0: 2477194Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 2487194Sgblack@eecs.umich.edu case 0x1: 2497194Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 2507194Sgblack@eecs.umich.edu case 0x2: 2517194Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 2527194Sgblack@eecs.umich.edu case 0x3: 2537194Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 2547194Sgblack@eecs.umich.edu case 0x4: 2557194Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 2567194Sgblack@eecs.umich.edu case 0x7: 2577194Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 2587194Sgblack@eecs.umich.edu } 2597194Sgblack@eecs.umich.edu break; 2607194Sgblack@eecs.umich.edu case 0x3: 2617194Sgblack@eecs.umich.edu switch (op2) { 2627194Sgblack@eecs.umich.edu case 0x0: 2637194Sgblack@eecs.umich.edu return new WarnUnimplemented("shadd16", machInst); 2647194Sgblack@eecs.umich.edu case 0x1: 2657194Sgblack@eecs.umich.edu return new WarnUnimplemented("shasx", machInst); 2667194Sgblack@eecs.umich.edu case 0x2: 2677194Sgblack@eecs.umich.edu return new WarnUnimplemented("shsax", machInst); 2687194Sgblack@eecs.umich.edu case 0x3: 2697194Sgblack@eecs.umich.edu return new WarnUnimplemented("shsub16", machInst); 2707194Sgblack@eecs.umich.edu case 0x4: 2717194Sgblack@eecs.umich.edu return new WarnUnimplemented("shadd8", machInst); 2727194Sgblack@eecs.umich.edu case 0x7: 2737194Sgblack@eecs.umich.edu return new WarnUnimplemented("shsub8", machInst); 2747194Sgblack@eecs.umich.edu } 2757194Sgblack@eecs.umich.edu break; 2767194Sgblack@eecs.umich.edu } 2777194Sgblack@eecs.umich.edu } else { 2787194Sgblack@eecs.umich.edu switch (op1) { 2797194Sgblack@eecs.umich.edu case 0x1: 2807194Sgblack@eecs.umich.edu switch (op2) { 2817194Sgblack@eecs.umich.edu case 0x0: 2827194Sgblack@eecs.umich.edu return new WarnUnimplemented("uadd16", machInst); 2837194Sgblack@eecs.umich.edu case 0x1: 2847194Sgblack@eecs.umich.edu return new WarnUnimplemented("uasx", machInst); 2857194Sgblack@eecs.umich.edu case 0x2: 2867194Sgblack@eecs.umich.edu return new WarnUnimplemented("usax", machInst); 2877194Sgblack@eecs.umich.edu case 0x3: 2887194Sgblack@eecs.umich.edu return new WarnUnimplemented("usub16", machInst); 2897194Sgblack@eecs.umich.edu case 0x4: 2907194Sgblack@eecs.umich.edu return new WarnUnimplemented("uadd8", machInst); 2917194Sgblack@eecs.umich.edu case 0x7: 2927194Sgblack@eecs.umich.edu return new WarnUnimplemented("usub8", machInst); 2937194Sgblack@eecs.umich.edu } 2947194Sgblack@eecs.umich.edu break; 2957194Sgblack@eecs.umich.edu case 0x2: 2967194Sgblack@eecs.umich.edu switch (op2) { 2977194Sgblack@eecs.umich.edu case 0x0: 2987194Sgblack@eecs.umich.edu return new WarnUnimplemented("uqadd16", machInst); 2997194Sgblack@eecs.umich.edu case 0x1: 3007194Sgblack@eecs.umich.edu return new WarnUnimplemented("uqasx", machInst); 3017194Sgblack@eecs.umich.edu case 0x2: 3027194Sgblack@eecs.umich.edu return new WarnUnimplemented("uqsax", machInst); 3037194Sgblack@eecs.umich.edu case 0x3: 3047194Sgblack@eecs.umich.edu return new WarnUnimplemented("uqsub16", machInst); 3057194Sgblack@eecs.umich.edu case 0x4: 3067194Sgblack@eecs.umich.edu return new WarnUnimplemented("uqadd8", machInst); 3077194Sgblack@eecs.umich.edu case 0x7: 3087194Sgblack@eecs.umich.edu return new WarnUnimplemented("uqsub8", machInst); 3097194Sgblack@eecs.umich.edu } 3107194Sgblack@eecs.umich.edu break; 3117194Sgblack@eecs.umich.edu case 0x3: 3127194Sgblack@eecs.umich.edu switch (op2) { 3137194Sgblack@eecs.umich.edu case 0x0: 3147194Sgblack@eecs.umich.edu return new WarnUnimplemented("uhadd16", machInst); 3157194Sgblack@eecs.umich.edu case 0x1: 3167194Sgblack@eecs.umich.edu return new WarnUnimplemented("uhasx", machInst); 3177194Sgblack@eecs.umich.edu case 0x2: 3187194Sgblack@eecs.umich.edu return new WarnUnimplemented("uhsax", machInst); 3197194Sgblack@eecs.umich.edu case 0x3: 3207194Sgblack@eecs.umich.edu return new WarnUnimplemented("uhsub16", machInst); 3217194Sgblack@eecs.umich.edu case 0x4: 3227194Sgblack@eecs.umich.edu return new WarnUnimplemented("uhadd8", machInst); 3237194Sgblack@eecs.umich.edu case 0x7: 3247194Sgblack@eecs.umich.edu return new WarnUnimplemented("uhsub8", machInst); 3257194Sgblack@eecs.umich.edu } 3267194Sgblack@eecs.umich.edu break; 3277194Sgblack@eecs.umich.edu } 3287194Sgblack@eecs.umich.edu } 3297194Sgblack@eecs.umich.edu return new Unknown(machInst); 3307194Sgblack@eecs.umich.edu } 3317194Sgblack@eecs.umich.edu ''' 3327194Sgblack@eecs.umich.edu}}; 3337194Sgblack@eecs.umich.edu 3347139Sgblack@eecs.umich.edudef format ArmDataProcImm() {{ 3357188Sgblack@eecs.umich.edu pclr = ''' 3367188Sgblack@eecs.umich.edu return new %(className)ssImmPclr(machInst, %(dest)s, 3377188Sgblack@eecs.umich.edu %(op1)s, imm, false); 3387188Sgblack@eecs.umich.edu ''' 3397188Sgblack@eecs.umich.edu adr = ''' 3407188Sgblack@eecs.umich.edu return new AdrImm(machInst, %(dest)s, %(add)s, 3417188Sgblack@eecs.umich.edu imm, false); 3427188Sgblack@eecs.umich.edu ''' 3437139Sgblack@eecs.umich.edu instDecode = ''' 3447188Sgblack@eecs.umich.edu case %(opcode)#x: 3457139Sgblack@eecs.umich.edu if (setCc) { 3467188Sgblack@eecs.umich.edu if (%(pclrInst)s && %(dest)s == INTREG_PC) { 3477188Sgblack@eecs.umich.edu %(pclr)s 3487188Sgblack@eecs.umich.edu } else { 3497188Sgblack@eecs.umich.edu return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 3507188Sgblack@eecs.umich.edu imm, rotC); 3517188Sgblack@eecs.umich.edu } 3527139Sgblack@eecs.umich.edu } else { 3537188Sgblack@eecs.umich.edu if (%(adrInst)s && %(op1)s == INTREG_PC) { 3547188Sgblack@eecs.umich.edu %(adr)s 3557188Sgblack@eecs.umich.edu } else { 3567188Sgblack@eecs.umich.edu return new %(className)sImm(machInst, %(dest)s, %(op1)s, 3577188Sgblack@eecs.umich.edu imm, rotC); 3587188Sgblack@eecs.umich.edu } 3597139Sgblack@eecs.umich.edu } 3607139Sgblack@eecs.umich.edu break; 3617139Sgblack@eecs.umich.edu ''' 3627139Sgblack@eecs.umich.edu 3637188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 3647188Sgblack@eecs.umich.edu global instDecode, pclr, adr 3657188Sgblack@eecs.umich.edu if useDest: 3667188Sgblack@eecs.umich.edu dest = "rd" 3677188Sgblack@eecs.umich.edu else: 3687188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 3697188Sgblack@eecs.umich.edu if useOp1: 3707188Sgblack@eecs.umich.edu op1 = "rn" 3717188Sgblack@eecs.umich.edu else: 3727188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 3737188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 3747188Sgblack@eecs.umich.edu "opcode": opcode, 3757188Sgblack@eecs.umich.edu "dest": dest, 3767188Sgblack@eecs.umich.edu "op1": op1, 3777188Sgblack@eecs.umich.edu "adr": "", 3787188Sgblack@eecs.umich.edu "adrInst": "false" } 3797188Sgblack@eecs.umich.edu if useDest: 3807188Sgblack@eecs.umich.edu substDict["pclrInst"] = "true" 3817188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 3827188Sgblack@eecs.umich.edu else: 3837188Sgblack@eecs.umich.edu substDict["pclrInst"] = "false" 3847188Sgblack@eecs.umich.edu substDict["pclr"] = "" 3857188Sgblack@eecs.umich.edu return instDecode % substDict 3867185Sgblack@eecs.umich.edu 3877188Sgblack@eecs.umich.edu def adrCode(opcode, mnem, add="1"): 3887188Sgblack@eecs.umich.edu global instDecode, pclr, adr 3897188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 3907188Sgblack@eecs.umich.edu "opcode": opcode, 3917188Sgblack@eecs.umich.edu "dest": "rd", 3927188Sgblack@eecs.umich.edu "op1": "rn", 3937188Sgblack@eecs.umich.edu "add": add, 3947188Sgblack@eecs.umich.edu "pclrInst": "true", 3957188Sgblack@eecs.umich.edu "adrInst": "true" } 3967188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 3977188Sgblack@eecs.umich.edu substDict["adr"] = adr % substDict 3987188Sgblack@eecs.umich.edu return instDecode % substDict 3997139Sgblack@eecs.umich.edu 4007139Sgblack@eecs.umich.edu decode_block = ''' 4017139Sgblack@eecs.umich.edu { 4027139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 4037139Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 4047139Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 4057139Sgblack@eecs.umich.edu const bool rotC = (rotation != 0); 4067139Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 4077139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 4087139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 4097139Sgblack@eecs.umich.edu switch (OPCODE) { 4107139Sgblack@eecs.umich.edu ''' 4117139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 4127139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 4137185Sgblack@eecs.umich.edu decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 4147139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 4157185Sgblack@eecs.umich.edu decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 4167139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 4177139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 4187139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 4197188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 4207188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 4217188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 4227188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 4237139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 4247188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 4257139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 4267188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 4277139Sgblack@eecs.umich.edu decode_block += ''' 4287139Sgblack@eecs.umich.edu default: 4297139Sgblack@eecs.umich.edu return new Unknown(machInst); 4307139Sgblack@eecs.umich.edu } 4317139Sgblack@eecs.umich.edu } 4327139Sgblack@eecs.umich.edu ''' 4337139Sgblack@eecs.umich.edu}}; 4347141Sgblack@eecs.umich.edu 4357195Sgblack@eecs.umich.edudef format ArmSatAddSub() {{ 4367195Sgblack@eecs.umich.edu decode_block = ''' 4377195Sgblack@eecs.umich.edu { 4387195Sgblack@eecs.umich.edu IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 4397195Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 4407195Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 4417195Sgblack@eecs.umich.edu switch (OPCODE) { 4427195Sgblack@eecs.umich.edu case 0x8: 4437195Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 4447195Sgblack@eecs.umich.edu case 0x9: 4457195Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 4467195Sgblack@eecs.umich.edu case 0xa: 4477195Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 4487195Sgblack@eecs.umich.edu case 0xb: 4497195Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 4507195Sgblack@eecs.umich.edu default: 4517195Sgblack@eecs.umich.edu return new Unknown(machInst); 4527195Sgblack@eecs.umich.edu } 4537195Sgblack@eecs.umich.edu } 4547195Sgblack@eecs.umich.edu ''' 4557195Sgblack@eecs.umich.edu}}; 4567195Sgblack@eecs.umich.edu 4577141Sgblack@eecs.umich.edudef format Thumb16ShiftAddSubMoveCmp() {{ 4587141Sgblack@eecs.umich.edu decode_block = ''' 4597141Sgblack@eecs.umich.edu { 4607141Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 10, 6); 4617141Sgblack@eecs.umich.edu const uint32_t imm3 = bits(machInst, 8, 6); 4627141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 4637141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 4647141Sgblack@eecs.umich.edu const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 4657141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 4667141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 4677141Sgblack@eecs.umich.edu switch (bits(machInst, 13, 11)) { 4687141Sgblack@eecs.umich.edu case 0x0: // lsl 4697183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 4707141Sgblack@eecs.umich.edu case 0x1: // lsr 4717183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 4727141Sgblack@eecs.umich.edu case 0x2: // asr 4737183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 4747141Sgblack@eecs.umich.edu case 0x3: 4757141Sgblack@eecs.umich.edu switch (bits(machInst, 10, 9)) { 4767141Sgblack@eecs.umich.edu case 0x0: 4777183Sgblack@eecs.umich.edu return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 4787141Sgblack@eecs.umich.edu case 0x1: 4797183Sgblack@eecs.umich.edu return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 4807141Sgblack@eecs.umich.edu case 0x2: 4817183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd, rn, imm3, true); 4827141Sgblack@eecs.umich.edu case 0x3: 4837183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd, rn, imm3, true); 4847141Sgblack@eecs.umich.edu } 4857141Sgblack@eecs.umich.edu case 0x4: 4867183Sgblack@eecs.umich.edu return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 4877141Sgblack@eecs.umich.edu case 0x5: 4887146Sgblack@eecs.umich.edu return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 4897141Sgblack@eecs.umich.edu case 0x6: 4907183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd8, rd8, imm8, true); 4917141Sgblack@eecs.umich.edu case 0x7: 4927183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd8, rd8, imm8, true); 4937141Sgblack@eecs.umich.edu } 4947141Sgblack@eecs.umich.edu } 4957141Sgblack@eecs.umich.edu ''' 4967141Sgblack@eecs.umich.edu}}; 4977141Sgblack@eecs.umich.edu 4987141Sgblack@eecs.umich.edudef format Thumb16DataProcessing() {{ 4997141Sgblack@eecs.umich.edu decode_block = ''' 5007141Sgblack@eecs.umich.edu { 5017141Sgblack@eecs.umich.edu const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 5027141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 5037141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 6)) { 5047141Sgblack@eecs.umich.edu case 0x0: 5057183Sgblack@eecs.umich.edu return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 5067141Sgblack@eecs.umich.edu case 0x1: 5077183Sgblack@eecs.umich.edu return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 5087141Sgblack@eecs.umich.edu case 0x2: //lsl 5097183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL); 5107141Sgblack@eecs.umich.edu case 0x3: //lsr 5117183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR); 5127141Sgblack@eecs.umich.edu case 0x4: //asr 5137183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR); 5147141Sgblack@eecs.umich.edu case 0x5: 5157183Sgblack@eecs.umich.edu return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 5167141Sgblack@eecs.umich.edu case 0x6: 5177183Sgblack@eecs.umich.edu return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 5187141Sgblack@eecs.umich.edu case 0x7: // ror 5197183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR); 5207141Sgblack@eecs.umich.edu case 0x8: 5217183Sgblack@eecs.umich.edu return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 5227141Sgblack@eecs.umich.edu case 0x9: 5237183Sgblack@eecs.umich.edu return new RsbImmCc(machInst, rdn, rm, 0, true); 5247141Sgblack@eecs.umich.edu case 0xa: 5257183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 5267141Sgblack@eecs.umich.edu case 0xb: 5277183Sgblack@eecs.umich.edu return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 5287141Sgblack@eecs.umich.edu case 0xc: 5297183Sgblack@eecs.umich.edu return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 5307141Sgblack@eecs.umich.edu case 0xd: 5317183Sgblack@eecs.umich.edu return new MulCc(machInst, rdn, rm, rdn); 5327141Sgblack@eecs.umich.edu case 0xe: 5337183Sgblack@eecs.umich.edu return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 5347141Sgblack@eecs.umich.edu case 0xf: 5357183Sgblack@eecs.umich.edu return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 5367141Sgblack@eecs.umich.edu } 5377141Sgblack@eecs.umich.edu } 5387141Sgblack@eecs.umich.edu ''' 5397141Sgblack@eecs.umich.edu}}; 5407141Sgblack@eecs.umich.edu 5417141Sgblack@eecs.umich.edudef format Thumb16SpecDataAndBx() {{ 5427141Sgblack@eecs.umich.edu decode_block = ''' 5437141Sgblack@eecs.umich.edu { 5447141Sgblack@eecs.umich.edu const IntRegIndex rdn = 5457141Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 5467141Sgblack@eecs.umich.edu (bits(machInst, 7) << 3)); 5477141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 5487141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 8)) { 5497141Sgblack@eecs.umich.edu case 0x0: 5507146Sgblack@eecs.umich.edu return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 5517141Sgblack@eecs.umich.edu case 0x1: 5527183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 5537141Sgblack@eecs.umich.edu case 0x2: 5547146Sgblack@eecs.umich.edu return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 5557141Sgblack@eecs.umich.edu case 0x3: 5567154Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 5577154Sgblack@eecs.umich.edu return new BxReg(machInst, 5587154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 5597154Sgblack@eecs.umich.edu COND_UC); 5607154Sgblack@eecs.umich.edu } else { 5617154Sgblack@eecs.umich.edu return new BlxReg(machInst, 5627154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 5637154Sgblack@eecs.umich.edu COND_UC); 5647154Sgblack@eecs.umich.edu } 5657141Sgblack@eecs.umich.edu } 5667141Sgblack@eecs.umich.edu } 5677141Sgblack@eecs.umich.edu ''' 5687141Sgblack@eecs.umich.edu}}; 5697141Sgblack@eecs.umich.edu 5707141Sgblack@eecs.umich.edudef format Thumb16Adr() {{ 5717141Sgblack@eecs.umich.edu decode_block = ''' 5727141Sgblack@eecs.umich.edu { 5737141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 5747141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 5757185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 5767141Sgblack@eecs.umich.edu } 5777141Sgblack@eecs.umich.edu ''' 5787141Sgblack@eecs.umich.edu}}; 5797141Sgblack@eecs.umich.edu 5807141Sgblack@eecs.umich.edudef format Thumb16AddSp() {{ 5817141Sgblack@eecs.umich.edu decode_block = ''' 5827141Sgblack@eecs.umich.edu { 5837141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 5847141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 5857146Sgblack@eecs.umich.edu return new AddImm(machInst, rd, INTREG_SP, imm8, true); 5867141Sgblack@eecs.umich.edu } 5877141Sgblack@eecs.umich.edu ''' 5887141Sgblack@eecs.umich.edu}}; 5897141Sgblack@eecs.umich.edu 5907141Sgblack@eecs.umich.edudef format Thumb16Misc() {{ 5917141Sgblack@eecs.umich.edu decode_block = ''' 5927141Sgblack@eecs.umich.edu { 5937141Sgblack@eecs.umich.edu switch (bits(machInst, 11, 8)) { 5947141Sgblack@eecs.umich.edu case 0x0: 5957141Sgblack@eecs.umich.edu if (bits(machInst, 7)) { 5967146Sgblack@eecs.umich.edu return new SubImm(machInst, INTREG_SP, INTREG_SP, 5977141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 5987141Sgblack@eecs.umich.edu } else { 5997146Sgblack@eecs.umich.edu return new AddImm(machInst, INTREG_SP, INTREG_SP, 6007141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 6017141Sgblack@eecs.umich.edu } 6027141Sgblack@eecs.umich.edu case 0x1: 6037154Sgblack@eecs.umich.edu return new Cbz(machInst, 6047154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 6057154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 6067154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 6077141Sgblack@eecs.umich.edu case 0x2: 6087141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 6097141Sgblack@eecs.umich.edu case 0x0: 6107141Sgblack@eecs.umich.edu return new WarnUnimplemented("sxth", machInst); 6117141Sgblack@eecs.umich.edu case 0x1: 6127141Sgblack@eecs.umich.edu return new WarnUnimplemented("sxtb", machInst); 6137141Sgblack@eecs.umich.edu case 0x2: 6147141Sgblack@eecs.umich.edu return new WarnUnimplemented("uxth", machInst); 6157141Sgblack@eecs.umich.edu case 0x3: 6167141Sgblack@eecs.umich.edu return new WarnUnimplemented("uxtb", machInst); 6177141Sgblack@eecs.umich.edu } 6187141Sgblack@eecs.umich.edu case 0x3: 6197154Sgblack@eecs.umich.edu return new Cbz(machInst, 6207154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 6217154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 6227154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 6237141Sgblack@eecs.umich.edu case 0x4: 6247141Sgblack@eecs.umich.edu case 0x5: 6257201Sgblack@eecs.umich.edu { 6267201Sgblack@eecs.umich.edu const uint32_t m = bits(machInst, 8); 6277201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 6287201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, false, false, false, 6297201Sgblack@eecs.umich.edu true, false, regList); 6307201Sgblack@eecs.umich.edu } 6317141Sgblack@eecs.umich.edu case 0x6: 6327141Sgblack@eecs.umich.edu { 6337141Sgblack@eecs.umich.edu const uint32_t opBits = bits(machInst, 7, 5); 6347141Sgblack@eecs.umich.edu if (opBits == 2) { 6357141Sgblack@eecs.umich.edu return new WarnUnimplemented("setend", machInst); 6367141Sgblack@eecs.umich.edu } else if (opBits == 3) { 6377141Sgblack@eecs.umich.edu return new WarnUnimplemented("cps", machInst); 6387141Sgblack@eecs.umich.edu } 6397141Sgblack@eecs.umich.edu } 6407141Sgblack@eecs.umich.edu case 0x9: 6417154Sgblack@eecs.umich.edu return new Cbnz(machInst, 6427154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 6437154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 6447154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 6457141Sgblack@eecs.umich.edu case 0xa: 6467141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 5)) { 6477141Sgblack@eecs.umich.edu case 0x0: 6487141Sgblack@eecs.umich.edu return new WarnUnimplemented("rev", machInst); 6497141Sgblack@eecs.umich.edu case 0x1: 6507141Sgblack@eecs.umich.edu return new WarnUnimplemented("rev16", machInst); 6517141Sgblack@eecs.umich.edu case 0x3: 6527141Sgblack@eecs.umich.edu return new WarnUnimplemented("revsh", machInst); 6537141Sgblack@eecs.umich.edu default: 6547141Sgblack@eecs.umich.edu break; 6557141Sgblack@eecs.umich.edu } 6567141Sgblack@eecs.umich.edu break; 6577141Sgblack@eecs.umich.edu case 0xb: 6587154Sgblack@eecs.umich.edu return new Cbnz(machInst, 6597154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 6607154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 6617154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 6627141Sgblack@eecs.umich.edu case 0xc: 6637141Sgblack@eecs.umich.edu case 0xd: 6647201Sgblack@eecs.umich.edu { 6657201Sgblack@eecs.umich.edu const uint32_t p = bits(machInst, 8); 6667201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 6677201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, true, true, false, 6687201Sgblack@eecs.umich.edu true, true, regList); 6697201Sgblack@eecs.umich.edu } 6707141Sgblack@eecs.umich.edu case 0xe: 6717141Sgblack@eecs.umich.edu return new WarnUnimplemented("bkpt", machInst); 6727141Sgblack@eecs.umich.edu case 0xf: 6737141Sgblack@eecs.umich.edu if (bits(machInst, 3, 0) != 0) 6747141Sgblack@eecs.umich.edu return new WarnUnimplemented("it", machInst); 6757141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 4)) { 6767141Sgblack@eecs.umich.edu case 0x0: 6777141Sgblack@eecs.umich.edu return new WarnUnimplemented("nop", machInst); 6787141Sgblack@eecs.umich.edu case 0x1: 6797141Sgblack@eecs.umich.edu return new WarnUnimplemented("yield", machInst); 6807141Sgblack@eecs.umich.edu case 0x2: 6817141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfe", machInst); 6827141Sgblack@eecs.umich.edu case 0x3: 6837141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfi", machInst); 6847141Sgblack@eecs.umich.edu case 0x4: 6857141Sgblack@eecs.umich.edu return new WarnUnimplemented("sev", machInst); 6867141Sgblack@eecs.umich.edu default: 6877141Sgblack@eecs.umich.edu return new WarnUnimplemented("unallocated_hint", machInst); 6887141Sgblack@eecs.umich.edu } 6897141Sgblack@eecs.umich.edu default: 6907141Sgblack@eecs.umich.edu break; 6917141Sgblack@eecs.umich.edu } 6927141Sgblack@eecs.umich.edu return new Unknown(machInst); 6937141Sgblack@eecs.umich.edu } 6947141Sgblack@eecs.umich.edu ''' 6957141Sgblack@eecs.umich.edu}}; 6967141Sgblack@eecs.umich.edu 6977141Sgblack@eecs.umich.edudef format Thumb32DataProcModImm() {{ 6987141Sgblack@eecs.umich.edu 6997141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 7007141Sgblack@eecs.umich.edu return ''' 7017141Sgblack@eecs.umich.edu if (s) { 7027146Sgblack@eecs.umich.edu return new %(mnem)sImmCc(machInst, %(dest)s, 7037183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 7047141Sgblack@eecs.umich.edu } else { 7057146Sgblack@eecs.umich.edu return new %(mnem)sImm(machInst, %(dest)s, 7067183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 7077141Sgblack@eecs.umich.edu } 7087141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 7097141Sgblack@eecs.umich.edu 7107141Sgblack@eecs.umich.edu decode_block = ''' 7117141Sgblack@eecs.umich.edu { 7127141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 7137141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 7147141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 7157141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 7167141Sgblack@eecs.umich.edu const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 7177141Sgblack@eecs.umich.edu bits(machInst, 14, 12); 7187183Sgblack@eecs.umich.edu const bool rotC = ctrlImm > 3; 7197141Sgblack@eecs.umich.edu const uint32_t dataImm = bits(machInst, 7, 0); 7207141Sgblack@eecs.umich.edu const uint32_t imm = modified_imm(ctrlImm, dataImm); 7217141Sgblack@eecs.umich.edu switch (op) { 7227141Sgblack@eecs.umich.edu case 0x0: 7237141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 7247141Sgblack@eecs.umich.edu %(tst)s 7257141Sgblack@eecs.umich.edu } else { 7267141Sgblack@eecs.umich.edu %(and)s 7277141Sgblack@eecs.umich.edu } 7287141Sgblack@eecs.umich.edu case 0x1: 7297141Sgblack@eecs.umich.edu %(bic)s 7307141Sgblack@eecs.umich.edu case 0x2: 7317141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 7327141Sgblack@eecs.umich.edu %(mov)s 7337141Sgblack@eecs.umich.edu } else { 7347141Sgblack@eecs.umich.edu %(orr)s 7357141Sgblack@eecs.umich.edu } 7367141Sgblack@eecs.umich.edu case 0x3: 7377141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 7387141Sgblack@eecs.umich.edu %(mvn)s 7397141Sgblack@eecs.umich.edu } else { 7407141Sgblack@eecs.umich.edu %(orn)s 7417141Sgblack@eecs.umich.edu } 7427141Sgblack@eecs.umich.edu case 0x4: 7437141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 7447141Sgblack@eecs.umich.edu %(teq)s 7457141Sgblack@eecs.umich.edu } else { 7467141Sgblack@eecs.umich.edu %(eor)s 7477141Sgblack@eecs.umich.edu } 7487141Sgblack@eecs.umich.edu case 0x8: 7497141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 7507141Sgblack@eecs.umich.edu %(cmn)s 7517141Sgblack@eecs.umich.edu } else { 7527141Sgblack@eecs.umich.edu %(add)s 7537141Sgblack@eecs.umich.edu } 7547141Sgblack@eecs.umich.edu case 0xa: 7557141Sgblack@eecs.umich.edu %(adc)s 7567141Sgblack@eecs.umich.edu case 0xb: 7577141Sgblack@eecs.umich.edu %(sbc)s 7587141Sgblack@eecs.umich.edu case 0xd: 7597141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 7607141Sgblack@eecs.umich.edu %(cmp)s 7617141Sgblack@eecs.umich.edu } else { 7627141Sgblack@eecs.umich.edu %(sub)s 7637141Sgblack@eecs.umich.edu } 7647141Sgblack@eecs.umich.edu case 0xe: 7657141Sgblack@eecs.umich.edu %(rsb)s 7667141Sgblack@eecs.umich.edu default: 7677141Sgblack@eecs.umich.edu return new Unknown(machInst); 7687141Sgblack@eecs.umich.edu } 7697141Sgblack@eecs.umich.edu } 7707141Sgblack@eecs.umich.edu ''' % { 7717141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 7727141Sgblack@eecs.umich.edu "and" : decInst("And"), 7737141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 7747141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 7757141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 7767141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 7777141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 7787141Sgblack@eecs.umich.edu "teq" : decInst("Teq", dest="INTREG_ZERO"), 7797141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 7807141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 7817141Sgblack@eecs.umich.edu "add" : decInst("Add"), 7827141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 7837141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 7847141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 7857141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 7867141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 7877141Sgblack@eecs.umich.edu } 7887141Sgblack@eecs.umich.edu}}; 7897141Sgblack@eecs.umich.edu 7907157Sgblack@eecs.umich.edudef format Thumb32DataProcPlainBin() {{ 7917157Sgblack@eecs.umich.edu decode_block = ''' 7927157Sgblack@eecs.umich.edu { 7937157Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 20); 7947157Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 7957157Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 7967157Sgblack@eecs.umich.edu switch (op) { 7977157Sgblack@eecs.umich.edu case 0x0: 7987157Sgblack@eecs.umich.edu { 7997157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 8007157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 8017157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 8027185Sgblack@eecs.umich.edu if (rn == 0xf) { 8037185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, 8047185Sgblack@eecs.umich.edu imm, false); 8057185Sgblack@eecs.umich.edu } else { 8067185Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm, true); 8077185Sgblack@eecs.umich.edu } 8087157Sgblack@eecs.umich.edu } 8097157Sgblack@eecs.umich.edu case 0x4: 8107157Sgblack@eecs.umich.edu { 8117157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 8127157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 8137157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 8147157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 8157157Sgblack@eecs.umich.edu return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 8167157Sgblack@eecs.umich.edu } 8177157Sgblack@eecs.umich.edu case 0xa: 8187157Sgblack@eecs.umich.edu { 8197157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 8207157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 8217157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 8227185Sgblack@eecs.umich.edu if (rn == 0xf) { 8237185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)0, 8247185Sgblack@eecs.umich.edu imm, false); 8257185Sgblack@eecs.umich.edu } else { 8267185Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm, true); 8277185Sgblack@eecs.umich.edu } 8287157Sgblack@eecs.umich.edu } 8297157Sgblack@eecs.umich.edu case 0xc: 8307157Sgblack@eecs.umich.edu { 8317157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 8327157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 8337157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 8347157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 8357157Sgblack@eecs.umich.edu return new MovtImm(machInst, rd, rd, imm, true); 8367157Sgblack@eecs.umich.edu } 8377157Sgblack@eecs.umich.edu case 0x12: 8387157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 8397157Sgblack@eecs.umich.edu return new WarnUnimplemented("ssat16", machInst); 8407157Sgblack@eecs.umich.edu } 8417157Sgblack@eecs.umich.edu // Fall through on purpose... 8427157Sgblack@eecs.umich.edu case 0x10: 8437157Sgblack@eecs.umich.edu return new WarnUnimplemented("ssat", machInst); 8447157Sgblack@eecs.umich.edu case 0x14: 8457157Sgblack@eecs.umich.edu return new WarnUnimplemented("sbfx", machInst); 8467157Sgblack@eecs.umich.edu case 0x16: 8477157Sgblack@eecs.umich.edu if (rn == 0xf) { 8487157Sgblack@eecs.umich.edu return new WarnUnimplemented("bfc", machInst); 8497157Sgblack@eecs.umich.edu } else { 8507157Sgblack@eecs.umich.edu return new WarnUnimplemented("bfi", machInst); 8517157Sgblack@eecs.umich.edu } 8527157Sgblack@eecs.umich.edu case 0x1a: 8537157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 8547157Sgblack@eecs.umich.edu return new WarnUnimplemented("usat16", machInst); 8557157Sgblack@eecs.umich.edu } 8567157Sgblack@eecs.umich.edu // Fall through on purpose... 8577157Sgblack@eecs.umich.edu case 0x18: 8587157Sgblack@eecs.umich.edu return new WarnUnimplemented("usat", machInst); 8597157Sgblack@eecs.umich.edu case 0x1c: 8607157Sgblack@eecs.umich.edu return new WarnUnimplemented("ubfx", machInst); 8617157Sgblack@eecs.umich.edu default: 8627157Sgblack@eecs.umich.edu return new Unknown(machInst); 8637157Sgblack@eecs.umich.edu } 8647157Sgblack@eecs.umich.edu } 8657157Sgblack@eecs.umich.edu ''' 8667157Sgblack@eecs.umich.edu}}; 8677157Sgblack@eecs.umich.edu 8687141Sgblack@eecs.umich.edudef format Thumb32DataProcShiftReg() {{ 8697141Sgblack@eecs.umich.edu 8707141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 8717141Sgblack@eecs.umich.edu return ''' 8727141Sgblack@eecs.umich.edu if (s) { 8737146Sgblack@eecs.umich.edu return new %(mnem)sRegCc(machInst, %(dest)s, 8747141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 8757141Sgblack@eecs.umich.edu } else { 8767146Sgblack@eecs.umich.edu return new %(mnem)sReg(machInst, %(dest)s, 8777141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 8787141Sgblack@eecs.umich.edu } 8797141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 8807141Sgblack@eecs.umich.edu 8817141Sgblack@eecs.umich.edu decode_block = ''' 8827141Sgblack@eecs.umich.edu { 8837141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 8847141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 8857141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 8867141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 8877141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 8887141Sgblack@eecs.umich.edu const uint32_t amt = (bits(machInst, 14, 12) << 2) | 8897141Sgblack@eecs.umich.edu bits(machInst, 7, 6); 8907141Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 8917141Sgblack@eecs.umich.edu switch (op) { 8927141Sgblack@eecs.umich.edu case 0x0: 8937141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 8947141Sgblack@eecs.umich.edu %(tst)s 8957141Sgblack@eecs.umich.edu } else { 8967141Sgblack@eecs.umich.edu %(and)s 8977141Sgblack@eecs.umich.edu } 8987141Sgblack@eecs.umich.edu case 0x1: 8997141Sgblack@eecs.umich.edu %(bic)s 9007141Sgblack@eecs.umich.edu case 0x2: 9017141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 9027141Sgblack@eecs.umich.edu %(mov)s 9037141Sgblack@eecs.umich.edu } else { 9047141Sgblack@eecs.umich.edu %(orr)s 9057141Sgblack@eecs.umich.edu } 9067141Sgblack@eecs.umich.edu case 0x3: 9077141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 9087141Sgblack@eecs.umich.edu %(mvn)s 9097141Sgblack@eecs.umich.edu } else { 9107141Sgblack@eecs.umich.edu %(orn)s 9117141Sgblack@eecs.umich.edu } 9127141Sgblack@eecs.umich.edu case 0x4: 9137141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 9147141Sgblack@eecs.umich.edu %(teq)s 9157141Sgblack@eecs.umich.edu } else { 9167141Sgblack@eecs.umich.edu %(eor)s 9177141Sgblack@eecs.umich.edu } 9187141Sgblack@eecs.umich.edu case 0x6: 9197141Sgblack@eecs.umich.edu return new WarnUnimplemented("pkh", machInst); 9207141Sgblack@eecs.umich.edu case 0x8: 9217141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 9227141Sgblack@eecs.umich.edu %(cmn)s 9237141Sgblack@eecs.umich.edu } else { 9247141Sgblack@eecs.umich.edu %(add)s 9257141Sgblack@eecs.umich.edu } 9267141Sgblack@eecs.umich.edu case 0xa: 9277141Sgblack@eecs.umich.edu %(adc)s 9287141Sgblack@eecs.umich.edu case 0xb: 9297141Sgblack@eecs.umich.edu %(sbc)s 9307141Sgblack@eecs.umich.edu case 0xd: 9317141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 9327141Sgblack@eecs.umich.edu %(cmp)s 9337141Sgblack@eecs.umich.edu } else { 9347141Sgblack@eecs.umich.edu %(sub)s 9357141Sgblack@eecs.umich.edu } 9367141Sgblack@eecs.umich.edu case 0xe: 9377141Sgblack@eecs.umich.edu %(rsb)s 9387141Sgblack@eecs.umich.edu default: 9397141Sgblack@eecs.umich.edu return new Unknown(machInst); 9407141Sgblack@eecs.umich.edu } 9417141Sgblack@eecs.umich.edu } 9427141Sgblack@eecs.umich.edu ''' % { 9437141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 9447141Sgblack@eecs.umich.edu "and" : decInst("And"), 9457141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 9467141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 9477141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 9487141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 9497141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 9507141Sgblack@eecs.umich.edu "teq" : decInst("Teq", "INTREG_ZERO"), 9517141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 9527141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", "INTREG_ZERO"), 9537141Sgblack@eecs.umich.edu "add" : decInst("Add"), 9547141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 9557141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 9567141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", "INTREG_ZERO"), 9577141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 9587141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 9597141Sgblack@eecs.umich.edu } 9607141Sgblack@eecs.umich.edu}}; 961