data.isa revision 7188
17139Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 27139Sgblack@eecs.umich.edu// All rights reserved 37139Sgblack@eecs.umich.edu// 47139Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 57139Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 67139Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 77139Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 87139Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 97139Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 107139Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 117139Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 127139Sgblack@eecs.umich.edu// 137139Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 147139Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 157139Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 167139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 177139Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 187139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 197139Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 207139Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 217139Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227139Sgblack@eecs.umich.edu// this software without specific prior written permission. 237139Sgblack@eecs.umich.edu// 247139Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 257139Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267139Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277139Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287139Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 297139Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317139Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327139Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 337139Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 347139Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357139Sgblack@eecs.umich.edu// 367139Sgblack@eecs.umich.edu// Authors: Gabe Black 377139Sgblack@eecs.umich.edu 387139Sgblack@eecs.umich.edudef format ArmDataProcReg() {{ 397188Sgblack@eecs.umich.edu pclr = ''' 407188Sgblack@eecs.umich.edu return new %(className)ssRegPclr(machInst, %(dest)s, 417188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, 427188Sgblack@eecs.umich.edu type); 437188Sgblack@eecs.umich.edu ''' 447139Sgblack@eecs.umich.edu instDecode = ''' 457139Sgblack@eecs.umich.edu case %(opcode)#x: 467139Sgblack@eecs.umich.edu if (immShift) { 477139Sgblack@eecs.umich.edu if (setCc) { 487188Sgblack@eecs.umich.edu if (%(dest)s == INTREG_PC) { 497188Sgblack@eecs.umich.edu %(pclr)s 507188Sgblack@eecs.umich.edu } else { 517188Sgblack@eecs.umich.edu return new %(className)sRegCc(machInst, %(dest)s, 527188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, type); 537188Sgblack@eecs.umich.edu } 547139Sgblack@eecs.umich.edu } else { 557146Sgblack@eecs.umich.edu return new %(className)sReg(machInst, %(dest)s, %(op1)s, 567141Sgblack@eecs.umich.edu rm, imm5, type); 577139Sgblack@eecs.umich.edu } 587139Sgblack@eecs.umich.edu } else { 597139Sgblack@eecs.umich.edu if (setCc) { 607146Sgblack@eecs.umich.edu return new %(className)sRegRegCc(machInst, %(dest)s, 617141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 627139Sgblack@eecs.umich.edu } else { 637146Sgblack@eecs.umich.edu return new %(className)sRegReg(machInst, %(dest)s, 647141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 657139Sgblack@eecs.umich.edu } 667139Sgblack@eecs.umich.edu } 677139Sgblack@eecs.umich.edu break; 687139Sgblack@eecs.umich.edu ''' 697139Sgblack@eecs.umich.edu 707188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 717188Sgblack@eecs.umich.edu global pclr 727188Sgblack@eecs.umich.edu if useDest: 737188Sgblack@eecs.umich.edu dest = "rd" 747188Sgblack@eecs.umich.edu else: 757188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 767188Sgblack@eecs.umich.edu if useOp1: 777188Sgblack@eecs.umich.edu op1 = "rn" 787188Sgblack@eecs.umich.edu else: 797188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 807188Sgblack@eecs.umich.edu global instDecode, pclrCode 817188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 827188Sgblack@eecs.umich.edu "opcode": opcode, 837188Sgblack@eecs.umich.edu "dest": dest, 847188Sgblack@eecs.umich.edu "op1": op1 } 857188Sgblack@eecs.umich.edu if useDest: 867188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 877188Sgblack@eecs.umich.edu else: 887188Sgblack@eecs.umich.edu substDict["pclr"] = "" 897188Sgblack@eecs.umich.edu return instDecode % substDict 907139Sgblack@eecs.umich.edu 917139Sgblack@eecs.umich.edu decode_block = ''' 927139Sgblack@eecs.umich.edu { 937139Sgblack@eecs.umich.edu const bool immShift = (bits(machInst, 4) == 0); 947139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 957139Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 967139Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 977139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 987139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 997139Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 1007139Sgblack@eecs.umich.edu const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 1017139Sgblack@eecs.umich.edu switch (OPCODE) { 1027139Sgblack@eecs.umich.edu ''' 1037139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 1047139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 1057139Sgblack@eecs.umich.edu decode_block += instCode(0x2, "sub") 1067139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 1077139Sgblack@eecs.umich.edu decode_block += instCode(0x4, "add") 1087139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 1097139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 1107139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 1117188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 1127188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 1137188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 1147188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 1157139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 1167188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 1177139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 1187188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 1197139Sgblack@eecs.umich.edu decode_block += ''' 1207139Sgblack@eecs.umich.edu default: 1217139Sgblack@eecs.umich.edu return new Unknown(machInst); 1227139Sgblack@eecs.umich.edu } 1237139Sgblack@eecs.umich.edu } 1247139Sgblack@eecs.umich.edu ''' 1257139Sgblack@eecs.umich.edu}}; 1267139Sgblack@eecs.umich.edu 1277139Sgblack@eecs.umich.edudef format ArmDataProcImm() {{ 1287188Sgblack@eecs.umich.edu pclr = ''' 1297188Sgblack@eecs.umich.edu return new %(className)ssImmPclr(machInst, %(dest)s, 1307188Sgblack@eecs.umich.edu %(op1)s, imm, false); 1317188Sgblack@eecs.umich.edu ''' 1327188Sgblack@eecs.umich.edu adr = ''' 1337188Sgblack@eecs.umich.edu return new AdrImm(machInst, %(dest)s, %(add)s, 1347188Sgblack@eecs.umich.edu imm, false); 1357188Sgblack@eecs.umich.edu ''' 1367139Sgblack@eecs.umich.edu instDecode = ''' 1377188Sgblack@eecs.umich.edu case %(opcode)#x: 1387139Sgblack@eecs.umich.edu if (setCc) { 1397188Sgblack@eecs.umich.edu if (%(pclrInst)s && %(dest)s == INTREG_PC) { 1407188Sgblack@eecs.umich.edu %(pclr)s 1417188Sgblack@eecs.umich.edu } else { 1427188Sgblack@eecs.umich.edu return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 1437188Sgblack@eecs.umich.edu imm, rotC); 1447188Sgblack@eecs.umich.edu } 1457139Sgblack@eecs.umich.edu } else { 1467188Sgblack@eecs.umich.edu if (%(adrInst)s && %(op1)s == INTREG_PC) { 1477188Sgblack@eecs.umich.edu %(adr)s 1487188Sgblack@eecs.umich.edu } else { 1497188Sgblack@eecs.umich.edu return new %(className)sImm(machInst, %(dest)s, %(op1)s, 1507188Sgblack@eecs.umich.edu imm, rotC); 1517188Sgblack@eecs.umich.edu } 1527139Sgblack@eecs.umich.edu } 1537139Sgblack@eecs.umich.edu break; 1547139Sgblack@eecs.umich.edu ''' 1557139Sgblack@eecs.umich.edu 1567188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 1577188Sgblack@eecs.umich.edu global instDecode, pclr, adr 1587188Sgblack@eecs.umich.edu if useDest: 1597188Sgblack@eecs.umich.edu dest = "rd" 1607188Sgblack@eecs.umich.edu else: 1617188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 1627188Sgblack@eecs.umich.edu if useOp1: 1637188Sgblack@eecs.umich.edu op1 = "rn" 1647188Sgblack@eecs.umich.edu else: 1657188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 1667188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 1677188Sgblack@eecs.umich.edu "opcode": opcode, 1687188Sgblack@eecs.umich.edu "dest": dest, 1697188Sgblack@eecs.umich.edu "op1": op1, 1707188Sgblack@eecs.umich.edu "adr": "", 1717188Sgblack@eecs.umich.edu "adrInst": "false" } 1727188Sgblack@eecs.umich.edu if useDest: 1737188Sgblack@eecs.umich.edu substDict["pclrInst"] = "true" 1747188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 1757188Sgblack@eecs.umich.edu else: 1767188Sgblack@eecs.umich.edu substDict["pclrInst"] = "false" 1777188Sgblack@eecs.umich.edu substDict["pclr"] = "" 1787188Sgblack@eecs.umich.edu return instDecode % substDict 1797185Sgblack@eecs.umich.edu 1807188Sgblack@eecs.umich.edu def adrCode(opcode, mnem, add="1"): 1817188Sgblack@eecs.umich.edu global instDecode, pclr, adr 1827188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 1837188Sgblack@eecs.umich.edu "opcode": opcode, 1847188Sgblack@eecs.umich.edu "dest": "rd", 1857188Sgblack@eecs.umich.edu "op1": "rn", 1867188Sgblack@eecs.umich.edu "add": add, 1877188Sgblack@eecs.umich.edu "pclrInst": "true", 1887188Sgblack@eecs.umich.edu "adrInst": "true" } 1897188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 1907188Sgblack@eecs.umich.edu substDict["adr"] = adr % substDict 1917188Sgblack@eecs.umich.edu return instDecode % substDict 1927139Sgblack@eecs.umich.edu 1937139Sgblack@eecs.umich.edu decode_block = ''' 1947139Sgblack@eecs.umich.edu { 1957139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 1967139Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 1977139Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 1987139Sgblack@eecs.umich.edu const bool rotC = (rotation != 0); 1997139Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 2007139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 2017139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 2027139Sgblack@eecs.umich.edu switch (OPCODE) { 2037139Sgblack@eecs.umich.edu ''' 2047139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 2057139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 2067185Sgblack@eecs.umich.edu decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 2077139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 2087185Sgblack@eecs.umich.edu decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 2097139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 2107139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 2117139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 2127188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 2137188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 2147188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 2157188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 2167139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 2177188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 2187139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 2197188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 2207139Sgblack@eecs.umich.edu decode_block += ''' 2217139Sgblack@eecs.umich.edu default: 2227139Sgblack@eecs.umich.edu return new Unknown(machInst); 2237139Sgblack@eecs.umich.edu } 2247139Sgblack@eecs.umich.edu } 2257139Sgblack@eecs.umich.edu ''' 2267139Sgblack@eecs.umich.edu}}; 2277141Sgblack@eecs.umich.edu 2287141Sgblack@eecs.umich.edudef format Thumb16ShiftAddSubMoveCmp() {{ 2297141Sgblack@eecs.umich.edu decode_block = ''' 2307141Sgblack@eecs.umich.edu { 2317141Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 10, 6); 2327141Sgblack@eecs.umich.edu const uint32_t imm3 = bits(machInst, 8, 6); 2337141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 2347141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 2357141Sgblack@eecs.umich.edu const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 2367141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 2377141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 2387141Sgblack@eecs.umich.edu switch (bits(machInst, 13, 11)) { 2397141Sgblack@eecs.umich.edu case 0x0: // lsl 2407183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 2417141Sgblack@eecs.umich.edu case 0x1: // lsr 2427183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 2437141Sgblack@eecs.umich.edu case 0x2: // asr 2447183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 2457141Sgblack@eecs.umich.edu case 0x3: 2467141Sgblack@eecs.umich.edu switch (bits(machInst, 10, 9)) { 2477141Sgblack@eecs.umich.edu case 0x0: 2487183Sgblack@eecs.umich.edu return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 2497141Sgblack@eecs.umich.edu case 0x1: 2507183Sgblack@eecs.umich.edu return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 2517141Sgblack@eecs.umich.edu case 0x2: 2527183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd, rn, imm3, true); 2537141Sgblack@eecs.umich.edu case 0x3: 2547183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd, rn, imm3, true); 2557141Sgblack@eecs.umich.edu } 2567141Sgblack@eecs.umich.edu case 0x4: 2577183Sgblack@eecs.umich.edu return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 2587141Sgblack@eecs.umich.edu case 0x5: 2597146Sgblack@eecs.umich.edu return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 2607141Sgblack@eecs.umich.edu case 0x6: 2617183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd8, rd8, imm8, true); 2627141Sgblack@eecs.umich.edu case 0x7: 2637183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd8, rd8, imm8, true); 2647141Sgblack@eecs.umich.edu } 2657141Sgblack@eecs.umich.edu } 2667141Sgblack@eecs.umich.edu ''' 2677141Sgblack@eecs.umich.edu}}; 2687141Sgblack@eecs.umich.edu 2697141Sgblack@eecs.umich.edudef format Thumb16DataProcessing() {{ 2707141Sgblack@eecs.umich.edu decode_block = ''' 2717141Sgblack@eecs.umich.edu { 2727141Sgblack@eecs.umich.edu const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 2737141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 2747141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 6)) { 2757141Sgblack@eecs.umich.edu case 0x0: 2767183Sgblack@eecs.umich.edu return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 2777141Sgblack@eecs.umich.edu case 0x1: 2787183Sgblack@eecs.umich.edu return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 2797141Sgblack@eecs.umich.edu case 0x2: //lsl 2807183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL); 2817141Sgblack@eecs.umich.edu case 0x3: //lsr 2827183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR); 2837141Sgblack@eecs.umich.edu case 0x4: //asr 2847183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR); 2857141Sgblack@eecs.umich.edu case 0x5: 2867183Sgblack@eecs.umich.edu return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 2877141Sgblack@eecs.umich.edu case 0x6: 2887183Sgblack@eecs.umich.edu return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 2897141Sgblack@eecs.umich.edu case 0x7: // ror 2907183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR); 2917141Sgblack@eecs.umich.edu case 0x8: 2927183Sgblack@eecs.umich.edu return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 2937141Sgblack@eecs.umich.edu case 0x9: 2947183Sgblack@eecs.umich.edu return new RsbImmCc(machInst, rdn, rm, 0, true); 2957141Sgblack@eecs.umich.edu case 0xa: 2967183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 2977141Sgblack@eecs.umich.edu case 0xb: 2987183Sgblack@eecs.umich.edu return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 2997141Sgblack@eecs.umich.edu case 0xc: 3007183Sgblack@eecs.umich.edu return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 3017141Sgblack@eecs.umich.edu case 0xd: 3027183Sgblack@eecs.umich.edu return new MulCc(machInst, rdn, rm, rdn); 3037141Sgblack@eecs.umich.edu case 0xe: 3047183Sgblack@eecs.umich.edu return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 3057141Sgblack@eecs.umich.edu case 0xf: 3067183Sgblack@eecs.umich.edu return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 3077141Sgblack@eecs.umich.edu } 3087141Sgblack@eecs.umich.edu } 3097141Sgblack@eecs.umich.edu ''' 3107141Sgblack@eecs.umich.edu}}; 3117141Sgblack@eecs.umich.edu 3127141Sgblack@eecs.umich.edudef format Thumb16SpecDataAndBx() {{ 3137141Sgblack@eecs.umich.edu decode_block = ''' 3147141Sgblack@eecs.umich.edu { 3157141Sgblack@eecs.umich.edu const IntRegIndex rdn = 3167141Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 3177141Sgblack@eecs.umich.edu (bits(machInst, 7) << 3)); 3187141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 3197141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 8)) { 3207141Sgblack@eecs.umich.edu case 0x0: 3217146Sgblack@eecs.umich.edu return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 3227141Sgblack@eecs.umich.edu case 0x1: 3237183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 3247141Sgblack@eecs.umich.edu case 0x2: 3257146Sgblack@eecs.umich.edu return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 3267141Sgblack@eecs.umich.edu case 0x3: 3277154Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 3287154Sgblack@eecs.umich.edu return new BxReg(machInst, 3297154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 3307154Sgblack@eecs.umich.edu COND_UC); 3317154Sgblack@eecs.umich.edu } else { 3327154Sgblack@eecs.umich.edu return new BlxReg(machInst, 3337154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 3347154Sgblack@eecs.umich.edu COND_UC); 3357154Sgblack@eecs.umich.edu } 3367141Sgblack@eecs.umich.edu } 3377141Sgblack@eecs.umich.edu } 3387141Sgblack@eecs.umich.edu ''' 3397141Sgblack@eecs.umich.edu}}; 3407141Sgblack@eecs.umich.edu 3417141Sgblack@eecs.umich.edudef format Thumb16Adr() {{ 3427141Sgblack@eecs.umich.edu decode_block = ''' 3437141Sgblack@eecs.umich.edu { 3447141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 3457141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 3467185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 3477141Sgblack@eecs.umich.edu } 3487141Sgblack@eecs.umich.edu ''' 3497141Sgblack@eecs.umich.edu}}; 3507141Sgblack@eecs.umich.edu 3517141Sgblack@eecs.umich.edudef format Thumb16AddSp() {{ 3527141Sgblack@eecs.umich.edu decode_block = ''' 3537141Sgblack@eecs.umich.edu { 3547141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 3557141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 3567146Sgblack@eecs.umich.edu return new AddImm(machInst, rd, INTREG_SP, imm8, true); 3577141Sgblack@eecs.umich.edu } 3587141Sgblack@eecs.umich.edu ''' 3597141Sgblack@eecs.umich.edu}}; 3607141Sgblack@eecs.umich.edu 3617141Sgblack@eecs.umich.edudef format Thumb16Misc() {{ 3627141Sgblack@eecs.umich.edu decode_block = ''' 3637141Sgblack@eecs.umich.edu { 3647141Sgblack@eecs.umich.edu switch (bits(machInst, 11, 8)) { 3657141Sgblack@eecs.umich.edu case 0x0: 3667141Sgblack@eecs.umich.edu if (bits(machInst, 7)) { 3677146Sgblack@eecs.umich.edu return new SubImm(machInst, INTREG_SP, INTREG_SP, 3687141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 3697141Sgblack@eecs.umich.edu } else { 3707146Sgblack@eecs.umich.edu return new AddImm(machInst, INTREG_SP, INTREG_SP, 3717141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 3727141Sgblack@eecs.umich.edu } 3737141Sgblack@eecs.umich.edu case 0x1: 3747154Sgblack@eecs.umich.edu return new Cbz(machInst, 3757154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 3767154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 3777154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 3787141Sgblack@eecs.umich.edu case 0x2: 3797141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 3807141Sgblack@eecs.umich.edu case 0x0: 3817141Sgblack@eecs.umich.edu return new WarnUnimplemented("sxth", machInst); 3827141Sgblack@eecs.umich.edu case 0x1: 3837141Sgblack@eecs.umich.edu return new WarnUnimplemented("sxtb", machInst); 3847141Sgblack@eecs.umich.edu case 0x2: 3857141Sgblack@eecs.umich.edu return new WarnUnimplemented("uxth", machInst); 3867141Sgblack@eecs.umich.edu case 0x3: 3877141Sgblack@eecs.umich.edu return new WarnUnimplemented("uxtb", machInst); 3887141Sgblack@eecs.umich.edu } 3897141Sgblack@eecs.umich.edu case 0x3: 3907154Sgblack@eecs.umich.edu return new Cbz(machInst, 3917154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 3927154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 3937154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 3947141Sgblack@eecs.umich.edu case 0x4: 3957141Sgblack@eecs.umich.edu case 0x5: 3967141Sgblack@eecs.umich.edu return new WarnUnimplemented("push", machInst); 3977141Sgblack@eecs.umich.edu case 0x6: 3987141Sgblack@eecs.umich.edu { 3997141Sgblack@eecs.umich.edu const uint32_t opBits = bits(machInst, 7, 5); 4007141Sgblack@eecs.umich.edu if (opBits == 2) { 4017141Sgblack@eecs.umich.edu return new WarnUnimplemented("setend", machInst); 4027141Sgblack@eecs.umich.edu } else if (opBits == 3) { 4037141Sgblack@eecs.umich.edu return new WarnUnimplemented("cps", machInst); 4047141Sgblack@eecs.umich.edu } 4057141Sgblack@eecs.umich.edu } 4067141Sgblack@eecs.umich.edu case 0x9: 4077154Sgblack@eecs.umich.edu return new Cbnz(machInst, 4087154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 4097154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 4107154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 4117141Sgblack@eecs.umich.edu case 0xa: 4127141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 5)) { 4137141Sgblack@eecs.umich.edu case 0x0: 4147141Sgblack@eecs.umich.edu return new WarnUnimplemented("rev", machInst); 4157141Sgblack@eecs.umich.edu case 0x1: 4167141Sgblack@eecs.umich.edu return new WarnUnimplemented("rev16", machInst); 4177141Sgblack@eecs.umich.edu case 0x3: 4187141Sgblack@eecs.umich.edu return new WarnUnimplemented("revsh", machInst); 4197141Sgblack@eecs.umich.edu default: 4207141Sgblack@eecs.umich.edu break; 4217141Sgblack@eecs.umich.edu } 4227141Sgblack@eecs.umich.edu break; 4237141Sgblack@eecs.umich.edu case 0xb: 4247154Sgblack@eecs.umich.edu return new Cbnz(machInst, 4257154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 4267154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 4277154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 4287141Sgblack@eecs.umich.edu case 0xc: 4297141Sgblack@eecs.umich.edu case 0xd: 4307141Sgblack@eecs.umich.edu return new WarnUnimplemented("pop", machInst); 4317141Sgblack@eecs.umich.edu case 0xe: 4327141Sgblack@eecs.umich.edu return new WarnUnimplemented("bkpt", machInst); 4337141Sgblack@eecs.umich.edu case 0xf: 4347141Sgblack@eecs.umich.edu if (bits(machInst, 3, 0) != 0) 4357141Sgblack@eecs.umich.edu return new WarnUnimplemented("it", machInst); 4367141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 4)) { 4377141Sgblack@eecs.umich.edu case 0x0: 4387141Sgblack@eecs.umich.edu return new WarnUnimplemented("nop", machInst); 4397141Sgblack@eecs.umich.edu case 0x1: 4407141Sgblack@eecs.umich.edu return new WarnUnimplemented("yield", machInst); 4417141Sgblack@eecs.umich.edu case 0x2: 4427141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfe", machInst); 4437141Sgblack@eecs.umich.edu case 0x3: 4447141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfi", machInst); 4457141Sgblack@eecs.umich.edu case 0x4: 4467141Sgblack@eecs.umich.edu return new WarnUnimplemented("sev", machInst); 4477141Sgblack@eecs.umich.edu default: 4487141Sgblack@eecs.umich.edu return new WarnUnimplemented("unallocated_hint", machInst); 4497141Sgblack@eecs.umich.edu } 4507141Sgblack@eecs.umich.edu default: 4517141Sgblack@eecs.umich.edu break; 4527141Sgblack@eecs.umich.edu } 4537141Sgblack@eecs.umich.edu return new Unknown(machInst); 4547141Sgblack@eecs.umich.edu } 4557141Sgblack@eecs.umich.edu ''' 4567141Sgblack@eecs.umich.edu}}; 4577141Sgblack@eecs.umich.edu 4587141Sgblack@eecs.umich.edudef format Thumb32DataProcModImm() {{ 4597141Sgblack@eecs.umich.edu 4607141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 4617141Sgblack@eecs.umich.edu return ''' 4627141Sgblack@eecs.umich.edu if (s) { 4637146Sgblack@eecs.umich.edu return new %(mnem)sImmCc(machInst, %(dest)s, 4647183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 4657141Sgblack@eecs.umich.edu } else { 4667146Sgblack@eecs.umich.edu return new %(mnem)sImm(machInst, %(dest)s, 4677183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 4687141Sgblack@eecs.umich.edu } 4697141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 4707141Sgblack@eecs.umich.edu 4717141Sgblack@eecs.umich.edu decode_block = ''' 4727141Sgblack@eecs.umich.edu { 4737141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 4747141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 4757141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 4767141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 4777141Sgblack@eecs.umich.edu const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 4787141Sgblack@eecs.umich.edu bits(machInst, 14, 12); 4797183Sgblack@eecs.umich.edu const bool rotC = ctrlImm > 3; 4807141Sgblack@eecs.umich.edu const uint32_t dataImm = bits(machInst, 7, 0); 4817141Sgblack@eecs.umich.edu const uint32_t imm = modified_imm(ctrlImm, dataImm); 4827141Sgblack@eecs.umich.edu switch (op) { 4837141Sgblack@eecs.umich.edu case 0x0: 4847141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 4857141Sgblack@eecs.umich.edu %(tst)s 4867141Sgblack@eecs.umich.edu } else { 4877141Sgblack@eecs.umich.edu %(and)s 4887141Sgblack@eecs.umich.edu } 4897141Sgblack@eecs.umich.edu case 0x1: 4907141Sgblack@eecs.umich.edu %(bic)s 4917141Sgblack@eecs.umich.edu case 0x2: 4927141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 4937141Sgblack@eecs.umich.edu %(mov)s 4947141Sgblack@eecs.umich.edu } else { 4957141Sgblack@eecs.umich.edu %(orr)s 4967141Sgblack@eecs.umich.edu } 4977141Sgblack@eecs.umich.edu case 0x3: 4987141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 4997141Sgblack@eecs.umich.edu %(mvn)s 5007141Sgblack@eecs.umich.edu } else { 5017141Sgblack@eecs.umich.edu %(orn)s 5027141Sgblack@eecs.umich.edu } 5037141Sgblack@eecs.umich.edu case 0x4: 5047141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 5057141Sgblack@eecs.umich.edu %(teq)s 5067141Sgblack@eecs.umich.edu } else { 5077141Sgblack@eecs.umich.edu %(eor)s 5087141Sgblack@eecs.umich.edu } 5097141Sgblack@eecs.umich.edu case 0x8: 5107141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 5117141Sgblack@eecs.umich.edu %(cmn)s 5127141Sgblack@eecs.umich.edu } else { 5137141Sgblack@eecs.umich.edu %(add)s 5147141Sgblack@eecs.umich.edu } 5157141Sgblack@eecs.umich.edu case 0xa: 5167141Sgblack@eecs.umich.edu %(adc)s 5177141Sgblack@eecs.umich.edu case 0xb: 5187141Sgblack@eecs.umich.edu %(sbc)s 5197141Sgblack@eecs.umich.edu case 0xd: 5207141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 5217141Sgblack@eecs.umich.edu %(cmp)s 5227141Sgblack@eecs.umich.edu } else { 5237141Sgblack@eecs.umich.edu %(sub)s 5247141Sgblack@eecs.umich.edu } 5257141Sgblack@eecs.umich.edu case 0xe: 5267141Sgblack@eecs.umich.edu %(rsb)s 5277141Sgblack@eecs.umich.edu default: 5287141Sgblack@eecs.umich.edu return new Unknown(machInst); 5297141Sgblack@eecs.umich.edu } 5307141Sgblack@eecs.umich.edu } 5317141Sgblack@eecs.umich.edu ''' % { 5327141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 5337141Sgblack@eecs.umich.edu "and" : decInst("And"), 5347141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 5357141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 5367141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 5377141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 5387141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 5397141Sgblack@eecs.umich.edu "teq" : decInst("Teq", dest="INTREG_ZERO"), 5407141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 5417141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 5427141Sgblack@eecs.umich.edu "add" : decInst("Add"), 5437141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 5447141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 5457141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 5467141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 5477141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 5487141Sgblack@eecs.umich.edu } 5497141Sgblack@eecs.umich.edu}}; 5507141Sgblack@eecs.umich.edu 5517157Sgblack@eecs.umich.edudef format Thumb32DataProcPlainBin() {{ 5527157Sgblack@eecs.umich.edu decode_block = ''' 5537157Sgblack@eecs.umich.edu { 5547157Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 20); 5557157Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5567157Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 5577157Sgblack@eecs.umich.edu switch (op) { 5587157Sgblack@eecs.umich.edu case 0x0: 5597157Sgblack@eecs.umich.edu { 5607157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 5617157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 5627157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 5637185Sgblack@eecs.umich.edu if (rn == 0xf) { 5647185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, 5657185Sgblack@eecs.umich.edu imm, false); 5667185Sgblack@eecs.umich.edu } else { 5677185Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm, true); 5687185Sgblack@eecs.umich.edu } 5697157Sgblack@eecs.umich.edu } 5707157Sgblack@eecs.umich.edu case 0x4: 5717157Sgblack@eecs.umich.edu { 5727157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 5737157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 5747157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 5757157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 5767157Sgblack@eecs.umich.edu return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 5777157Sgblack@eecs.umich.edu } 5787157Sgblack@eecs.umich.edu case 0xa: 5797157Sgblack@eecs.umich.edu { 5807157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 5817157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 5827157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 5837185Sgblack@eecs.umich.edu if (rn == 0xf) { 5847185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)0, 5857185Sgblack@eecs.umich.edu imm, false); 5867185Sgblack@eecs.umich.edu } else { 5877185Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm, true); 5887185Sgblack@eecs.umich.edu } 5897157Sgblack@eecs.umich.edu } 5907157Sgblack@eecs.umich.edu case 0xc: 5917157Sgblack@eecs.umich.edu { 5927157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 5937157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 5947157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 5957157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 5967157Sgblack@eecs.umich.edu return new MovtImm(machInst, rd, rd, imm, true); 5977157Sgblack@eecs.umich.edu } 5987157Sgblack@eecs.umich.edu case 0x12: 5997157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 6007157Sgblack@eecs.umich.edu return new WarnUnimplemented("ssat16", machInst); 6017157Sgblack@eecs.umich.edu } 6027157Sgblack@eecs.umich.edu // Fall through on purpose... 6037157Sgblack@eecs.umich.edu case 0x10: 6047157Sgblack@eecs.umich.edu return new WarnUnimplemented("ssat", machInst); 6057157Sgblack@eecs.umich.edu case 0x14: 6067157Sgblack@eecs.umich.edu return new WarnUnimplemented("sbfx", machInst); 6077157Sgblack@eecs.umich.edu case 0x16: 6087157Sgblack@eecs.umich.edu if (rn == 0xf) { 6097157Sgblack@eecs.umich.edu return new WarnUnimplemented("bfc", machInst); 6107157Sgblack@eecs.umich.edu } else { 6117157Sgblack@eecs.umich.edu return new WarnUnimplemented("bfi", machInst); 6127157Sgblack@eecs.umich.edu } 6137157Sgblack@eecs.umich.edu case 0x1a: 6147157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 6157157Sgblack@eecs.umich.edu return new WarnUnimplemented("usat16", machInst); 6167157Sgblack@eecs.umich.edu } 6177157Sgblack@eecs.umich.edu // Fall through on purpose... 6187157Sgblack@eecs.umich.edu case 0x18: 6197157Sgblack@eecs.umich.edu return new WarnUnimplemented("usat", machInst); 6207157Sgblack@eecs.umich.edu case 0x1c: 6217157Sgblack@eecs.umich.edu return new WarnUnimplemented("ubfx", machInst); 6227157Sgblack@eecs.umich.edu default: 6237157Sgblack@eecs.umich.edu return new Unknown(machInst); 6247157Sgblack@eecs.umich.edu } 6257157Sgblack@eecs.umich.edu } 6267157Sgblack@eecs.umich.edu ''' 6277157Sgblack@eecs.umich.edu}}; 6287157Sgblack@eecs.umich.edu 6297141Sgblack@eecs.umich.edudef format Thumb32DataProcShiftReg() {{ 6307141Sgblack@eecs.umich.edu 6317141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 6327141Sgblack@eecs.umich.edu return ''' 6337141Sgblack@eecs.umich.edu if (s) { 6347146Sgblack@eecs.umich.edu return new %(mnem)sRegCc(machInst, %(dest)s, 6357141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 6367141Sgblack@eecs.umich.edu } else { 6377146Sgblack@eecs.umich.edu return new %(mnem)sReg(machInst, %(dest)s, 6387141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 6397141Sgblack@eecs.umich.edu } 6407141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 6417141Sgblack@eecs.umich.edu 6427141Sgblack@eecs.umich.edu decode_block = ''' 6437141Sgblack@eecs.umich.edu { 6447141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 6457141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 6467141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 6477141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6487141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6497141Sgblack@eecs.umich.edu const uint32_t amt = (bits(machInst, 14, 12) << 2) | 6507141Sgblack@eecs.umich.edu bits(machInst, 7, 6); 6517141Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 6527141Sgblack@eecs.umich.edu switch (op) { 6537141Sgblack@eecs.umich.edu case 0x0: 6547141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 6557141Sgblack@eecs.umich.edu %(tst)s 6567141Sgblack@eecs.umich.edu } else { 6577141Sgblack@eecs.umich.edu %(and)s 6587141Sgblack@eecs.umich.edu } 6597141Sgblack@eecs.umich.edu case 0x1: 6607141Sgblack@eecs.umich.edu %(bic)s 6617141Sgblack@eecs.umich.edu case 0x2: 6627141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 6637141Sgblack@eecs.umich.edu %(mov)s 6647141Sgblack@eecs.umich.edu } else { 6657141Sgblack@eecs.umich.edu %(orr)s 6667141Sgblack@eecs.umich.edu } 6677141Sgblack@eecs.umich.edu case 0x3: 6687141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 6697141Sgblack@eecs.umich.edu %(mvn)s 6707141Sgblack@eecs.umich.edu } else { 6717141Sgblack@eecs.umich.edu %(orn)s 6727141Sgblack@eecs.umich.edu } 6737141Sgblack@eecs.umich.edu case 0x4: 6747141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 6757141Sgblack@eecs.umich.edu %(teq)s 6767141Sgblack@eecs.umich.edu } else { 6777141Sgblack@eecs.umich.edu %(eor)s 6787141Sgblack@eecs.umich.edu } 6797141Sgblack@eecs.umich.edu case 0x6: 6807141Sgblack@eecs.umich.edu return new WarnUnimplemented("pkh", machInst); 6817141Sgblack@eecs.umich.edu case 0x8: 6827141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 6837141Sgblack@eecs.umich.edu %(cmn)s 6847141Sgblack@eecs.umich.edu } else { 6857141Sgblack@eecs.umich.edu %(add)s 6867141Sgblack@eecs.umich.edu } 6877141Sgblack@eecs.umich.edu case 0xa: 6887141Sgblack@eecs.umich.edu %(adc)s 6897141Sgblack@eecs.umich.edu case 0xb: 6907141Sgblack@eecs.umich.edu %(sbc)s 6917141Sgblack@eecs.umich.edu case 0xd: 6927141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 6937141Sgblack@eecs.umich.edu %(cmp)s 6947141Sgblack@eecs.umich.edu } else { 6957141Sgblack@eecs.umich.edu %(sub)s 6967141Sgblack@eecs.umich.edu } 6977141Sgblack@eecs.umich.edu case 0xe: 6987141Sgblack@eecs.umich.edu %(rsb)s 6997141Sgblack@eecs.umich.edu default: 7007141Sgblack@eecs.umich.edu return new Unknown(machInst); 7017141Sgblack@eecs.umich.edu } 7027141Sgblack@eecs.umich.edu } 7037141Sgblack@eecs.umich.edu ''' % { 7047141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 7057141Sgblack@eecs.umich.edu "and" : decInst("And"), 7067141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 7077141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 7087141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 7097141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 7107141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 7117141Sgblack@eecs.umich.edu "teq" : decInst("Teq", "INTREG_ZERO"), 7127141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 7137141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", "INTREG_ZERO"), 7147141Sgblack@eecs.umich.edu "add" : decInst("Add"), 7157141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 7167141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 7177141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", "INTREG_ZERO"), 7187141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 7197141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 7207141Sgblack@eecs.umich.edu } 7217141Sgblack@eecs.umich.edu}}; 722