data.isa revision 14031
112542Sgiacomo.travaglini@arm.com// Copyright (c) 2010,2017-2018 ARM Limited 27139Sgblack@eecs.umich.edu// All rights reserved 37139Sgblack@eecs.umich.edu// 47139Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 57139Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 67139Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 77139Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 87139Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 97139Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 107139Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 117139Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 127139Sgblack@eecs.umich.edu// 137139Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 147139Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 157139Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 167139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 177139Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 187139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 197139Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 207139Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 217139Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227139Sgblack@eecs.umich.edu// this software without specific prior written permission. 237139Sgblack@eecs.umich.edu// 247139Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 257139Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267139Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277139Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287139Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 297139Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317139Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327139Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 337139Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 347139Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357139Sgblack@eecs.umich.edu// 367139Sgblack@eecs.umich.edu// Authors: Gabe Black 377139Sgblack@eecs.umich.edu 387255Sgblack@eecs.umich.edudef format ArmMiscMedia() {{ 397243Sgblack@eecs.umich.edu decode_block = ''' 407243Sgblack@eecs.umich.edu { 417255Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 427255Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 437243Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 447243Sgblack@eecs.umich.edu const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 457255Sgblack@eecs.umich.edu if (op1 == 0 && op2 == 0) { 467255Sgblack@eecs.umich.edu const IntRegIndex rd = 477255Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 487255Sgblack@eecs.umich.edu const IntRegIndex rm = 497255Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 507255Sgblack@eecs.umich.edu if (ra == 0xf) { 517255Sgblack@eecs.umich.edu return new Usad8(machInst, rd, rn, rm); 527255Sgblack@eecs.umich.edu } else { 537255Sgblack@eecs.umich.edu return new Usada8(machInst, rd, rn, rm, ra); 547255Sgblack@eecs.umich.edu } 557255Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x2) { 567256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 11, 7); 577256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 20, 16); 587255Sgblack@eecs.umich.edu if (bits(op1, 2, 1) == 0x3) { 597256Sgblack@eecs.umich.edu return new Ubfx(machInst, ra, rn, lsb, msb); 607255Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 0x1) { 617256Sgblack@eecs.umich.edu return new Sbfx(machInst, ra, rn, lsb, msb); 627255Sgblack@eecs.umich.edu } 637255Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) { 647258Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 11, 7); 657258Sgblack@eecs.umich.edu const uint32_t msb = bits(machInst, 20, 16); 667255Sgblack@eecs.umich.edu if (rn == 0xf) { 677258Sgblack@eecs.umich.edu return new Bfc(machInst, ra, ra, lsb, msb); 687255Sgblack@eecs.umich.edu } else { 697258Sgblack@eecs.umich.edu return new Bfi(machInst, ra, rn, lsb, msb); 707255Sgblack@eecs.umich.edu } 717243Sgblack@eecs.umich.edu } 727255Sgblack@eecs.umich.edu return new Unknown(machInst); 737243Sgblack@eecs.umich.edu } 747243Sgblack@eecs.umich.edu ''' 757243Sgblack@eecs.umich.edu}}; 767243Sgblack@eecs.umich.edu 777139Sgblack@eecs.umich.edudef format ArmDataProcReg() {{ 787188Sgblack@eecs.umich.edu pclr = ''' 7912595Ssiddhesh.poyarekar@gmail.com if (%(dest)s == INTREG_PC) { 8012595Ssiddhesh.poyarekar@gmail.com return new %(className)ssRegPclr(machInst, %(dest)s, 8112595Ssiddhesh.poyarekar@gmail.com %(op1)s, rm, imm5, 8212595Ssiddhesh.poyarekar@gmail.com type); 8312595Ssiddhesh.poyarekar@gmail.com } else 847188Sgblack@eecs.umich.edu ''' 857139Sgblack@eecs.umich.edu instDecode = ''' 867139Sgblack@eecs.umich.edu case %(opcode)#x: 877139Sgblack@eecs.umich.edu if (immShift) { 887139Sgblack@eecs.umich.edu if (setCc) { 8912595Ssiddhesh.poyarekar@gmail.com %(pclr)s { 907188Sgblack@eecs.umich.edu return new %(className)sRegCc(machInst, %(dest)s, 917188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, type); 927188Sgblack@eecs.umich.edu } 937139Sgblack@eecs.umich.edu } else { 947146Sgblack@eecs.umich.edu return new %(className)sReg(machInst, %(dest)s, %(op1)s, 957141Sgblack@eecs.umich.edu rm, imm5, type); 967139Sgblack@eecs.umich.edu } 977139Sgblack@eecs.umich.edu } else { 987139Sgblack@eecs.umich.edu if (setCc) { 997146Sgblack@eecs.umich.edu return new %(className)sRegRegCc(machInst, %(dest)s, 1007141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 1017139Sgblack@eecs.umich.edu } else { 1027146Sgblack@eecs.umich.edu return new %(className)sRegReg(machInst, %(dest)s, 1037141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 1047139Sgblack@eecs.umich.edu } 1057139Sgblack@eecs.umich.edu } 1067139Sgblack@eecs.umich.edu break; 1077139Sgblack@eecs.umich.edu ''' 1087139Sgblack@eecs.umich.edu 1097188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 1107188Sgblack@eecs.umich.edu global pclr 1117188Sgblack@eecs.umich.edu if useDest: 1127188Sgblack@eecs.umich.edu dest = "rd" 1137188Sgblack@eecs.umich.edu else: 1147188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 1157188Sgblack@eecs.umich.edu if useOp1: 1167188Sgblack@eecs.umich.edu op1 = "rn" 1177188Sgblack@eecs.umich.edu else: 1187188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 1197188Sgblack@eecs.umich.edu global instDecode, pclrCode 1207188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 1217188Sgblack@eecs.umich.edu "opcode": opcode, 1227188Sgblack@eecs.umich.edu "dest": dest, 1237188Sgblack@eecs.umich.edu "op1": op1 } 1247188Sgblack@eecs.umich.edu if useDest: 1257188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 1267188Sgblack@eecs.umich.edu else: 1277188Sgblack@eecs.umich.edu substDict["pclr"] = "" 1287188Sgblack@eecs.umich.edu return instDecode % substDict 1297139Sgblack@eecs.umich.edu 1307139Sgblack@eecs.umich.edu decode_block = ''' 1317139Sgblack@eecs.umich.edu { 1327139Sgblack@eecs.umich.edu const bool immShift = (bits(machInst, 4) == 0); 1337139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 1347139Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 1357139Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1367139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 1377139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 1387139Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 1397139Sgblack@eecs.umich.edu const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 1407139Sgblack@eecs.umich.edu switch (OPCODE) { 1417139Sgblack@eecs.umich.edu ''' 1427139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 1437139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 1447139Sgblack@eecs.umich.edu decode_block += instCode(0x2, "sub") 1457139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 1467139Sgblack@eecs.umich.edu decode_block += instCode(0x4, "add") 1477139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 1487139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 1497139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 1507188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 1517188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 1527188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 1537188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 1547139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 1557188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 1567139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 1577188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 1587139Sgblack@eecs.umich.edu decode_block += ''' 1597139Sgblack@eecs.umich.edu default: 1607139Sgblack@eecs.umich.edu return new Unknown(machInst); 1617139Sgblack@eecs.umich.edu } 1627139Sgblack@eecs.umich.edu } 1637139Sgblack@eecs.umich.edu ''' 1647139Sgblack@eecs.umich.edu}}; 1657139Sgblack@eecs.umich.edu 1667210Sgblack@eecs.umich.edudef format ArmPackUnpackSatReverse() {{ 1677210Sgblack@eecs.umich.edu decode_block = ''' 1687210Sgblack@eecs.umich.edu { 1697210Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 1707210Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 19, 16); 1717210Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 1727210Sgblack@eecs.umich.edu if (bits(op2, 0) == 0) { 1737227Sgblack@eecs.umich.edu const IntRegIndex rn = 1747227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1757227Sgblack@eecs.umich.edu const IntRegIndex rd = 1767227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1777227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 1787227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 11, 7); 1797227Sgblack@eecs.umich.edu const ArmShiftType type = 1807227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1817210Sgblack@eecs.umich.edu if (op1 == 0) { 1827237Sgblack@eecs.umich.edu if (type) { 1837237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, (IntRegIndex)a, 1847237Sgblack@eecs.umich.edu rn, imm, type); 1857237Sgblack@eecs.umich.edu } else { 1867237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, (IntRegIndex)a, 1877237Sgblack@eecs.umich.edu rn, imm, type); 1887237Sgblack@eecs.umich.edu } 1897210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 1) { 1907227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 1917210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 3) { 1927227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 1937210Sgblack@eecs.umich.edu } 1947210Sgblack@eecs.umich.edu return new Unknown(machInst); 1957210Sgblack@eecs.umich.edu } 1967210Sgblack@eecs.umich.edu switch (op1) { 1977210Sgblack@eecs.umich.edu case 0x0: 1987240Sgblack@eecs.umich.edu { 1997235Sgblack@eecs.umich.edu const IntRegIndex rn = 2007235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2017235Sgblack@eecs.umich.edu const IntRegIndex rd = 2027235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2037235Sgblack@eecs.umich.edu const IntRegIndex rm = 2047235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2057240Sgblack@eecs.umich.edu if (op2 == 0x3) { 2067240Sgblack@eecs.umich.edu const uint32_t rotation = 2077240Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2087240Sgblack@eecs.umich.edu if (a == 0xf) { 2097240Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 2107240Sgblack@eecs.umich.edu } else { 2117240Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 2127240Sgblack@eecs.umich.edu } 2137240Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2147240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 2157210Sgblack@eecs.umich.edu } 2167210Sgblack@eecs.umich.edu } 2177210Sgblack@eecs.umich.edu break; 2187210Sgblack@eecs.umich.edu case 0x2: 2197210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2207227Sgblack@eecs.umich.edu const IntRegIndex rn = 2217227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2227227Sgblack@eecs.umich.edu const IntRegIndex rd = 2237227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2247227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2257227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 2267210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2277235Sgblack@eecs.umich.edu const IntRegIndex rn = 2287235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2297235Sgblack@eecs.umich.edu const IntRegIndex rd = 2307235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2317235Sgblack@eecs.umich.edu const IntRegIndex rm = 2327235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2337235Sgblack@eecs.umich.edu const uint32_t rotation = 2347235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2357210Sgblack@eecs.umich.edu if (a == 0xf) { 2367235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 2377210Sgblack@eecs.umich.edu } else { 2387235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 2397210Sgblack@eecs.umich.edu } 2407210Sgblack@eecs.umich.edu } 2417210Sgblack@eecs.umich.edu break; 2427210Sgblack@eecs.umich.edu case 0x3: 2437210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2447211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2457211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2467211Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 2477210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2487235Sgblack@eecs.umich.edu const IntRegIndex rn = 2497235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2507235Sgblack@eecs.umich.edu const IntRegIndex rd = 2517235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2527235Sgblack@eecs.umich.edu const IntRegIndex rm = 2537235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2547235Sgblack@eecs.umich.edu const uint32_t rotation = 2557235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2567210Sgblack@eecs.umich.edu if (a == 0xf) { 2577235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 2587210Sgblack@eecs.umich.edu } else { 2597235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 2607210Sgblack@eecs.umich.edu } 2617210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2627211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2637211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2647211Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 2657210Sgblack@eecs.umich.edu } 2667210Sgblack@eecs.umich.edu break; 2677210Sgblack@eecs.umich.edu case 0x4: 2687210Sgblack@eecs.umich.edu if (op2 == 0x3) { 2697235Sgblack@eecs.umich.edu const IntRegIndex rn = 2707235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2717235Sgblack@eecs.umich.edu const IntRegIndex rd = 2727235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2737235Sgblack@eecs.umich.edu const IntRegIndex rm = 2747235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2757235Sgblack@eecs.umich.edu const uint32_t rotation = 2767235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2777210Sgblack@eecs.umich.edu if (a == 0xf) { 2787235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 2797210Sgblack@eecs.umich.edu } else { 2807235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 2817210Sgblack@eecs.umich.edu } 2827210Sgblack@eecs.umich.edu } 2837210Sgblack@eecs.umich.edu break; 2847210Sgblack@eecs.umich.edu case 0x6: 2857210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2867227Sgblack@eecs.umich.edu const IntRegIndex rn = 2877227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2887227Sgblack@eecs.umich.edu const IntRegIndex rd = 2897227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2907227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2917227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 2927210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2937235Sgblack@eecs.umich.edu const IntRegIndex rn = 2947235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2957235Sgblack@eecs.umich.edu const IntRegIndex rd = 2967235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2977235Sgblack@eecs.umich.edu const IntRegIndex rm = 2987235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2997235Sgblack@eecs.umich.edu const uint32_t rotation = 3007235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 3017210Sgblack@eecs.umich.edu if (a == 0xf) { 3027235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 3037210Sgblack@eecs.umich.edu } else { 3047235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 3057210Sgblack@eecs.umich.edu } 3067210Sgblack@eecs.umich.edu } 3077210Sgblack@eecs.umich.edu break; 3087210Sgblack@eecs.umich.edu case 0x7: 3097250Sgblack@eecs.umich.edu { 3107235Sgblack@eecs.umich.edu const IntRegIndex rn = 3117235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3127235Sgblack@eecs.umich.edu const IntRegIndex rd = 3137235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3147235Sgblack@eecs.umich.edu const IntRegIndex rm = 3157235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3167250Sgblack@eecs.umich.edu if (op2 == 0x1) { 3177250Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 3187250Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 3197250Sgblack@eecs.umich.edu const uint32_t rotation = 3207250Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 3217250Sgblack@eecs.umich.edu if (a == 0xf) { 3227250Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 3237250Sgblack@eecs.umich.edu } else { 3247250Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 3257250Sgblack@eecs.umich.edu } 3267250Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 3277250Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 3287210Sgblack@eecs.umich.edu } 3297210Sgblack@eecs.umich.edu } 3307210Sgblack@eecs.umich.edu break; 3317210Sgblack@eecs.umich.edu } 3327210Sgblack@eecs.umich.edu return new Unknown(machInst); 3337210Sgblack@eecs.umich.edu } 3347210Sgblack@eecs.umich.edu ''' 3357210Sgblack@eecs.umich.edu}}; 3367210Sgblack@eecs.umich.edu 3377194Sgblack@eecs.umich.edudef format ArmParallelAddSubtract() {{ 3387194Sgblack@eecs.umich.edu decode_block=''' 3397194Sgblack@eecs.umich.edu { 3407194Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 3417194Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 3427194Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3437194Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3447194Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3457194Sgblack@eecs.umich.edu if (bits(machInst, 22) == 0) { 3467194Sgblack@eecs.umich.edu switch (op1) { 3477194Sgblack@eecs.umich.edu case 0x1: 3487194Sgblack@eecs.umich.edu switch (op2) { 3497194Sgblack@eecs.umich.edu case 0x0: 3507216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3517194Sgblack@eecs.umich.edu case 0x1: 3527224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); 3537194Sgblack@eecs.umich.edu case 0x2: 3547224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); 3557194Sgblack@eecs.umich.edu case 0x3: 3567218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); 3577194Sgblack@eecs.umich.edu case 0x4: 3587216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 3597194Sgblack@eecs.umich.edu case 0x7: 3607218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); 3617194Sgblack@eecs.umich.edu } 3627194Sgblack@eecs.umich.edu break; 3637194Sgblack@eecs.umich.edu case 0x2: 3647194Sgblack@eecs.umich.edu switch (op2) { 3657194Sgblack@eecs.umich.edu case 0x0: 3667194Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 3677194Sgblack@eecs.umich.edu case 0x1: 3687194Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 3697194Sgblack@eecs.umich.edu case 0x2: 3707194Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 3717194Sgblack@eecs.umich.edu case 0x3: 3727194Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 3737194Sgblack@eecs.umich.edu case 0x4: 3747194Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 3757194Sgblack@eecs.umich.edu case 0x7: 3767194Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 3777194Sgblack@eecs.umich.edu } 3787194Sgblack@eecs.umich.edu break; 3797194Sgblack@eecs.umich.edu case 0x3: 3807194Sgblack@eecs.umich.edu switch (op2) { 3817194Sgblack@eecs.umich.edu case 0x0: 3827231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 3837194Sgblack@eecs.umich.edu case 0x1: 3847231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 3857194Sgblack@eecs.umich.edu case 0x2: 3867231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 3877194Sgblack@eecs.umich.edu case 0x3: 3887231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 3897194Sgblack@eecs.umich.edu case 0x4: 3907231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 3917194Sgblack@eecs.umich.edu case 0x7: 3927231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 3937194Sgblack@eecs.umich.edu } 3947194Sgblack@eecs.umich.edu break; 3957194Sgblack@eecs.umich.edu } 3967194Sgblack@eecs.umich.edu } else { 3977194Sgblack@eecs.umich.edu switch (op1) { 3987194Sgblack@eecs.umich.edu case 0x1: 3997194Sgblack@eecs.umich.edu switch (op2) { 4007194Sgblack@eecs.umich.edu case 0x0: 4017222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL); 4027194Sgblack@eecs.umich.edu case 0x1: 4037222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, rn, rm, 0, LSL); 4047194Sgblack@eecs.umich.edu case 0x2: 4057222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL); 4067194Sgblack@eecs.umich.edu case 0x3: 4077222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL); 4087194Sgblack@eecs.umich.edu case 0x4: 4097222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL); 4107194Sgblack@eecs.umich.edu case 0x7: 4117222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL); 4127194Sgblack@eecs.umich.edu } 4137194Sgblack@eecs.umich.edu break; 4147194Sgblack@eecs.umich.edu case 0x2: 4157194Sgblack@eecs.umich.edu switch (op2) { 4167194Sgblack@eecs.umich.edu case 0x0: 4177220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 4187194Sgblack@eecs.umich.edu case 0x1: 4197220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 4207194Sgblack@eecs.umich.edu case 0x2: 4217220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 4227194Sgblack@eecs.umich.edu case 0x3: 4237220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 4247194Sgblack@eecs.umich.edu case 0x4: 4257220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 4267194Sgblack@eecs.umich.edu case 0x7: 4277220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 4287194Sgblack@eecs.umich.edu } 4297194Sgblack@eecs.umich.edu break; 4307194Sgblack@eecs.umich.edu case 0x3: 4317194Sgblack@eecs.umich.edu switch (op2) { 4327194Sgblack@eecs.umich.edu case 0x0: 4337231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 4347194Sgblack@eecs.umich.edu case 0x1: 4357231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 4367194Sgblack@eecs.umich.edu case 0x2: 4377231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 4387194Sgblack@eecs.umich.edu case 0x3: 4397231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 4407194Sgblack@eecs.umich.edu case 0x4: 4417231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 4427194Sgblack@eecs.umich.edu case 0x7: 4437231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 4447194Sgblack@eecs.umich.edu } 4457194Sgblack@eecs.umich.edu break; 4467194Sgblack@eecs.umich.edu } 4477194Sgblack@eecs.umich.edu } 4487194Sgblack@eecs.umich.edu return new Unknown(machInst); 4497194Sgblack@eecs.umich.edu } 4507194Sgblack@eecs.umich.edu ''' 4517194Sgblack@eecs.umich.edu}}; 4527194Sgblack@eecs.umich.edu 4537139Sgblack@eecs.umich.edudef format ArmDataProcImm() {{ 4547188Sgblack@eecs.umich.edu pclr = ''' 45512595Ssiddhesh.poyarekar@gmail.com if (%(dest)s == INTREG_PC) { 45612595Ssiddhesh.poyarekar@gmail.com return new %(className)ssImmPclr(machInst, %(dest)s, 45712595Ssiddhesh.poyarekar@gmail.com %(op1)s, imm, false); 45812595Ssiddhesh.poyarekar@gmail.com } else 4597188Sgblack@eecs.umich.edu ''' 4607188Sgblack@eecs.umich.edu adr = ''' 46112595Ssiddhesh.poyarekar@gmail.com if (%(op1)s == INTREG_PC) { 46212595Ssiddhesh.poyarekar@gmail.com return new AdrImm(machInst, %(dest)s, %(add)s, 46312595Ssiddhesh.poyarekar@gmail.com imm, false); 46412595Ssiddhesh.poyarekar@gmail.com } else 4657188Sgblack@eecs.umich.edu ''' 4667139Sgblack@eecs.umich.edu instDecode = ''' 4677188Sgblack@eecs.umich.edu case %(opcode)#x: 4687139Sgblack@eecs.umich.edu if (setCc) { 46912595Ssiddhesh.poyarekar@gmail.com %(pclr)s { 4707188Sgblack@eecs.umich.edu return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 4717188Sgblack@eecs.umich.edu imm, rotC); 4727188Sgblack@eecs.umich.edu } 4737139Sgblack@eecs.umich.edu } else { 47412595Ssiddhesh.poyarekar@gmail.com %(adr)s { 4757188Sgblack@eecs.umich.edu return new %(className)sImm(machInst, %(dest)s, %(op1)s, 4767188Sgblack@eecs.umich.edu imm, rotC); 4777188Sgblack@eecs.umich.edu } 4787139Sgblack@eecs.umich.edu } 4797139Sgblack@eecs.umich.edu break; 4807139Sgblack@eecs.umich.edu ''' 4817139Sgblack@eecs.umich.edu 4827188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 4837188Sgblack@eecs.umich.edu global instDecode, pclr, adr 4847188Sgblack@eecs.umich.edu if useDest: 4857188Sgblack@eecs.umich.edu dest = "rd" 4867188Sgblack@eecs.umich.edu else: 4877188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 4887188Sgblack@eecs.umich.edu if useOp1: 4897188Sgblack@eecs.umich.edu op1 = "rn" 4907188Sgblack@eecs.umich.edu else: 4917188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 4927188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 4937188Sgblack@eecs.umich.edu "opcode": opcode, 4947188Sgblack@eecs.umich.edu "dest": dest, 4957188Sgblack@eecs.umich.edu "op1": op1, 49612595Ssiddhesh.poyarekar@gmail.com "adr": "" } 4977188Sgblack@eecs.umich.edu if useDest: 4987188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 4997188Sgblack@eecs.umich.edu else: 5007188Sgblack@eecs.umich.edu substDict["pclr"] = "" 5017188Sgblack@eecs.umich.edu return instDecode % substDict 5027185Sgblack@eecs.umich.edu 5037188Sgblack@eecs.umich.edu def adrCode(opcode, mnem, add="1"): 5047188Sgblack@eecs.umich.edu global instDecode, pclr, adr 5057188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 5067188Sgblack@eecs.umich.edu "opcode": opcode, 5077188Sgblack@eecs.umich.edu "dest": "rd", 5087188Sgblack@eecs.umich.edu "op1": "rn", 50912595Ssiddhesh.poyarekar@gmail.com "add": add } 5107188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 5117188Sgblack@eecs.umich.edu substDict["adr"] = adr % substDict 5127188Sgblack@eecs.umich.edu return instDecode % substDict 5137139Sgblack@eecs.umich.edu 5147139Sgblack@eecs.umich.edu decode_block = ''' 5157139Sgblack@eecs.umich.edu { 5167139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 5177139Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 5187139Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 5197139Sgblack@eecs.umich.edu const bool rotC = (rotation != 0); 5207139Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 5217139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 5227139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 5237139Sgblack@eecs.umich.edu switch (OPCODE) { 5247139Sgblack@eecs.umich.edu ''' 5257139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 5267139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 5277185Sgblack@eecs.umich.edu decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 5287139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 5297185Sgblack@eecs.umich.edu decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 5307139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 5317139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 5327139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 5337188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 5347188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 5357188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 5367188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 5377139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 5387188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 5397139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 5407188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 5417139Sgblack@eecs.umich.edu decode_block += ''' 5427139Sgblack@eecs.umich.edu default: 5437139Sgblack@eecs.umich.edu return new Unknown(machInst); 5447139Sgblack@eecs.umich.edu } 5457139Sgblack@eecs.umich.edu } 5467139Sgblack@eecs.umich.edu ''' 5477139Sgblack@eecs.umich.edu}}; 5487141Sgblack@eecs.umich.edu 5497195Sgblack@eecs.umich.edudef format ArmSatAddSub() {{ 5507195Sgblack@eecs.umich.edu decode_block = ''' 5517195Sgblack@eecs.umich.edu { 5527195Sgblack@eecs.umich.edu IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5537195Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 5547195Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5557195Sgblack@eecs.umich.edu switch (OPCODE) { 5567195Sgblack@eecs.umich.edu case 0x8: 5577195Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 5587195Sgblack@eecs.umich.edu case 0x9: 5597195Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 5607195Sgblack@eecs.umich.edu case 0xa: 5617195Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 5627195Sgblack@eecs.umich.edu case 0xb: 5637195Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 5647195Sgblack@eecs.umich.edu default: 5657195Sgblack@eecs.umich.edu return new Unknown(machInst); 5667195Sgblack@eecs.umich.edu } 5677195Sgblack@eecs.umich.edu } 5687195Sgblack@eecs.umich.edu ''' 5697195Sgblack@eecs.umich.edu}}; 5707195Sgblack@eecs.umich.edu 5717213Sgblack@eecs.umich.edudef format Thumb32DataProcReg() {{ 5727213Sgblack@eecs.umich.edu decode_block = ''' 5737213Sgblack@eecs.umich.edu { 5747213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 23, 20); 5757213Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5767213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 4); 5777290Sgblack@eecs.umich.edu if (bits(machInst, 15, 12) != 0xf) { 5787290Sgblack@eecs.umich.edu return new Unknown(machInst); 5797290Sgblack@eecs.umich.edu } 5807213Sgblack@eecs.umich.edu if (bits(op1, 3) != 1) { 5817213Sgblack@eecs.umich.edu if (op2 == 0) { 5827213Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 5837213Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5847213Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 5857213Sgblack@eecs.umich.edu case 0x0: 5867213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5877213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5887213Sgblack@eecs.umich.edu case 0x1: 5897213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5907213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5917213Sgblack@eecs.umich.edu case 0x2: 5927213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5937213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5947213Sgblack@eecs.umich.edu case 0x3: 5957213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5967213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5977213Sgblack@eecs.umich.edu case 0x4: 5987213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5997213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 6007213Sgblack@eecs.umich.edu case 0x5: 6017213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6027213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 6037213Sgblack@eecs.umich.edu case 0x6: 6047213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 6057213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6067213Sgblack@eecs.umich.edu case 0x7: 6077213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6087213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 60912595Ssiddhesh.poyarekar@gmail.com default: 61012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 6117213Sgblack@eecs.umich.edu } 6127290Sgblack@eecs.umich.edu } else if (bits(op2, 3) == 0) { 6137290Sgblack@eecs.umich.edu return new Unknown(machInst); 6147290Sgblack@eecs.umich.edu } else { 6157235Sgblack@eecs.umich.edu const IntRegIndex rd = 6167235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6177235Sgblack@eecs.umich.edu const IntRegIndex rm = 6187235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6197235Sgblack@eecs.umich.edu const uint32_t rotation = 6207235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 5, 4) << 3; 6217235Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 6227235Sgblack@eecs.umich.edu case 0x0: 6237235Sgblack@eecs.umich.edu if (rn == 0xf) { 6247235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 6257235Sgblack@eecs.umich.edu } else { 6267235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 6277235Sgblack@eecs.umich.edu } 6287235Sgblack@eecs.umich.edu case 0x1: 6297235Sgblack@eecs.umich.edu if (rn == 0xf) { 6307235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 6317235Sgblack@eecs.umich.edu } else { 6327235Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 6337235Sgblack@eecs.umich.edu } 6347235Sgblack@eecs.umich.edu case 0x2: 6357235Sgblack@eecs.umich.edu if (rn == 0xf) { 6367235Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 6377235Sgblack@eecs.umich.edu } else { 6387235Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 6397235Sgblack@eecs.umich.edu } 6407235Sgblack@eecs.umich.edu case 0x3: 6417235Sgblack@eecs.umich.edu if (rn == 0xf) { 6427235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 6437235Sgblack@eecs.umich.edu } else { 6447235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 6457235Sgblack@eecs.umich.edu } 6467235Sgblack@eecs.umich.edu case 0x4: 6477235Sgblack@eecs.umich.edu if (rn == 0xf) { 6487235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 6497235Sgblack@eecs.umich.edu } else { 6507235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 6517235Sgblack@eecs.umich.edu } 6527235Sgblack@eecs.umich.edu case 0x5: 6537235Sgblack@eecs.umich.edu if (rn == 0xf) { 6547235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 6557235Sgblack@eecs.umich.edu } else { 6567235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 6577235Sgblack@eecs.umich.edu } 6587235Sgblack@eecs.umich.edu default: 6597235Sgblack@eecs.umich.edu return new Unknown(machInst); 6607213Sgblack@eecs.umich.edu } 6617213Sgblack@eecs.umich.edu } 6627213Sgblack@eecs.umich.edu } else { 6637213Sgblack@eecs.umich.edu if (bits(op2, 3) == 0) { 6647220Sgblack@eecs.umich.edu const IntRegIndex rd = 6657220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6667220Sgblack@eecs.umich.edu const IntRegIndex rm = 6677220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6687213Sgblack@eecs.umich.edu if (bits(op2, 2) == 0x0) { 6697213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 6707213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 6717213Sgblack@eecs.umich.edu switch (op2) { 6727213Sgblack@eecs.umich.edu case 0x0: 6737213Sgblack@eecs.umich.edu switch (op1) { 6747213Sgblack@eecs.umich.edu case 0x1: 6757216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, 6767216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6777213Sgblack@eecs.umich.edu case 0x2: 6787224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, 6797224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6807213Sgblack@eecs.umich.edu case 0x6: 6817224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, 6827224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6837213Sgblack@eecs.umich.edu case 0x5: 6847218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, 6857218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6867213Sgblack@eecs.umich.edu case 0x0: 6877216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, 6887216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6897213Sgblack@eecs.umich.edu case 0x4: 6907218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, 6917218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6927213Sgblack@eecs.umich.edu } 6937213Sgblack@eecs.umich.edu break; 6947213Sgblack@eecs.umich.edu case 0x1: 6957216Sgblack@eecs.umich.edu switch (op1) { 6967216Sgblack@eecs.umich.edu case 0x1: 6977216Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 6987216Sgblack@eecs.umich.edu case 0x2: 6997216Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 7007216Sgblack@eecs.umich.edu case 0x6: 7017216Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 7027216Sgblack@eecs.umich.edu case 0x5: 7037216Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 7047216Sgblack@eecs.umich.edu case 0x0: 7057216Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 7067216Sgblack@eecs.umich.edu case 0x4: 7077216Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 7087213Sgblack@eecs.umich.edu } 7097213Sgblack@eecs.umich.edu break; 7107213Sgblack@eecs.umich.edu case 0x2: 7117213Sgblack@eecs.umich.edu switch (op1) { 7127213Sgblack@eecs.umich.edu case 0x1: 7137231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 7147213Sgblack@eecs.umich.edu case 0x2: 7157231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 7167213Sgblack@eecs.umich.edu case 0x6: 7177231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 7187213Sgblack@eecs.umich.edu case 0x5: 7197231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 7207213Sgblack@eecs.umich.edu case 0x0: 7217231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 7227213Sgblack@eecs.umich.edu case 0x4: 7237231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 7247213Sgblack@eecs.umich.edu } 7257213Sgblack@eecs.umich.edu break; 7267213Sgblack@eecs.umich.edu } 7277213Sgblack@eecs.umich.edu } else { 7287213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 7297213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7307213Sgblack@eecs.umich.edu switch (op2) { 7317213Sgblack@eecs.umich.edu case 0x0: 7327213Sgblack@eecs.umich.edu switch (op1) { 7337213Sgblack@eecs.umich.edu case 0x1: 7347222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, 7357222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7367213Sgblack@eecs.umich.edu case 0x2: 7377222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, 7387222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7397213Sgblack@eecs.umich.edu case 0x6: 7407222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, 7417222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7427213Sgblack@eecs.umich.edu case 0x5: 7437222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, 7447222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7457213Sgblack@eecs.umich.edu case 0x0: 7467222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, 7477222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7487213Sgblack@eecs.umich.edu case 0x4: 7497222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, 7507222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7517213Sgblack@eecs.umich.edu } 7527213Sgblack@eecs.umich.edu break; 7537213Sgblack@eecs.umich.edu case 0x1: 7547213Sgblack@eecs.umich.edu switch (op1) { 7557213Sgblack@eecs.umich.edu case 0x1: 7567220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 7577213Sgblack@eecs.umich.edu case 0x2: 7587220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 7597213Sgblack@eecs.umich.edu case 0x6: 7607220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 7617213Sgblack@eecs.umich.edu case 0x5: 7627220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 7637213Sgblack@eecs.umich.edu case 0x0: 7647220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 7657213Sgblack@eecs.umich.edu case 0x4: 7667220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 7677213Sgblack@eecs.umich.edu } 7687213Sgblack@eecs.umich.edu break; 7697213Sgblack@eecs.umich.edu case 0x2: 7707213Sgblack@eecs.umich.edu switch (op1) { 7717213Sgblack@eecs.umich.edu case 0x1: 7727231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 7737213Sgblack@eecs.umich.edu case 0x2: 7747231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 7757213Sgblack@eecs.umich.edu case 0x6: 7767231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 7777213Sgblack@eecs.umich.edu case 0x5: 7787231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 7797213Sgblack@eecs.umich.edu case 0x0: 7807231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 7817213Sgblack@eecs.umich.edu case 0x4: 7827231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 7837213Sgblack@eecs.umich.edu } 7847213Sgblack@eecs.umich.edu break; 7857213Sgblack@eecs.umich.edu } 7867213Sgblack@eecs.umich.edu } 7877213Sgblack@eecs.umich.edu } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 78812258Sgiacomo.travaglini@arm.com const uint32_t op1 = bits(machInst, 22, 20); 7897213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7907240Sgblack@eecs.umich.edu const IntRegIndex rd = 7917240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 7927240Sgblack@eecs.umich.edu const IntRegIndex rm = 7937240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 7947213Sgblack@eecs.umich.edu switch (op1) { 7957213Sgblack@eecs.umich.edu case 0x0: 7967240Sgblack@eecs.umich.edu switch (op2) { 7977240Sgblack@eecs.umich.edu case 0x0: 7987240Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, 7997240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8007240Sgblack@eecs.umich.edu case 0x1: 8017240Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, 8027240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8037240Sgblack@eecs.umich.edu case 0x2: 8047240Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, 8057240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8067240Sgblack@eecs.umich.edu case 0x3: 8077240Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, 8087240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8097213Sgblack@eecs.umich.edu } 8107213Sgblack@eecs.umich.edu break; 8117213Sgblack@eecs.umich.edu case 0x1: 8127240Sgblack@eecs.umich.edu switch (op2) { 8137240Sgblack@eecs.umich.edu case 0x0: 8147240Sgblack@eecs.umich.edu return new Rev(machInst, rd, rn); 8157240Sgblack@eecs.umich.edu case 0x1: 8167240Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rn); 8177240Sgblack@eecs.umich.edu case 0x2: 8187250Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 8197240Sgblack@eecs.umich.edu case 0x3: 8207240Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rn); 8217213Sgblack@eecs.umich.edu } 8227213Sgblack@eecs.umich.edu break; 8237213Sgblack@eecs.umich.edu case 0x2: 8247213Sgblack@eecs.umich.edu if (op2 == 0) { 8257240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 8267213Sgblack@eecs.umich.edu } 8277213Sgblack@eecs.umich.edu break; 8287213Sgblack@eecs.umich.edu case 0x3: 8297213Sgblack@eecs.umich.edu if (op2 == 0) { 8307252Sgblack@eecs.umich.edu return new Clz(machInst, rd, rm); 8317213Sgblack@eecs.umich.edu } 83212258Sgiacomo.travaglini@arm.com break; 83314031Schunchenhsu@google.com } 83414031Schunchenhsu@google.com } else if (bits(op1, 3, 2) == 0x3 && bits(op2, 3, 2) == 0x2) { 83514031Schunchenhsu@google.com const uint32_t op1 = bits(machInst, 22, 20); 83614031Schunchenhsu@google.com const uint32_t op2 = bits(machInst, 5, 4); 83714031Schunchenhsu@google.com const IntRegIndex rd = 83814031Schunchenhsu@google.com (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 83914031Schunchenhsu@google.com const IntRegIndex rm = 84014031Schunchenhsu@google.com (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 84114031Schunchenhsu@google.com switch (op1) { 84212258Sgiacomo.travaglini@arm.com case 0x4: 84312258Sgiacomo.travaglini@arm.com switch (op2) { 84412258Sgiacomo.travaglini@arm.com case 0x0: 84512258Sgiacomo.travaglini@arm.com return new Crc32b(machInst, rd, rn, rm); 84612258Sgiacomo.travaglini@arm.com case 0x1: 84712258Sgiacomo.travaglini@arm.com return new Crc32h(machInst, rd, rn, rm); 84812258Sgiacomo.travaglini@arm.com case 0x2: 84912258Sgiacomo.travaglini@arm.com return new Crc32w(machInst, rd, rn, rm); 85012258Sgiacomo.travaglini@arm.com } 85112258Sgiacomo.travaglini@arm.com break; 85212258Sgiacomo.travaglini@arm.com case 0x5: 85312258Sgiacomo.travaglini@arm.com switch (op2) { 85412258Sgiacomo.travaglini@arm.com case 0x0: 85512258Sgiacomo.travaglini@arm.com return new Crc32cb(machInst, rd, rn, rm); 85612258Sgiacomo.travaglini@arm.com case 0x1: 85712258Sgiacomo.travaglini@arm.com return new Crc32ch(machInst, rd, rn, rm); 85812258Sgiacomo.travaglini@arm.com case 0x2: 85912258Sgiacomo.travaglini@arm.com return new Crc32cw(machInst, rd, rn, rm); 86012258Sgiacomo.travaglini@arm.com } 86112258Sgiacomo.travaglini@arm.com break; 8627213Sgblack@eecs.umich.edu } 8637213Sgblack@eecs.umich.edu } 8647213Sgblack@eecs.umich.edu return new Unknown(machInst); 8657213Sgblack@eecs.umich.edu } 8667213Sgblack@eecs.umich.edu } 8677213Sgblack@eecs.umich.edu ''' 8687213Sgblack@eecs.umich.edu}}; 8697213Sgblack@eecs.umich.edu 8707141Sgblack@eecs.umich.edudef format Thumb16ShiftAddSubMoveCmp() {{ 8717141Sgblack@eecs.umich.edu decode_block = ''' 8727141Sgblack@eecs.umich.edu { 8737141Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 10, 6); 8747141Sgblack@eecs.umich.edu const uint32_t imm3 = bits(machInst, 8, 6); 8757141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 8767141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8777141Sgblack@eecs.umich.edu const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 8787141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8797141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 8807141Sgblack@eecs.umich.edu switch (bits(machInst, 13, 11)) { 8817141Sgblack@eecs.umich.edu case 0x0: // lsl 8827408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 8837408Sgblack@eecs.umich.edu return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 8847408Sgblack@eecs.umich.edu } else { 8857408Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 8867408Sgblack@eecs.umich.edu } 8877141Sgblack@eecs.umich.edu case 0x1: // lsr 8887408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 8897408Sgblack@eecs.umich.edu return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 8907408Sgblack@eecs.umich.edu } else { 8917408Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 8927408Sgblack@eecs.umich.edu } 8937141Sgblack@eecs.umich.edu case 0x2: // asr 8947408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 8957408Sgblack@eecs.umich.edu return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 8967408Sgblack@eecs.umich.edu } else { 8977408Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 8987408Sgblack@eecs.umich.edu } 8997141Sgblack@eecs.umich.edu case 0x3: 9007141Sgblack@eecs.umich.edu switch (bits(machInst, 10, 9)) { 9017141Sgblack@eecs.umich.edu case 0x0: 9027408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9037408Sgblack@eecs.umich.edu return new AddReg(machInst, rd, rn, rm, 0, LSL); 9047408Sgblack@eecs.umich.edu } else { 9057408Sgblack@eecs.umich.edu return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 9067408Sgblack@eecs.umich.edu } 9077141Sgblack@eecs.umich.edu case 0x1: 9087408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9097408Sgblack@eecs.umich.edu return new SubReg(machInst, rd, rn, rm, 0, LSL); 9107408Sgblack@eecs.umich.edu } else { 9117408Sgblack@eecs.umich.edu return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 9127408Sgblack@eecs.umich.edu } 9137141Sgblack@eecs.umich.edu case 0x2: 9147408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9157408Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm3, true); 9167408Sgblack@eecs.umich.edu } else { 9177408Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd, rn, imm3, true); 9187408Sgblack@eecs.umich.edu } 9197141Sgblack@eecs.umich.edu case 0x3: 9207408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9217408Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm3, true); 9227408Sgblack@eecs.umich.edu } else { 9237408Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd, rn, imm3, true); 9247408Sgblack@eecs.umich.edu } 92512595Ssiddhesh.poyarekar@gmail.com default: 92612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 9277141Sgblack@eecs.umich.edu } 9287141Sgblack@eecs.umich.edu case 0x4: 9297408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9307408Sgblack@eecs.umich.edu return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false); 9317408Sgblack@eecs.umich.edu } else { 9327408Sgblack@eecs.umich.edu return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 9337408Sgblack@eecs.umich.edu } 9347141Sgblack@eecs.umich.edu case 0x5: 9357146Sgblack@eecs.umich.edu return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 9367141Sgblack@eecs.umich.edu case 0x6: 9377408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9387408Sgblack@eecs.umich.edu return new AddImm(machInst, rd8, rd8, imm8, true); 9397408Sgblack@eecs.umich.edu } else { 9407408Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd8, rd8, imm8, true); 9417408Sgblack@eecs.umich.edu } 9427141Sgblack@eecs.umich.edu case 0x7: 9437408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9447408Sgblack@eecs.umich.edu return new SubImm(machInst, rd8, rd8, imm8, true); 9457408Sgblack@eecs.umich.edu } else { 9467408Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd8, rd8, imm8, true); 9477408Sgblack@eecs.umich.edu } 94812595Ssiddhesh.poyarekar@gmail.com default: 94912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 9507141Sgblack@eecs.umich.edu } 9517141Sgblack@eecs.umich.edu } 9527141Sgblack@eecs.umich.edu ''' 9537141Sgblack@eecs.umich.edu}}; 9547141Sgblack@eecs.umich.edu 9557141Sgblack@eecs.umich.edudef format Thumb16DataProcessing() {{ 9567141Sgblack@eecs.umich.edu decode_block = ''' 9577141Sgblack@eecs.umich.edu { 9587141Sgblack@eecs.umich.edu const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 9597141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 9607141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 6)) { 9617141Sgblack@eecs.umich.edu case 0x0: 9627408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9637408Sgblack@eecs.umich.edu return new AndReg(machInst, rdn, rdn, rm, 0, LSL); 9647408Sgblack@eecs.umich.edu } else { 9657408Sgblack@eecs.umich.edu return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 9667408Sgblack@eecs.umich.edu } 9677141Sgblack@eecs.umich.edu case 0x1: 9687408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9697408Sgblack@eecs.umich.edu return new EorReg(machInst, rdn, rdn, rm, 0, LSL); 9707408Sgblack@eecs.umich.edu } else { 9717408Sgblack@eecs.umich.edu return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 9727408Sgblack@eecs.umich.edu } 9737141Sgblack@eecs.umich.edu case 0x2: //lsl 9747408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9757408Sgblack@eecs.umich.edu return new MovRegReg(machInst, rdn, 9767408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, LSL); 9777408Sgblack@eecs.umich.edu } else { 9787408Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, 9797408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, LSL); 9807408Sgblack@eecs.umich.edu } 9817141Sgblack@eecs.umich.edu case 0x3: //lsr 9827408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9837408Sgblack@eecs.umich.edu return new MovRegReg(machInst, rdn, 9847408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, LSR); 9857408Sgblack@eecs.umich.edu } else { 9867408Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, 9877408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, LSR); 9887408Sgblack@eecs.umich.edu } 9897141Sgblack@eecs.umich.edu case 0x4: //asr 9907408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9917408Sgblack@eecs.umich.edu return new MovRegReg(machInst, rdn, 9927408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, ASR); 9937408Sgblack@eecs.umich.edu } else { 9947408Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, 9957408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, ASR); 9967408Sgblack@eecs.umich.edu } 9977141Sgblack@eecs.umich.edu case 0x5: 9987408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9997408Sgblack@eecs.umich.edu return new AdcReg(machInst, rdn, rdn, rm, 0, LSL); 10007408Sgblack@eecs.umich.edu } else { 10017408Sgblack@eecs.umich.edu return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 10027408Sgblack@eecs.umich.edu } 10037141Sgblack@eecs.umich.edu case 0x6: 10047408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10057408Sgblack@eecs.umich.edu return new SbcReg(machInst, rdn, rdn, rm, 0, LSL); 10067408Sgblack@eecs.umich.edu } else { 10077408Sgblack@eecs.umich.edu return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 10087408Sgblack@eecs.umich.edu } 10097141Sgblack@eecs.umich.edu case 0x7: // ror 10107408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10117408Sgblack@eecs.umich.edu return new MovRegReg(machInst, rdn, 10127408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, ROR); 10137408Sgblack@eecs.umich.edu } else { 10147408Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, 10157408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, ROR); 10167408Sgblack@eecs.umich.edu } 10177141Sgblack@eecs.umich.edu case 0x8: 10187183Sgblack@eecs.umich.edu return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 10197141Sgblack@eecs.umich.edu case 0x9: 10207408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10217408Sgblack@eecs.umich.edu return new RsbImm(machInst, rdn, rm, 0, true); 10227408Sgblack@eecs.umich.edu } else { 10237408Sgblack@eecs.umich.edu return new RsbImmCc(machInst, rdn, rm, 0, true); 10247408Sgblack@eecs.umich.edu } 10257141Sgblack@eecs.umich.edu case 0xa: 10267183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 10277141Sgblack@eecs.umich.edu case 0xb: 10287183Sgblack@eecs.umich.edu return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 10297141Sgblack@eecs.umich.edu case 0xc: 10307408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10317408Sgblack@eecs.umich.edu return new OrrReg(machInst, rdn, rdn, rm, 0, LSL); 10327408Sgblack@eecs.umich.edu } else { 10337408Sgblack@eecs.umich.edu return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 10347408Sgblack@eecs.umich.edu } 10357141Sgblack@eecs.umich.edu case 0xd: 10367408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10377408Sgblack@eecs.umich.edu return new Mul(machInst, rdn, rm, rdn); 10387408Sgblack@eecs.umich.edu } else { 10397408Sgblack@eecs.umich.edu return new MulCc(machInst, rdn, rm, rdn); 10407408Sgblack@eecs.umich.edu } 10417141Sgblack@eecs.umich.edu case 0xe: 10427408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10437408Sgblack@eecs.umich.edu return new BicReg(machInst, rdn, rdn, rm, 0, LSL); 10447408Sgblack@eecs.umich.edu } else { 10457408Sgblack@eecs.umich.edu return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 10467408Sgblack@eecs.umich.edu } 10477141Sgblack@eecs.umich.edu case 0xf: 10487408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10497408Sgblack@eecs.umich.edu return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 10507408Sgblack@eecs.umich.edu } else { 10517408Sgblack@eecs.umich.edu return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 10527408Sgblack@eecs.umich.edu } 105312595Ssiddhesh.poyarekar@gmail.com default: 105412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 10557141Sgblack@eecs.umich.edu } 10567141Sgblack@eecs.umich.edu } 10577141Sgblack@eecs.umich.edu ''' 10587141Sgblack@eecs.umich.edu}}; 10597141Sgblack@eecs.umich.edu 10607141Sgblack@eecs.umich.edudef format Thumb16SpecDataAndBx() {{ 10617141Sgblack@eecs.umich.edu decode_block = ''' 10627141Sgblack@eecs.umich.edu { 10637141Sgblack@eecs.umich.edu const IntRegIndex rdn = 10647141Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 10657141Sgblack@eecs.umich.edu (bits(machInst, 7) << 3)); 10667141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 10677141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 8)) { 10687141Sgblack@eecs.umich.edu case 0x0: 10697146Sgblack@eecs.umich.edu return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 10707141Sgblack@eecs.umich.edu case 0x1: 10717183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 10727141Sgblack@eecs.umich.edu case 0x2: 10737146Sgblack@eecs.umich.edu return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 10747141Sgblack@eecs.umich.edu case 0x3: 10757154Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 10767154Sgblack@eecs.umich.edu return new BxReg(machInst, 10777154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 10788909SAli.Saidi@ARM.com COND_UC); 10797154Sgblack@eecs.umich.edu } else { 10807154Sgblack@eecs.umich.edu return new BlxReg(machInst, 10817154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 10828909SAli.Saidi@ARM.com COND_UC); 10837154Sgblack@eecs.umich.edu } 108412595Ssiddhesh.poyarekar@gmail.com default: 108512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 10867141Sgblack@eecs.umich.edu } 10877141Sgblack@eecs.umich.edu } 10887141Sgblack@eecs.umich.edu ''' 10897141Sgblack@eecs.umich.edu}}; 10907141Sgblack@eecs.umich.edu 10917141Sgblack@eecs.umich.edudef format Thumb16Adr() {{ 10927141Sgblack@eecs.umich.edu decode_block = ''' 10937141Sgblack@eecs.umich.edu { 10947141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 10957141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 10967185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 10977141Sgblack@eecs.umich.edu } 10987141Sgblack@eecs.umich.edu ''' 10997141Sgblack@eecs.umich.edu}}; 11007141Sgblack@eecs.umich.edu 11017141Sgblack@eecs.umich.edudef format Thumb16AddSp() {{ 11027141Sgblack@eecs.umich.edu decode_block = ''' 11037141Sgblack@eecs.umich.edu { 11047141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 11057141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 11067146Sgblack@eecs.umich.edu return new AddImm(machInst, rd, INTREG_SP, imm8, true); 11077141Sgblack@eecs.umich.edu } 11087141Sgblack@eecs.umich.edu ''' 11097141Sgblack@eecs.umich.edu}}; 11107141Sgblack@eecs.umich.edu 11117418Sgblack@eecs.umich.edudef format ArmMisc() {{ 11127418Sgblack@eecs.umich.edu decode_block = ''' 11137418Sgblack@eecs.umich.edu { 11147418Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 11157418Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 11167418Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 11177418Sgblack@eecs.umich.edu const uint8_t byteMask = bits(machInst, 19, 16); 11187418Sgblack@eecs.umich.edu switch (OPCODE) { 11197418Sgblack@eecs.umich.edu case 0x8: 11207418Sgblack@eecs.umich.edu return new MovImm(machInst, (IntRegIndex)(uint32_t)RD, 11217418Sgblack@eecs.umich.edu (IntRegIndex)INTREG_ZERO, 11227418Sgblack@eecs.umich.edu bits(machInst, 11, 0) | (bits(machInst, 19, 16) << 12), 11237418Sgblack@eecs.umich.edu false); 11247418Sgblack@eecs.umich.edu case 0x9: 11257418Sgblack@eecs.umich.edu if (RN == 0) { 112613354Sciro.santilli@arm.com if ((IMM & 0xf0) == 0xf0) { 112713354Sciro.santilli@arm.com return new Dbg(machInst); 112813354Sciro.santilli@arm.com } else { 112913354Sciro.santilli@arm.com switch (IMM) { 113013354Sciro.santilli@arm.com case 0x0: 113113354Sciro.santilli@arm.com return new NopInst(machInst); 113213354Sciro.santilli@arm.com case 0x1: 113313354Sciro.santilli@arm.com return new YieldInst(machInst); 113413354Sciro.santilli@arm.com case 0x2: 113513354Sciro.santilli@arm.com return new WfeInst(machInst); 113613354Sciro.santilli@arm.com case 0x3: 113713354Sciro.santilli@arm.com return new WfiInst(machInst); 113813354Sciro.santilli@arm.com case 0x4: 113913354Sciro.santilli@arm.com return new SevInst(machInst); 114013354Sciro.santilli@arm.com case 0x5: 114113354Sciro.santilli@arm.com return new WarnUnimplemented( 114213354Sciro.santilli@arm.com "sevl", machInst); 114313354Sciro.santilli@arm.com case 0x10: 114413354Sciro.santilli@arm.com return new WarnUnimplemented( 114513354Sciro.santilli@arm.com "esb", machInst); 114613354Sciro.santilli@arm.com case 0x12: 114713354Sciro.santilli@arm.com return new WarnUnimplemented( 114813354Sciro.santilli@arm.com "tsb csync", machInst); 114913354Sciro.santilli@arm.com case 0x14: 115013354Sciro.santilli@arm.com return new WarnUnimplemented( 115113354Sciro.santilli@arm.com "csdb", machInst); 115213354Sciro.santilli@arm.com default: 115313354Sciro.santilli@arm.com return new WarnUnimplemented( 115413354Sciro.santilli@arm.com "unallocated_hint", machInst); 115513354Sciro.santilli@arm.com } 11567418Sgblack@eecs.umich.edu } 11577418Sgblack@eecs.umich.edu } else { 11587418Sgblack@eecs.umich.edu return new MsrCpsrImm(machInst, imm, byteMask); 11597418Sgblack@eecs.umich.edu } 11607418Sgblack@eecs.umich.edu case 0xa: 11617418Sgblack@eecs.umich.edu { 11627418Sgblack@eecs.umich.edu const uint32_t timm = (bits(machInst, 19, 16) << 12) | 11637418Sgblack@eecs.umich.edu bits(machInst, 11, 0); 11647418Sgblack@eecs.umich.edu return new MovtImm(machInst, (IntRegIndex)(uint32_t)RD, 11657418Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)RD, timm, true); 11667418Sgblack@eecs.umich.edu } 11677418Sgblack@eecs.umich.edu case 0xb: 11687418Sgblack@eecs.umich.edu return new MsrSpsrImm(machInst, imm, byteMask); 11697418Sgblack@eecs.umich.edu default: 11707418Sgblack@eecs.umich.edu return new Unknown(machInst); 11717418Sgblack@eecs.umich.edu } 11727418Sgblack@eecs.umich.edu } 11737418Sgblack@eecs.umich.edu ''' 11747418Sgblack@eecs.umich.edu}}; 11757418Sgblack@eecs.umich.edu 11767141Sgblack@eecs.umich.edudef format Thumb16Misc() {{ 11777141Sgblack@eecs.umich.edu decode_block = ''' 11787141Sgblack@eecs.umich.edu { 11797141Sgblack@eecs.umich.edu switch (bits(machInst, 11, 8)) { 11807141Sgblack@eecs.umich.edu case 0x0: 11817141Sgblack@eecs.umich.edu if (bits(machInst, 7)) { 11827146Sgblack@eecs.umich.edu return new SubImm(machInst, INTREG_SP, INTREG_SP, 11837141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 11847141Sgblack@eecs.umich.edu } else { 11857146Sgblack@eecs.umich.edu return new AddImm(machInst, INTREG_SP, INTREG_SP, 11867141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 11877141Sgblack@eecs.umich.edu } 11887141Sgblack@eecs.umich.edu case 0x2: 11897235Sgblack@eecs.umich.edu { 11907235Sgblack@eecs.umich.edu const IntRegIndex rd = 11917235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 11927235Sgblack@eecs.umich.edu const IntRegIndex rm = 11937235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 11947235Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 11957235Sgblack@eecs.umich.edu case 0x0: 11967235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, 0, rm); 11977235Sgblack@eecs.umich.edu case 0x1: 11987235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, 0, rm); 11997235Sgblack@eecs.umich.edu case 0x2: 12007235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, 0, rm); 12017235Sgblack@eecs.umich.edu case 0x3: 12027235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, 0, rm); 120312595Ssiddhesh.poyarekar@gmail.com default: 120412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 12057235Sgblack@eecs.umich.edu } 12067141Sgblack@eecs.umich.edu } 12077432Sgblack@eecs.umich.edu case 0x1: 12087141Sgblack@eecs.umich.edu case 0x3: 12097154Sgblack@eecs.umich.edu return new Cbz(machInst, 12107154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 12117154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 12127154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 12137141Sgblack@eecs.umich.edu case 0x4: 12147141Sgblack@eecs.umich.edu case 0x5: 12157201Sgblack@eecs.umich.edu { 12167201Sgblack@eecs.umich.edu const uint32_t m = bits(machInst, 8); 12177201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 12187201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, false, false, false, 12197201Sgblack@eecs.umich.edu true, false, regList); 12207201Sgblack@eecs.umich.edu } 12217141Sgblack@eecs.umich.edu case 0x6: 12227141Sgblack@eecs.umich.edu { 12237141Sgblack@eecs.umich.edu const uint32_t opBits = bits(machInst, 7, 5); 12247141Sgblack@eecs.umich.edu if (opBits == 2) { 12257308Sgblack@eecs.umich.edu return new Setend(machInst, bits(machInst, 3)); 12267141Sgblack@eecs.umich.edu } else if (opBits == 3) { 12277316Sgblack@eecs.umich.edu const bool enable = (bits(machInst, 4) == 0); 12287316Sgblack@eecs.umich.edu const uint32_t mods = (bits(machInst, 2, 0) << 5) | 12297316Sgblack@eecs.umich.edu ((enable ? 1 : 0) << 9); 12307316Sgblack@eecs.umich.edu return new Cps(machInst, mods); 12317141Sgblack@eecs.umich.edu } 123212595Ssiddhesh.poyarekar@gmail.com return new Unknown(machInst); 12337141Sgblack@eecs.umich.edu } 12347141Sgblack@eecs.umich.edu case 0xa: 12357212Sgblack@eecs.umich.edu { 123612542Sgiacomo.travaglini@arm.com const uint8_t op1 = bits(machInst, 7, 6); 123712542Sgiacomo.travaglini@arm.com if (op1 == 0x2) { 123812542Sgiacomo.travaglini@arm.com return new Hlt(machInst, bits(machInst, 5, 0)); 123912542Sgiacomo.travaglini@arm.com } else { 124012542Sgiacomo.travaglini@arm.com IntRegIndex rd = 124112542Sgiacomo.travaglini@arm.com (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 124212542Sgiacomo.travaglini@arm.com IntRegIndex rm = 124312542Sgiacomo.travaglini@arm.com (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 124412542Sgiacomo.travaglini@arm.com 124512542Sgiacomo.travaglini@arm.com switch (op1) { 124612542Sgiacomo.travaglini@arm.com case 0x0: 124712542Sgiacomo.travaglini@arm.com return new Rev(machInst, rd, rm); 124812542Sgiacomo.travaglini@arm.com case 0x1: 124912542Sgiacomo.travaglini@arm.com return new Rev16(machInst, rd, rm); 125012542Sgiacomo.travaglini@arm.com case 0x3: 125112542Sgiacomo.travaglini@arm.com return new Revsh(machInst, rd, rm); 125212542Sgiacomo.travaglini@arm.com default: 125312542Sgiacomo.travaglini@arm.com break; 125412542Sgiacomo.travaglini@arm.com } 12557212Sgblack@eecs.umich.edu } 12567141Sgblack@eecs.umich.edu } 12577141Sgblack@eecs.umich.edu break; 12587432Sgblack@eecs.umich.edu case 0x9: 12597141Sgblack@eecs.umich.edu case 0xb: 12607154Sgblack@eecs.umich.edu return new Cbnz(machInst, 12617154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 12627154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 12637154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 12647141Sgblack@eecs.umich.edu case 0xc: 12657141Sgblack@eecs.umich.edu case 0xd: 12667201Sgblack@eecs.umich.edu { 12677201Sgblack@eecs.umich.edu const uint32_t p = bits(machInst, 8); 12687201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 12697201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, true, true, false, 12707201Sgblack@eecs.umich.edu true, true, regList); 12717201Sgblack@eecs.umich.edu } 12727141Sgblack@eecs.umich.edu case 0xe: 12737410Sgblack@eecs.umich.edu return new BkptInst(machInst); 12747141Sgblack@eecs.umich.edu case 0xf: 12757141Sgblack@eecs.umich.edu if (bits(machInst, 3, 0) != 0) 12767408Sgblack@eecs.umich.edu return new ItInst(machInst); 12777141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 4)) { 12787141Sgblack@eecs.umich.edu case 0x0: 12797248Sgblack@eecs.umich.edu return new NopInst(machInst); 12807141Sgblack@eecs.umich.edu case 0x1: 12817419Sgblack@eecs.umich.edu return new YieldInst(machInst); 12827141Sgblack@eecs.umich.edu case 0x2: 12837419Sgblack@eecs.umich.edu return new WfeInst(machInst); 12847141Sgblack@eecs.umich.edu case 0x3: 12857419Sgblack@eecs.umich.edu return new WfiInst(machInst); 12867141Sgblack@eecs.umich.edu case 0x4: 12877419Sgblack@eecs.umich.edu return new SevInst(machInst); 12887141Sgblack@eecs.umich.edu default: 12897141Sgblack@eecs.umich.edu return new WarnUnimplemented("unallocated_hint", machInst); 12907141Sgblack@eecs.umich.edu } 12917141Sgblack@eecs.umich.edu default: 12927141Sgblack@eecs.umich.edu break; 12937141Sgblack@eecs.umich.edu } 12947141Sgblack@eecs.umich.edu return new Unknown(machInst); 12957141Sgblack@eecs.umich.edu } 12967141Sgblack@eecs.umich.edu ''' 12977141Sgblack@eecs.umich.edu}}; 12987141Sgblack@eecs.umich.edu 12997141Sgblack@eecs.umich.edudef format Thumb32DataProcModImm() {{ 13007141Sgblack@eecs.umich.edu 13017141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 13027141Sgblack@eecs.umich.edu return ''' 13037141Sgblack@eecs.umich.edu if (s) { 13047146Sgblack@eecs.umich.edu return new %(mnem)sImmCc(machInst, %(dest)s, 13057183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 13067141Sgblack@eecs.umich.edu } else { 13077146Sgblack@eecs.umich.edu return new %(mnem)sImm(machInst, %(dest)s, 13087183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 13097141Sgblack@eecs.umich.edu } 13107141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 13117141Sgblack@eecs.umich.edu 13127141Sgblack@eecs.umich.edu decode_block = ''' 13137141Sgblack@eecs.umich.edu { 13147141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 13157141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 13167141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 13177141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 13187141Sgblack@eecs.umich.edu const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 13197141Sgblack@eecs.umich.edu bits(machInst, 14, 12); 13207183Sgblack@eecs.umich.edu const bool rotC = ctrlImm > 3; 13217141Sgblack@eecs.umich.edu const uint32_t dataImm = bits(machInst, 7, 0); 13227141Sgblack@eecs.umich.edu const uint32_t imm = modified_imm(ctrlImm, dataImm); 13237141Sgblack@eecs.umich.edu switch (op) { 13247141Sgblack@eecs.umich.edu case 0x0: 13257141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13267141Sgblack@eecs.umich.edu %(tst)s 13277141Sgblack@eecs.umich.edu } else { 13287141Sgblack@eecs.umich.edu %(and)s 13297141Sgblack@eecs.umich.edu } 13307141Sgblack@eecs.umich.edu case 0x1: 13317141Sgblack@eecs.umich.edu %(bic)s 13327141Sgblack@eecs.umich.edu case 0x2: 13337141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13347141Sgblack@eecs.umich.edu %(mov)s 13357141Sgblack@eecs.umich.edu } else { 13367141Sgblack@eecs.umich.edu %(orr)s 13377141Sgblack@eecs.umich.edu } 13387141Sgblack@eecs.umich.edu case 0x3: 13397141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13407141Sgblack@eecs.umich.edu %(mvn)s 13417141Sgblack@eecs.umich.edu } else { 13427141Sgblack@eecs.umich.edu %(orn)s 13437141Sgblack@eecs.umich.edu } 13447141Sgblack@eecs.umich.edu case 0x4: 13457141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13467141Sgblack@eecs.umich.edu %(teq)s 13477141Sgblack@eecs.umich.edu } else { 13487141Sgblack@eecs.umich.edu %(eor)s 13497141Sgblack@eecs.umich.edu } 13507141Sgblack@eecs.umich.edu case 0x8: 13517141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13527141Sgblack@eecs.umich.edu %(cmn)s 13537141Sgblack@eecs.umich.edu } else { 13547141Sgblack@eecs.umich.edu %(add)s 13557141Sgblack@eecs.umich.edu } 13567141Sgblack@eecs.umich.edu case 0xa: 13577141Sgblack@eecs.umich.edu %(adc)s 13587141Sgblack@eecs.umich.edu case 0xb: 13597141Sgblack@eecs.umich.edu %(sbc)s 13607141Sgblack@eecs.umich.edu case 0xd: 13617141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13627141Sgblack@eecs.umich.edu %(cmp)s 13637141Sgblack@eecs.umich.edu } else { 13647141Sgblack@eecs.umich.edu %(sub)s 13657141Sgblack@eecs.umich.edu } 13667141Sgblack@eecs.umich.edu case 0xe: 13677141Sgblack@eecs.umich.edu %(rsb)s 13687141Sgblack@eecs.umich.edu default: 13697141Sgblack@eecs.umich.edu return new Unknown(machInst); 13707141Sgblack@eecs.umich.edu } 13717141Sgblack@eecs.umich.edu } 13727141Sgblack@eecs.umich.edu ''' % { 13737141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 13747141Sgblack@eecs.umich.edu "and" : decInst("And"), 13757141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 13767141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 13777141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 13787141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 13797141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 13807141Sgblack@eecs.umich.edu "teq" : decInst("Teq", dest="INTREG_ZERO"), 13817141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 13827141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 13837141Sgblack@eecs.umich.edu "add" : decInst("Add"), 13847141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 13857141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 13867141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 13877141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 13887141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 13897141Sgblack@eecs.umich.edu } 13907141Sgblack@eecs.umich.edu}}; 13917141Sgblack@eecs.umich.edu 13927157Sgblack@eecs.umich.edudef format Thumb32DataProcPlainBin() {{ 13937157Sgblack@eecs.umich.edu decode_block = ''' 13947157Sgblack@eecs.umich.edu { 13957157Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 20); 13967157Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 13977157Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 13987157Sgblack@eecs.umich.edu switch (op) { 13997157Sgblack@eecs.umich.edu case 0x0: 14007157Sgblack@eecs.umich.edu { 14017157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 14027157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 14037157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 14047185Sgblack@eecs.umich.edu if (rn == 0xf) { 14057185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, 14067185Sgblack@eecs.umich.edu imm, false); 14077185Sgblack@eecs.umich.edu } else { 14087185Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm, true); 14097185Sgblack@eecs.umich.edu } 14107157Sgblack@eecs.umich.edu } 14117157Sgblack@eecs.umich.edu case 0x4: 14127157Sgblack@eecs.umich.edu { 14137157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 14147157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 14157157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 14167157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 14177157Sgblack@eecs.umich.edu return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 14187157Sgblack@eecs.umich.edu } 14197157Sgblack@eecs.umich.edu case 0xa: 14207157Sgblack@eecs.umich.edu { 14217157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 14227157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 14237157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 14247185Sgblack@eecs.umich.edu if (rn == 0xf) { 14257185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)0, 14267185Sgblack@eecs.umich.edu imm, false); 14277185Sgblack@eecs.umich.edu } else { 14287185Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm, true); 14297185Sgblack@eecs.umich.edu } 14307157Sgblack@eecs.umich.edu } 14317157Sgblack@eecs.umich.edu case 0xc: 14327157Sgblack@eecs.umich.edu { 14337157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 14347157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 14357157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 14367157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 14377157Sgblack@eecs.umich.edu return new MovtImm(machInst, rd, rd, imm, true); 14387157Sgblack@eecs.umich.edu } 14397157Sgblack@eecs.umich.edu case 0x12: 14407157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 14417227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 14427227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 14437157Sgblack@eecs.umich.edu } 144412595Ssiddhesh.poyarekar@gmail.com M5_FALLTHROUGH; 14457157Sgblack@eecs.umich.edu case 0x10: 14467227Sgblack@eecs.umich.edu { 14477227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 14487227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 14497227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14507227Sgblack@eecs.umich.edu const ArmShiftType type = 14517227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 14527227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 14537227Sgblack@eecs.umich.edu } 14547157Sgblack@eecs.umich.edu case 0x14: 14557256Sgblack@eecs.umich.edu { 14567256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 14577256Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14587256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 4, 0); 14597256Sgblack@eecs.umich.edu return new Sbfx(machInst, rd, rn, lsb, msb); 14607256Sgblack@eecs.umich.edu } 14617157Sgblack@eecs.umich.edu case 0x16: 14627258Sgblack@eecs.umich.edu { 14637258Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 14647258Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14657258Sgblack@eecs.umich.edu const uint32_t msb = bits(machInst, 4, 0); 14667258Sgblack@eecs.umich.edu if (rn == 0xf) { 14677258Sgblack@eecs.umich.edu return new Bfc(machInst, rd, rd, lsb, msb); 14687258Sgblack@eecs.umich.edu } else { 14697258Sgblack@eecs.umich.edu return new Bfi(machInst, rd, rn, lsb, msb); 14707258Sgblack@eecs.umich.edu } 14717157Sgblack@eecs.umich.edu } 14727157Sgblack@eecs.umich.edu case 0x1a: 14737157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 14747227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 14757227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 14767157Sgblack@eecs.umich.edu } 147712595Ssiddhesh.poyarekar@gmail.com M5_FALLTHROUGH; 14787157Sgblack@eecs.umich.edu case 0x18: 14797227Sgblack@eecs.umich.edu { 14807227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 14817227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 14827227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14837227Sgblack@eecs.umich.edu const ArmShiftType type = 14847227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 14857227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 14867227Sgblack@eecs.umich.edu } 14877157Sgblack@eecs.umich.edu case 0x1c: 14887256Sgblack@eecs.umich.edu { 14897256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 14907256Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14917256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 4, 0); 14927256Sgblack@eecs.umich.edu return new Ubfx(machInst, rd, rn, lsb, msb); 14937256Sgblack@eecs.umich.edu } 14947157Sgblack@eecs.umich.edu default: 14957157Sgblack@eecs.umich.edu return new Unknown(machInst); 14967157Sgblack@eecs.umich.edu } 14977157Sgblack@eecs.umich.edu } 14987157Sgblack@eecs.umich.edu ''' 14997157Sgblack@eecs.umich.edu}}; 15007157Sgblack@eecs.umich.edu 15017141Sgblack@eecs.umich.edudef format Thumb32DataProcShiftReg() {{ 15027141Sgblack@eecs.umich.edu 15037141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 15047141Sgblack@eecs.umich.edu return ''' 15057141Sgblack@eecs.umich.edu if (s) { 15067146Sgblack@eecs.umich.edu return new %(mnem)sRegCc(machInst, %(dest)s, 15077141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 15087141Sgblack@eecs.umich.edu } else { 15097146Sgblack@eecs.umich.edu return new %(mnem)sReg(machInst, %(dest)s, 15107141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 15117141Sgblack@eecs.umich.edu } 15127141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 15137141Sgblack@eecs.umich.edu 15147141Sgblack@eecs.umich.edu decode_block = ''' 15157141Sgblack@eecs.umich.edu { 15167141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 15177141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 15187141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 15197141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 15207141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 15217141Sgblack@eecs.umich.edu const uint32_t amt = (bits(machInst, 14, 12) << 2) | 15227141Sgblack@eecs.umich.edu bits(machInst, 7, 6); 15237141Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 15247141Sgblack@eecs.umich.edu switch (op) { 15257141Sgblack@eecs.umich.edu case 0x0: 15267141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 15277141Sgblack@eecs.umich.edu %(tst)s 15287141Sgblack@eecs.umich.edu } else { 15297141Sgblack@eecs.umich.edu %(and)s 15307141Sgblack@eecs.umich.edu } 15317141Sgblack@eecs.umich.edu case 0x1: 15327141Sgblack@eecs.umich.edu %(bic)s 15337141Sgblack@eecs.umich.edu case 0x2: 15347141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 15357141Sgblack@eecs.umich.edu %(mov)s 15367141Sgblack@eecs.umich.edu } else { 15377141Sgblack@eecs.umich.edu %(orr)s 15387141Sgblack@eecs.umich.edu } 15397141Sgblack@eecs.umich.edu case 0x3: 15407141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 15417141Sgblack@eecs.umich.edu %(mvn)s 15427141Sgblack@eecs.umich.edu } else { 15437141Sgblack@eecs.umich.edu %(orn)s 15447141Sgblack@eecs.umich.edu } 15457141Sgblack@eecs.umich.edu case 0x4: 15467141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 15477141Sgblack@eecs.umich.edu %(teq)s 15487141Sgblack@eecs.umich.edu } else { 15497141Sgblack@eecs.umich.edu %(eor)s 15507141Sgblack@eecs.umich.edu } 15517141Sgblack@eecs.umich.edu case 0x6: 15527237Sgblack@eecs.umich.edu if (type) { 15537237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, rn, rm, amt, type); 15547237Sgblack@eecs.umich.edu } else { 15557237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, rn, rm, amt, type); 15567237Sgblack@eecs.umich.edu } 15577141Sgblack@eecs.umich.edu case 0x8: 15587141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 15597141Sgblack@eecs.umich.edu %(cmn)s 15607141Sgblack@eecs.umich.edu } else { 15617141Sgblack@eecs.umich.edu %(add)s 15627141Sgblack@eecs.umich.edu } 15637141Sgblack@eecs.umich.edu case 0xa: 15647141Sgblack@eecs.umich.edu %(adc)s 15657141Sgblack@eecs.umich.edu case 0xb: 15667141Sgblack@eecs.umich.edu %(sbc)s 15677141Sgblack@eecs.umich.edu case 0xd: 15687141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 15697141Sgblack@eecs.umich.edu %(cmp)s 15707141Sgblack@eecs.umich.edu } else { 15717141Sgblack@eecs.umich.edu %(sub)s 15727141Sgblack@eecs.umich.edu } 15737141Sgblack@eecs.umich.edu case 0xe: 15747141Sgblack@eecs.umich.edu %(rsb)s 15757141Sgblack@eecs.umich.edu default: 15767141Sgblack@eecs.umich.edu return new Unknown(machInst); 15777141Sgblack@eecs.umich.edu } 15787141Sgblack@eecs.umich.edu } 15797141Sgblack@eecs.umich.edu ''' % { 15807141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 15817141Sgblack@eecs.umich.edu "and" : decInst("And"), 15827141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 15837141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 15847141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 15857141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 15867141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 15877141Sgblack@eecs.umich.edu "teq" : decInst("Teq", "INTREG_ZERO"), 15887141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 15897141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", "INTREG_ZERO"), 15907141Sgblack@eecs.umich.edu "add" : decInst("Add"), 15917141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 15927141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 15937141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", "INTREG_ZERO"), 15947141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 15957141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 15967141Sgblack@eecs.umich.edu } 15977141Sgblack@eecs.umich.edu}}; 1598