1// -*- mode:c++ -*-
2
3// Copyright (c) 2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Giacomo Travaglini
39
40let {{
41    header_output = '''
42    StaticInstPtr
43    decodeCryptoAES(ExtMachInst machInst);
44
45    StaticInstPtr
46    decodeCryptoThreeRegSHA(ExtMachInst machInst);
47
48    StaticInstPtr
49    decodeCryptoTwoRegSHA(ExtMachInst machInst);
50    '''
51
52    decoder_output = '''
53
54    StaticInstPtr
55    decodeCryptoAES(ExtMachInst machInst)
56    {
57        const auto opcode = bits(machInst, 16, 12);
58        const auto size = bits(machInst, 23, 22);
59
60        IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
61        IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
62
63        if (size) {
64            // UNALLOCATED
65            return new Unknown64(machInst);
66        } else {
67            switch (opcode) {
68              case 0x4: return new AESE64(machInst, rd, rd, rn);
69              case 0x5: return new AESD64(machInst, rd, rd, rn);
70              case 0x6: return new AESMC64(machInst, rd, rn);
71              case 0x7: return new AESIMC64(machInst, rd, rn);
72              default: return new Unknown64(machInst);
73            }
74        }
75    }
76
77    StaticInstPtr
78    decodeCryptoTwoRegSHA(ExtMachInst machInst)
79    {
80        const auto opcode = bits(machInst, 16, 12);
81        const auto size = bits(machInst, 23, 22);
82
83        IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
84        IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
85
86        if (size) {
87            // UNALLOCATED
88            return new Unknown64(machInst);
89        } else {
90            switch (opcode) {
91              case 0x0: return new SHA1H64(machInst, rd, rn);
92              case 0x1: return new SHA1SU164(machInst, rd, rn);
93              case 0x2: return new SHA256SU064(machInst, rd, rn);
94              default: return new Unknown64(machInst);
95            }
96        }
97    }
98
99    StaticInstPtr
100    decodeCryptoThreeRegSHA(ExtMachInst machInst)
101    {
102        const auto opcode = bits(machInst, 14, 12);
103        const auto size = bits(machInst, 23, 22);
104
105        IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
106        IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
107        IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
108
109        if (size) {
110            // UNALLOCATED
111            return new Unknown64(machInst);
112        } else {
113            switch (opcode) {
114              case 0x0: return new SHA1C64(machInst, rd, rn, rm);
115              case 0x1: return new SHA1P64(machInst, rd, rn, rm);
116              case 0x2: return new SHA1M64(machInst, rd, rn, rm);
117              case 0x3: return new SHA1SU064(machInst, rd, rn, rm);
118              case 0x4: return new SHA256H64(machInst, rd, rn, rm);
119              case 0x5: return new SHA256H264(machInst, rd, rn, rm);
120              case 0x6: return new SHA256SU164(machInst, rd, rn, rm);
121              default: return new Unknown64(machInst);
122            }
123        }
124    }
125   '''
126}};
127