branch.isa revision 7602
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 37152Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47152Sgblack@eecs.umich.edu// All rights reserved 57152Sgblack@eecs.umich.edu// 67152Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77152Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87152Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97152Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107152Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117152Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127152Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137152Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147152Sgblack@eecs.umich.edu// 156019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu// All rights reserved. 176019Shines@cs.fsu.edu// 186019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu// this software without specific prior written permission. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu// 416019Shines@cs.fsu.edu// Authors: Stephen Hines 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 446019Shines@cs.fsu.edu// 456019Shines@cs.fsu.edu// Control transfer instructions 466019Shines@cs.fsu.edu// 476019Shines@cs.fsu.edu 487152Sgblack@eecs.umich.edudef format ArmBBlxImm() {{ 497152Sgblack@eecs.umich.edu decode_block = ''' 507152Sgblack@eecs.umich.edu if (machInst.condCode == 0xF) { 517152Sgblack@eecs.umich.edu int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 527152Sgblack@eecs.umich.edu (bits(machInst, 24) << 1); 537602SGene.Wu@arm.com return new BlxImm(machInst, imm, COND_UC); 547152Sgblack@eecs.umich.edu } else { 557152Sgblack@eecs.umich.edu return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2), 567152Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)machInst.condCode); 577152Sgblack@eecs.umich.edu } 587152Sgblack@eecs.umich.edu ''' 597152Sgblack@eecs.umich.edu}}; 607152Sgblack@eecs.umich.edu 617152Sgblack@eecs.umich.edudef format ArmBlBlxImm() {{ 627152Sgblack@eecs.umich.edu decode_block = ''' 637152Sgblack@eecs.umich.edu if (machInst.condCode == 0xF) { 647152Sgblack@eecs.umich.edu int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 657152Sgblack@eecs.umich.edu (bits(machInst, 24) << 1); 667602SGene.Wu@arm.com return new BlxImm(machInst, imm, COND_UC); 677152Sgblack@eecs.umich.edu } else { 687152Sgblack@eecs.umich.edu return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2), 697152Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)machInst.condCode); 707152Sgblack@eecs.umich.edu } 717152Sgblack@eecs.umich.edu ''' 727152Sgblack@eecs.umich.edu}}; 737152Sgblack@eecs.umich.edu 747252Sgblack@eecs.umich.edudef format ArmBxClz() {{ 757152Sgblack@eecs.umich.edu decode_block = ''' 767252Sgblack@eecs.umich.edu { 777252Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 787252Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 797252Sgblack@eecs.umich.edu if (OPCODE == 0x9) { 807252Sgblack@eecs.umich.edu return new BxReg(machInst, rm, 817252Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)machInst.condCode); 827252Sgblack@eecs.umich.edu } else if (OPCODE == 0xb) { 837252Sgblack@eecs.umich.edu return new Clz(machInst, rd, rm); 847252Sgblack@eecs.umich.edu } else { 857252Sgblack@eecs.umich.edu return new Unknown(machInst); 867252Sgblack@eecs.umich.edu } 877252Sgblack@eecs.umich.edu } 887152Sgblack@eecs.umich.edu ''' 897152Sgblack@eecs.umich.edu}}; 907152Sgblack@eecs.umich.edu 917152Sgblack@eecs.umich.edudef format ArmBlxReg() {{ 927152Sgblack@eecs.umich.edu decode_block = ''' 937152Sgblack@eecs.umich.edu return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), 947152Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)machInst.condCode); 957152Sgblack@eecs.umich.edu ''' 967152Sgblack@eecs.umich.edu}}; 977154Sgblack@eecs.umich.edu 987154Sgblack@eecs.umich.edudef format Thumb16CondBranchAndSvc() {{ 997154Sgblack@eecs.umich.edu decode_block = ''' 1007154Sgblack@eecs.umich.edu if (bits(machInst, 11, 9) != 0x7) { 1017154Sgblack@eecs.umich.edu return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1), 1027154Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)bits(machInst, 11, 8)); 1037154Sgblack@eecs.umich.edu } else if (bits(machInst, 8)) { 1047200Sgblack@eecs.umich.edu return new Svc(machInst); 1057154Sgblack@eecs.umich.edu } else { 1067154Sgblack@eecs.umich.edu // This space will not be allocated in the future. 1077281Sgblack@eecs.umich.edu return new Unknown(machInst); 1087154Sgblack@eecs.umich.edu } 1097154Sgblack@eecs.umich.edu ''' 1107154Sgblack@eecs.umich.edu}}; 1117154Sgblack@eecs.umich.edu 1127154Sgblack@eecs.umich.edudef format Thumb16UncondBranch() {{ 1137154Sgblack@eecs.umich.edu decode_block = ''' 1147154Sgblack@eecs.umich.edu return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC); 1157154Sgblack@eecs.umich.edu ''' 1167154Sgblack@eecs.umich.edu}}; 1177154Sgblack@eecs.umich.edu 1187155Sgblack@eecs.umich.edudef format Thumb32BranchesAndMiscCtrl() {{ 1197154Sgblack@eecs.umich.edu decode_block = ''' 1207155Sgblack@eecs.umich.edu { 1217155Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 26, 20); 1227155Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 14, 12); 1237155Sgblack@eecs.umich.edu switch (op1 & 0x5) { 1247155Sgblack@eecs.umich.edu case 0x0: 1257155Sgblack@eecs.umich.edu if (op == 127) { 1267155Sgblack@eecs.umich.edu if (op1 & 0x2) { 1277281Sgblack@eecs.umich.edu // Permanently undefined. 1287281Sgblack@eecs.umich.edu return new Unknown(machInst); 1297155Sgblack@eecs.umich.edu } else { 1307155Sgblack@eecs.umich.edu return new WarnUnimplemented("smc", machInst); 1317155Sgblack@eecs.umich.edu } 1327155Sgblack@eecs.umich.edu } else if ((op & 0x38) != 0x38) { 1337155Sgblack@eecs.umich.edu const uint32_t s = bits(machInst, 26); 1347155Sgblack@eecs.umich.edu const uint32_t j1 = bits(machInst, 13); 1357155Sgblack@eecs.umich.edu const uint32_t j2 = bits(machInst, 11); 1367155Sgblack@eecs.umich.edu const uint32_t imm6 = bits(machInst, 21, 16); 1377155Sgblack@eecs.umich.edu const uint32_t imm11 = bits(machInst, 10, 0); 1387155Sgblack@eecs.umich.edu const int32_t imm = sext<21>((s << 20) | 1397155Sgblack@eecs.umich.edu (j2 << 19) | (j1 << 18) | 1407155Sgblack@eecs.umich.edu (imm6 << 12) | (imm11 << 1)); 1417155Sgblack@eecs.umich.edu return new B(machInst, imm, 1427155Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)bits(machInst, 25, 22)); 1437155Sgblack@eecs.umich.edu } else { 1447155Sgblack@eecs.umich.edu switch (op) { 1457155Sgblack@eecs.umich.edu case 0x38: 1467204Sgblack@eecs.umich.edu { 1477204Sgblack@eecs.umich.edu const IntRegIndex rn = 1487204Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1497204Sgblack@eecs.umich.edu const uint8_t byteMask = bits(machInst, 11, 8); 1507204Sgblack@eecs.umich.edu return new MsrCpsrReg(machInst, rn, byteMask); 1517155Sgblack@eecs.umich.edu } 1527155Sgblack@eecs.umich.edu case 0x39: 1537204Sgblack@eecs.umich.edu { 1547204Sgblack@eecs.umich.edu const IntRegIndex rn = 1557204Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1567204Sgblack@eecs.umich.edu const uint8_t byteMask = bits(machInst, 11, 8); 1577204Sgblack@eecs.umich.edu return new MsrSpsrReg(machInst, rn, byteMask); 1587204Sgblack@eecs.umich.edu } 1597155Sgblack@eecs.umich.edu case 0x3a: 1607155Sgblack@eecs.umich.edu { 1617155Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 10, 8); 1627155Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 0); 1637155Sgblack@eecs.umich.edu if (op1 != 0) { 1647316Sgblack@eecs.umich.edu const bool enable = bits(machInst, 10, 9) == 0x2; 1657316Sgblack@eecs.umich.edu const uint32_t mods = bits(machInst, 8, 0) | 1667316Sgblack@eecs.umich.edu ((enable ? 1 : 0) << 9); 1677316Sgblack@eecs.umich.edu return new Cps(machInst, mods); 1687155Sgblack@eecs.umich.edu } else if ((op2 & 0xf0) == 0xf0) { 1697155Sgblack@eecs.umich.edu return new WarnUnimplemented("dbg", machInst); 1707155Sgblack@eecs.umich.edu } else { 1717155Sgblack@eecs.umich.edu switch (op2) { 1727155Sgblack@eecs.umich.edu case 0x0: 1737248Sgblack@eecs.umich.edu return new NopInst(machInst); 1747155Sgblack@eecs.umich.edu case 0x1: 1757419Sgblack@eecs.umich.edu return new YieldInst(machInst); 1767155Sgblack@eecs.umich.edu case 0x2: 1777419Sgblack@eecs.umich.edu return new WfeInst(machInst); 1787155Sgblack@eecs.umich.edu case 0x3: 1797419Sgblack@eecs.umich.edu return new WfiInst(machInst); 1807155Sgblack@eecs.umich.edu case 0x4: 1817419Sgblack@eecs.umich.edu return new SevInst(machInst); 1827155Sgblack@eecs.umich.edu default: 1837155Sgblack@eecs.umich.edu break; 1847155Sgblack@eecs.umich.edu } 1857155Sgblack@eecs.umich.edu } 1867155Sgblack@eecs.umich.edu break; 1877155Sgblack@eecs.umich.edu } 1887155Sgblack@eecs.umich.edu case 0x3b: 1897155Sgblack@eecs.umich.edu { 1907155Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 7, 4); 1917155Sgblack@eecs.umich.edu switch (op) { 1927155Sgblack@eecs.umich.edu case 0x0: 1937284Sgblack@eecs.umich.edu return new Leavex(machInst); 1947155Sgblack@eecs.umich.edu case 0x1: 1957284Sgblack@eecs.umich.edu return new Enterx(machInst); 1967155Sgblack@eecs.umich.edu case 0x2: 1977155Sgblack@eecs.umich.edu return new WarnUnimplemented("clrex", machInst); 1987155Sgblack@eecs.umich.edu case 0x4: 1997155Sgblack@eecs.umich.edu return new WarnUnimplemented("dsb", machInst); 2007155Sgblack@eecs.umich.edu case 0x5: 2017155Sgblack@eecs.umich.edu return new WarnUnimplemented("dmb", machInst); 2027155Sgblack@eecs.umich.edu case 0x6: 2037155Sgblack@eecs.umich.edu return new WarnUnimplemented("isb", machInst); 2047155Sgblack@eecs.umich.edu default: 2057155Sgblack@eecs.umich.edu break; 2067155Sgblack@eecs.umich.edu } 2077155Sgblack@eecs.umich.edu break; 2087155Sgblack@eecs.umich.edu } 2097155Sgblack@eecs.umich.edu case 0x3c: 2107344SAli.Saidi@ARM.com { 2117344SAli.Saidi@ARM.com // On systems that don't support bxj, bxj == bx 2127344SAli.Saidi@ARM.com return new BxReg(machInst, 2137344SAli.Saidi@ARM.com (IntRegIndex)(uint32_t)bits(machInst, 19, 16), 2147344SAli.Saidi@ARM.com COND_UC); 2157344SAli.Saidi@ARM.com } 2167155Sgblack@eecs.umich.edu case 0x3d: 2177188Sgblack@eecs.umich.edu { 2187188Sgblack@eecs.umich.edu const uint32_t imm32 = bits(machInst, 7, 0); 2197188Sgblack@eecs.umich.edu return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR, 2207188Sgblack@eecs.umich.edu imm32, false); 2217188Sgblack@eecs.umich.edu } 2227155Sgblack@eecs.umich.edu case 0x3e: 2237204Sgblack@eecs.umich.edu { 2247204Sgblack@eecs.umich.edu const IntRegIndex rd = 2257204Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 2267204Sgblack@eecs.umich.edu return new MrsCpsr(machInst, rd); 2277204Sgblack@eecs.umich.edu } 2287155Sgblack@eecs.umich.edu case 0x3f: 2297204Sgblack@eecs.umich.edu { 2307204Sgblack@eecs.umich.edu const IntRegIndex rd = 2317204Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 2327204Sgblack@eecs.umich.edu return new MrsSpsr(machInst, rd); 2337204Sgblack@eecs.umich.edu } 2347155Sgblack@eecs.umich.edu } 2357155Sgblack@eecs.umich.edu break; 2367155Sgblack@eecs.umich.edu } 2377155Sgblack@eecs.umich.edu case 0x1: 2387155Sgblack@eecs.umich.edu { 2397602SGene.Wu@arm.com ConditionCode condCode; 2407602SGene.Wu@arm.com if(machInst.itstateMask) { 2417602SGene.Wu@arm.com condCode = (ConditionCode)(uint8_t)machInst.itstateCond; 2427602SGene.Wu@arm.com } else { 2437602SGene.Wu@arm.com condCode = COND_UC; 2447602SGene.Wu@arm.com } 2457602SGene.Wu@arm.com 2467155Sgblack@eecs.umich.edu const uint32_t s = bits(machInst, 26); 2477155Sgblack@eecs.umich.edu const uint32_t i1 = !(bits(machInst, 13) ^ s); 2487155Sgblack@eecs.umich.edu const uint32_t i2 = !(bits(machInst, 11) ^ s); 2497155Sgblack@eecs.umich.edu const uint32_t imm10 = bits(machInst, 25, 16); 2507155Sgblack@eecs.umich.edu const uint32_t imm11 = bits(machInst, 10, 0); 2517155Sgblack@eecs.umich.edu const int32_t imm = sext<25>((s << 24) | 2527155Sgblack@eecs.umich.edu (i1 << 23) | (i2 << 22) | 2537155Sgblack@eecs.umich.edu (imm10 << 12) | (imm11 << 1)); 2547602SGene.Wu@arm.com return new B(machInst, imm, condCode); 2557155Sgblack@eecs.umich.edu } 2567155Sgblack@eecs.umich.edu case 0x4: 2577155Sgblack@eecs.umich.edu { 2587290Sgblack@eecs.umich.edu if (bits(machInst, 0) == 1) { 2597290Sgblack@eecs.umich.edu return new Unknown(machInst); 2607290Sgblack@eecs.umich.edu } 2617602SGene.Wu@arm.com ConditionCode condCode; 2627602SGene.Wu@arm.com if(machInst.itstateMask) { 2637602SGene.Wu@arm.com condCode = (ConditionCode)(uint8_t)machInst.itstateCond; 2647602SGene.Wu@arm.com } else { 2657602SGene.Wu@arm.com condCode = COND_UC; 2667602SGene.Wu@arm.com } 2677155Sgblack@eecs.umich.edu const uint32_t s = bits(machInst, 26); 2687155Sgblack@eecs.umich.edu const uint32_t i1 = !(bits(machInst, 13) ^ s); 2697155Sgblack@eecs.umich.edu const uint32_t i2 = !(bits(machInst, 11) ^ s); 2707155Sgblack@eecs.umich.edu const uint32_t imm10h = bits(machInst, 25, 16); 2717155Sgblack@eecs.umich.edu const uint32_t imm10l = bits(machInst, 10, 1); 2727155Sgblack@eecs.umich.edu const int32_t imm = sext<25>((s << 24) | 2737155Sgblack@eecs.umich.edu (i1 << 23) | (i2 << 22) | 2747155Sgblack@eecs.umich.edu (imm10h << 12) | (imm10l << 2)); 2757602SGene.Wu@arm.com return new BlxImm(machInst, imm, condCode); 2767155Sgblack@eecs.umich.edu } 2777155Sgblack@eecs.umich.edu case 0x5: 2787155Sgblack@eecs.umich.edu { 2797602SGene.Wu@arm.com ConditionCode condCode; 2807602SGene.Wu@arm.com if(machInst.itstateMask) { 2817602SGene.Wu@arm.com condCode = (ConditionCode)(uint8_t)machInst.itstateCond; 2827602SGene.Wu@arm.com } else { 2837602SGene.Wu@arm.com condCode = COND_UC; 2847602SGene.Wu@arm.com } 2857155Sgblack@eecs.umich.edu const uint32_t s = bits(machInst, 26); 2867155Sgblack@eecs.umich.edu const uint32_t i1 = !(bits(machInst, 13) ^ s); 2877155Sgblack@eecs.umich.edu const uint32_t i2 = !(bits(machInst, 11) ^ s); 2887155Sgblack@eecs.umich.edu const uint32_t imm10 = bits(machInst, 25, 16); 2897155Sgblack@eecs.umich.edu const uint32_t imm11 = bits(machInst, 10, 0); 2907155Sgblack@eecs.umich.edu const int32_t imm = sext<25>((s << 24) | 2917155Sgblack@eecs.umich.edu (i1 << 23) | (i2 << 22) | 2927155Sgblack@eecs.umich.edu (imm10 << 12) | (imm11 << 1)); 2937602SGene.Wu@arm.com return new Bl(machInst, imm, condCode); 2947155Sgblack@eecs.umich.edu } 2957155Sgblack@eecs.umich.edu default: 2967155Sgblack@eecs.umich.edu break; 2977155Sgblack@eecs.umich.edu } 2987155Sgblack@eecs.umich.edu return new Unknown(machInst); 2997155Sgblack@eecs.umich.edu } 3007154Sgblack@eecs.umich.edu ''' 3017154Sgblack@eecs.umich.edu}}; 302