isa.cc revision 8059
17405SAli.Saidi@ARM.com/* 27405SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 427678Sgblack@eecs.umich.edu#include "sim/faults.hh" 438059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 447405SAli.Saidi@ARM.com 457405SAli.Saidi@ARM.comnamespace ArmISA 467405SAli.Saidi@ARM.com{ 477405SAli.Saidi@ARM.com 487427Sgblack@eecs.umich.eduvoid 497427Sgblack@eecs.umich.eduISA::clear() 507427Sgblack@eecs.umich.edu{ 517427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 527427Sgblack@eecs.umich.edu 537427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 547427Sgblack@eecs.umich.edu CPSR cpsr = 0; 557427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 567427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 577427Sgblack@eecs.umich.edu updateRegMap(cpsr); 587427Sgblack@eecs.umich.edu 597427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 607604SGene.Wu@arm.com sctlr.te = (bool)sctlr_rst.te; 617427Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 627427Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 637427Sgblack@eecs.umich.edu sctlr.u = 1; 647427Sgblack@eecs.umich.edu sctlr.xp = 1; 657427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 667427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 677427Sgblack@eecs.umich.edu sctlr.rao4 = 1; 687427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 697427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 707427Sgblack@eecs.umich.edu 717427Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 727427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 737427Sgblack@eecs.umich.edu 747427Sgblack@eecs.umich.edu /* 757427Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 767427Sgblack@eecs.umich.edu * Variant = 0, 777427Sgblack@eecs.umich.edu */ 787427Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = 797645Sali.saidi@arm.com (0x35 << 24) | // Implementor is '5' from "M5" 807645Sali.saidi@arm.com (0 << 20) | // Variant 817645Sali.saidi@arm.com (0xf << 16) | // Architecture from CPUID scheme 827645Sali.saidi@arm.com (0xf00 << 4) | // Primary part number 837645Sali.saidi@arm.com (0 << 0) | // Revision 847427Sgblack@eecs.umich.edu 0; 857427Sgblack@eecs.umich.edu 867427Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 877427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 887427Sgblack@eecs.umich.edu 897427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 907427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 917427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 927427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 937427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 947427Sgblack@eecs.umich.edu mvfr0.divide = 1; 957427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 967427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 977427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 987427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 997427Sgblack@eecs.umich.edu 1007427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1017427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1027427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1037427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1047427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1057427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1067427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1077427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1087427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1097427Sgblack@eecs.umich.edu 1107427Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1117427Sgblack@eecs.umich.edu 1127436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1137436Sdam.sunwoo@arm.com 1147436Sdam.sunwoo@arm.com miscRegs[MISCREG_PRRR] = 1157436Sdam.sunwoo@arm.com (1 << 19) | // 19 1167436Sdam.sunwoo@arm.com (0 << 18) | // 18 1177436Sdam.sunwoo@arm.com (0 << 17) | // 17 1187436Sdam.sunwoo@arm.com (1 << 16) | // 16 1197436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1207436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1217436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1227436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1237436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1247436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1257436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1267436Sdam.sunwoo@arm.com 0; // 1:0 1277436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR] = 1287436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1297436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1307436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1317436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1327436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1337436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1347436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1357436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1367436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1377436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1387436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1397436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1407436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1417436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1427436Sdam.sunwoo@arm.com 0; // 1:0 1437436Sdam.sunwoo@arm.com 1447644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 1457644Sali.saidi@arm.com miscRegs[MISCREG_FPSID] = 0x410430A0; 1467427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1477427Sgblack@eecs.umich.edu} 1487427Sgblack@eecs.umich.edu 1497405SAli.Saidi@ARM.comMiscReg 1507405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) 1517405SAli.Saidi@ARM.com{ 1527405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1537614Sminkyu.jeong@arm.com 1547614Sminkyu.jeong@arm.com int flat_idx; 1557614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 1567614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 1577614Sminkyu.jeong@arm.com else 1587614Sminkyu.jeong@arm.com flat_idx = misc_reg; 1597614Sminkyu.jeong@arm.com MiscReg val = miscRegs[flat_idx]; 1607614Sminkyu.jeong@arm.com 1617614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1627614Sminkyu.jeong@arm.com misc_reg, flat_idx, val); 1637614Sminkyu.jeong@arm.com return val; 1647405SAli.Saidi@ARM.com} 1657405SAli.Saidi@ARM.com 1667405SAli.Saidi@ARM.com 1677405SAli.Saidi@ARM.comMiscReg 1687405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1697405SAli.Saidi@ARM.com{ 1707405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 1717405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 1727720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1737720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 1747720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 1757405SAli.Saidi@ARM.com return cpsr; 1767405SAli.Saidi@ARM.com } 1777757SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START) 1787405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 1797405SAli.Saidi@ARM.com miscRegName[misc_reg]); 1807757SAli.Saidi@ARM.com 1817405SAli.Saidi@ARM.com switch (misc_reg) { 1827405SAli.Saidi@ARM.com case MISCREG_CLIDR: 1837731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 1847405SAli.Saidi@ARM.com break; 1857405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 1867731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 1877405SAli.Saidi@ARM.com "always reads as 0.\n"); 1887405SAli.Saidi@ARM.com break; 1897405SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 1907588SAli.Saidi@arm.com warn("Returning thumbEE disabled for now since we don't support CP14" 1917588SAli.Saidi@arm.com "config registers and jumping to ThumbEE vectors\n"); 1927588SAli.Saidi@arm.com return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 1937583SAli.Saidi@arm.com case MISCREG_ID_MMFR0: 1947583SAli.Saidi@arm.com return 0x03; //VMSAz7 1957583SAli.Saidi@arm.com case MISCREG_CTR: 1967583SAli.Saidi@arm.com return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 1977583SAli.Saidi@arm.com case MISCREG_ACTLR: 1987583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 1997583SAli.Saidi@arm.com break; 2007583SAli.Saidi@arm.com case MISCREG_PMCR: 2017583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 2027583SAli.Saidi@arm.com case MISCREG_PMSELR: 2037583SAli.Saidi@arm.com warn("Not doing anyhting for read to miscreg %s\n", 2047583SAli.Saidi@arm.com miscRegName[misc_reg]); 2057583SAli.Saidi@arm.com break; 2067783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 2077783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2087783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 2097783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2107405SAli.Saidi@ARM.com } 2117405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 2127405SAli.Saidi@ARM.com} 2137405SAli.Saidi@ARM.com 2147405SAli.Saidi@ARM.comvoid 2157405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2167405SAli.Saidi@ARM.com{ 2177405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 2187614Sminkyu.jeong@arm.com 2197614Sminkyu.jeong@arm.com int flat_idx; 2207614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 2217614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 2227614Sminkyu.jeong@arm.com else 2237614Sminkyu.jeong@arm.com flat_idx = misc_reg; 2247614Sminkyu.jeong@arm.com miscRegs[flat_idx] = val; 2257614Sminkyu.jeong@arm.com 2267614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2277614Sminkyu.jeong@arm.com flat_idx, val); 2287405SAli.Saidi@ARM.com} 2297405SAli.Saidi@ARM.com 2307405SAli.Saidi@ARM.comvoid 2317405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2327405SAli.Saidi@ARM.com{ 2337749SAli.Saidi@ARM.com 2347405SAli.Saidi@ARM.com MiscReg newVal = val; 2357405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 2367405SAli.Saidi@ARM.com updateRegMap(val); 2377749SAli.Saidi@ARM.com 2387749SAli.Saidi@ARM.com 2397749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 2407749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 2417405SAli.Saidi@ARM.com CPSR cpsr = val; 2427749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 2437749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 2447749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 2457749SAli.Saidi@ARM.com } 2467749SAli.Saidi@ARM.com 2477614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2487614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2497720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 2507720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 2517720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 2527720Sgblack@eecs.umich.edu tc->pcState(pc); 2537408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 2547405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 2557405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 2567405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 2577408Sgblack@eecs.umich.edu } else { 2587408Sgblack@eecs.umich.edu switch (misc_reg) { 2597408Sgblack@eecs.umich.edu case MISCREG_ITSTATE: 2607408Sgblack@eecs.umich.edu { 2617408Sgblack@eecs.umich.edu ITSTATE itstate = newVal; 2627408Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 2637408Sgblack@eecs.umich.edu cpsr.it1 = itstate.bottom2; 2647408Sgblack@eecs.umich.edu cpsr.it2 = itstate.top6; 2657408Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 2667408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, 2677408Sgblack@eecs.umich.edu "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 2687408Sgblack@eecs.umich.edu (uint8_t)itstate, (uint32_t)cpsr); 2697405SAli.Saidi@ARM.com } 2707408Sgblack@eecs.umich.edu break; 2717408Sgblack@eecs.umich.edu case MISCREG_CPACR: 2727408Sgblack@eecs.umich.edu { 2737408Sgblack@eecs.umich.edu CPACR newCpacr = 0; 2747408Sgblack@eecs.umich.edu CPACR valCpacr = val; 2757408Sgblack@eecs.umich.edu newCpacr.cp10 = valCpacr.cp10; 2767408Sgblack@eecs.umich.edu newCpacr.cp11 = valCpacr.cp11; 2777640Sgblack@eecs.umich.edu //XXX d32dis isn't implemented. The manual says whether or not 2787640Sgblack@eecs.umich.edu //it works is implementation defined. 2797640Sgblack@eecs.umich.edu newCpacr.asedis = valCpacr.asedis; 2807408Sgblack@eecs.umich.edu newVal = newCpacr; 2817408Sgblack@eecs.umich.edu } 2827408Sgblack@eecs.umich.edu break; 2837408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 2847731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 2857408Sgblack@eecs.umich.edu break; 2867408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 2877408Sgblack@eecs.umich.edu { 2887408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 2897408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 2907408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 2917408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 2927408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 2937408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 2947408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 2957408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 2967408Sgblack@eecs.umich.edu fpscrMask.len = ones; 2977408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 2987408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 2997408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3007408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3017408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3027408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3037408Sgblack@eecs.umich.edu fpscrMask.v = ones; 3047408Sgblack@eecs.umich.edu fpscrMask.c = ones; 3057408Sgblack@eecs.umich.edu fpscrMask.z = ones; 3067408Sgblack@eecs.umich.edu fpscrMask.n = ones; 3077408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3087408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3097408Sgblack@eecs.umich.edu } 3107408Sgblack@eecs.umich.edu break; 3117783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 3127783SGiacomo.Gabrielli@arm.com { 3137783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3147783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3157783SGiacomo.Gabrielli@arm.com } 3167783SGiacomo.Gabrielli@arm.com break; 3177783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 3187783SGiacomo.Gabrielli@arm.com { 3197783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 3207783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3217783SGiacomo.Gabrielli@arm.com } 3227783SGiacomo.Gabrielli@arm.com break; 3237408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3247408Sgblack@eecs.umich.edu { 3257408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3267408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3277408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3287408Sgblack@eecs.umich.edu } 3297408Sgblack@eecs.umich.edu break; 3307408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 3317408Sgblack@eecs.umich.edu { 3327408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3337408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3347408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3357408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3367408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3377749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 3387749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 3397408Sgblack@eecs.umich.edu return; 3407408Sgblack@eecs.umich.edu } 3417408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3427408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3437408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3447408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3457408Sgblack@eecs.umich.edu case MISCREG_FPSID: 3467408Sgblack@eecs.umich.edu return; 3477408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 3487408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 3497731SAli.Saidi@ARM.com warn_once("Need to flush all TLBs in MP\n"); 3507408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3517408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3527408Sgblack@eecs.umich.edu return; 3537408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 3547408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3557408Sgblack@eecs.umich.edu return; 3567408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 3577408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3587408Sgblack@eecs.umich.edu return; 3597408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 3607408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 3617731SAli.Saidi@ARM.com warn_once("Need to flush all TLBs in MP\n"); 3627408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3637408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3647408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3657408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3667408Sgblack@eecs.umich.edu return; 3677408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 3687408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 3697731SAli.Saidi@ARM.com warn_once("Need to flush all TLBs in MP\n"); 3707408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3717408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3727408Sgblack@eecs.umich.edu return; 3737408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 3747408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 3757731SAli.Saidi@ARM.com warn_once("Need to flush all TLBs in MP\n"); 3767408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 3777408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 3787408Sgblack@eecs.umich.edu return; 3797408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 3807408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3817408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3827408Sgblack@eecs.umich.edu return; 3837408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 3847408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3857408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3867408Sgblack@eecs.umich.edu return; 3877408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 3887408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3897408Sgblack@eecs.umich.edu return; 3907408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 3917408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3927405SAli.Saidi@ARM.com return; 3937583SAli.Saidi@arm.com case MISCREG_ACTLR: 3947583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 3957583SAli.Saidi@arm.com break; 3967583SAli.Saidi@arm.com case MISCREG_PMCR: 3978059SAli.Saidi@ARM.com { 3988059SAli.Saidi@ARM.com // Performance counters not implemented. Instead, interpret 3998059SAli.Saidi@ARM.com // a reset command to this register to reset the simulator 4008059SAli.Saidi@ARM.com // statistics. 4018059SAli.Saidi@ARM.com // PMCR_E | PMCR_P | PMCR_C 4028059SAli.Saidi@ARM.com const int ResetAndEnableCounters = 0x7; 4038059SAli.Saidi@ARM.com if (newVal == ResetAndEnableCounters) { 4048059SAli.Saidi@ARM.com inform("Resetting all simobject stats\n"); 4058059SAli.Saidi@ARM.com Stats::schedStatEvent(false, true); 4068059SAli.Saidi@ARM.com break; 4078059SAli.Saidi@ARM.com } 4088059SAli.Saidi@ARM.com } 4097583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 4107583SAli.Saidi@arm.com case MISCREG_PMSELR: 4117583SAli.Saidi@arm.com warn("Not doing anything for write to miscreg %s\n", 4127583SAli.Saidi@arm.com miscRegName[misc_reg]); 4137583SAli.Saidi@arm.com break; 4147436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 4157436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4167436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 4177436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 4187436Sdam.sunwoo@arm.com case MISCREG_V2POWPR: 4197436Sdam.sunwoo@arm.com case MISCREG_V2POWPW: 4207436Sdam.sunwoo@arm.com case MISCREG_V2POWUR: 4217436Sdam.sunwoo@arm.com case MISCREG_V2POWUW: 4227436Sdam.sunwoo@arm.com { 4237436Sdam.sunwoo@arm.com RequestPtr req = new Request; 4247436Sdam.sunwoo@arm.com unsigned flags; 4257436Sdam.sunwoo@arm.com BaseTLB::Mode mode; 4267436Sdam.sunwoo@arm.com Fault fault; 4277436Sdam.sunwoo@arm.com switch(misc_reg) { 4287436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 4297436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4307436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4317436Sdam.sunwoo@arm.com break; 4327436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4337436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4347436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4357436Sdam.sunwoo@arm.com break; 4367436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 4377436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 4387436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4397436Sdam.sunwoo@arm.com break; 4407436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 4417436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 4427436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4437436Sdam.sunwoo@arm.com break; 4447442Ssaidi@eecs.umich.edu default: 4457436Sdam.sunwoo@arm.com panic("Security Extensions not implemented!"); 4467436Sdam.sunwoo@arm.com } 4477720Sgblack@eecs.umich.edu req->setVirt(0, val, 1, flags, tc->pcState().pc()); 4487436Sdam.sunwoo@arm.com fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 4497436Sdam.sunwoo@arm.com if (fault == NoFault) { 4507436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 4517436Sdam.sunwoo@arm.com (req->getPaddr() & 0xfffff000) | 4527436Sdam.sunwoo@arm.com (tc->getDTBPtr()->getAttr() ); 4537436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 4547436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 4557436Sdam.sunwoo@arm.com val, miscRegs[MISCREG_PAR]); 4567436Sdam.sunwoo@arm.com } 4577436Sdam.sunwoo@arm.com else { 4587436Sdam.sunwoo@arm.com // Set fault bit and FSR 4597436Sdam.sunwoo@arm.com FSR fsr = miscRegs[MISCREG_DFSR]; 4607436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 4617436Sdam.sunwoo@arm.com (fsr.ext << 6) | 4627436Sdam.sunwoo@arm.com (fsr.fsHigh << 5) | 4637436Sdam.sunwoo@arm.com (fsr.fsLow << 1) | 4647436Sdam.sunwoo@arm.com 0x1; // F bit 4657436Sdam.sunwoo@arm.com } 4667436Sdam.sunwoo@arm.com return; 4677436Sdam.sunwoo@arm.com } 4687749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 4697749SAli.Saidi@ARM.com case MISCREG_PRRR: 4707749SAli.Saidi@ARM.com case MISCREG_NMRR: 4717749SAli.Saidi@ARM.com case MISCREG_DACR: 4727749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 4737749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 4747749SAli.Saidi@ARM.com break; 4757749SAli.Saidi@ARM.com 4767405SAli.Saidi@ARM.com } 4777405SAli.Saidi@ARM.com } 4787405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 4797405SAli.Saidi@ARM.com} 4807405SAli.Saidi@ARM.com 4817405SAli.Saidi@ARM.com} 482