isa.cc revision 8059
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "sim/faults.hh"
43#include "sim/stat_control.hh"
44
45namespace ArmISA
46{
47
48void
49ISA::clear()
50{
51    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
52
53    memset(miscRegs, 0, sizeof(miscRegs));
54    CPSR cpsr = 0;
55    cpsr.mode = MODE_USER;
56    miscRegs[MISCREG_CPSR] = cpsr;
57    updateRegMap(cpsr);
58
59    SCTLR sctlr = 0;
60    sctlr.te = (bool)sctlr_rst.te;
61    sctlr.nmfi = (bool)sctlr_rst.nmfi;
62    sctlr.v = (bool)sctlr_rst.v;
63    sctlr.u    = 1;
64    sctlr.xp = 1;
65    sctlr.rao2 = 1;
66    sctlr.rao3 = 1;
67    sctlr.rao4 = 1;
68    miscRegs[MISCREG_SCTLR] = sctlr;
69    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
70
71    /* Start with an event in the mailbox */
72    miscRegs[MISCREG_SEV_MAILBOX] = 1;
73
74    /*
75     * Implemented = '5' from "M5",
76     * Variant = 0,
77     */
78    miscRegs[MISCREG_MIDR] =
79        (0x35 << 24) | // Implementor is '5' from "M5"
80        (0 << 20)    | // Variant
81        (0xf << 16)  | // Architecture from CPUID scheme
82        (0xf00 << 4) | // Primary part number
83        (0 << 0)     | // Revision
84        0;
85
86    // Separate Instruction and Data TLBs.
87    miscRegs[MISCREG_TLBTR] = 1;
88
89    MVFR0 mvfr0 = 0;
90    mvfr0.advSimdRegisters = 2;
91    mvfr0.singlePrecision = 2;
92    mvfr0.doublePrecision = 2;
93    mvfr0.vfpExceptionTrapping = 0;
94    mvfr0.divide = 1;
95    mvfr0.squareRoot = 1;
96    mvfr0.shortVectors = 1;
97    mvfr0.roundingModes = 1;
98    miscRegs[MISCREG_MVFR0] = mvfr0;
99
100    MVFR1 mvfr1 = 0;
101    mvfr1.flushToZero = 1;
102    mvfr1.defaultNaN = 1;
103    mvfr1.advSimdLoadStore = 1;
104    mvfr1.advSimdInteger = 1;
105    mvfr1.advSimdSinglePrecision = 1;
106    mvfr1.advSimdHalfPrecision = 1;
107    mvfr1.vfpHalfPrecision = 1;
108    miscRegs[MISCREG_MVFR1] = mvfr1;
109
110    miscRegs[MISCREG_MPIDR] = 0;
111
112    // Reset values of PRRR and NMRR are implementation dependent
113
114    miscRegs[MISCREG_PRRR] =
115        (1 << 19) | // 19
116        (0 << 18) | // 18
117        (0 << 17) | // 17
118        (1 << 16) | // 16
119        (2 << 14) | // 15:14
120        (0 << 12) | // 13:12
121        (2 << 10) | // 11:10
122        (2 << 8)  | // 9:8
123        (2 << 6)  | // 7:6
124        (2 << 4)  | // 5:4
125        (1 << 2)  | // 3:2
126        0;          // 1:0
127    miscRegs[MISCREG_NMRR] =
128        (1 << 30) | // 31:30
129        (0 << 26) | // 27:26
130        (0 << 24) | // 25:24
131        (3 << 22) | // 23:22
132        (2 << 20) | // 21:20
133        (0 << 18) | // 19:18
134        (0 << 16) | // 17:16
135        (1 << 14) | // 15:14
136        (0 << 12) | // 13:12
137        (2 << 10) | // 11:10
138        (0 << 8)  | // 9:8
139        (3 << 6)  | // 7:6
140        (2 << 4)  | // 5:4
141        (0 << 2)  | // 3:2
142        0;          // 1:0
143
144    miscRegs[MISCREG_CPACR] = 0;
145    miscRegs[MISCREG_FPSID] = 0x410430A0;
146    //XXX We need to initialize the rest of the state.
147}
148
149MiscReg
150ISA::readMiscRegNoEffect(int misc_reg)
151{
152    assert(misc_reg < NumMiscRegs);
153
154    int flat_idx;
155    if (misc_reg == MISCREG_SPSR)
156        flat_idx = flattenMiscIndex(misc_reg);
157    else
158        flat_idx = misc_reg;
159    MiscReg val = miscRegs[flat_idx];
160
161    DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
162            misc_reg, flat_idx, val);
163    return val;
164}
165
166
167MiscReg
168ISA::readMiscReg(int misc_reg, ThreadContext *tc)
169{
170    if (misc_reg == MISCREG_CPSR) {
171        CPSR cpsr = miscRegs[misc_reg];
172        PCState pc = tc->pcState();
173        cpsr.j = pc.jazelle() ? 1 : 0;
174        cpsr.t = pc.thumb() ? 1 : 0;
175        return cpsr;
176    }
177    if (misc_reg >= MISCREG_CP15_UNIMP_START)
178        panic("Unimplemented CP15 register %s read.\n",
179              miscRegName[misc_reg]);
180
181    switch (misc_reg) {
182      case MISCREG_CLIDR:
183        warn_once("The clidr register always reports 0 caches.\n");
184        break;
185      case MISCREG_CCSIDR:
186        warn_once("The ccsidr register isn't implemented and "
187                "always reads as 0.\n");
188        break;
189      case MISCREG_ID_PFR0:
190        warn("Returning thumbEE disabled for now since we don't support CP14"
191             "config registers and jumping to ThumbEE vectors\n");
192        return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
193      case MISCREG_ID_MMFR0:
194        return 0x03; //VMSAz7
195      case MISCREG_CTR:
196        return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
197      case MISCREG_ACTLR:
198        warn("Not doing anything for miscreg ACTLR\n");
199        break;
200      case MISCREG_PMCR:
201      case MISCREG_PMCCNTR:
202      case MISCREG_PMSELR:
203        warn("Not doing anyhting for read to miscreg %s\n",
204                miscRegName[misc_reg]);
205        break;
206      case MISCREG_FPSCR_QC:
207        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
208      case MISCREG_FPSCR_EXC:
209        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
210    }
211    return readMiscRegNoEffect(misc_reg);
212}
213
214void
215ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
216{
217    assert(misc_reg < NumMiscRegs);
218
219    int flat_idx;
220    if (misc_reg == MISCREG_SPSR)
221        flat_idx = flattenMiscIndex(misc_reg);
222    else
223        flat_idx = misc_reg;
224    miscRegs[flat_idx] = val;
225
226    DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
227            flat_idx, val);
228}
229
230void
231ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
232{
233
234    MiscReg newVal = val;
235    if (misc_reg == MISCREG_CPSR) {
236        updateRegMap(val);
237
238
239        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
240        int old_mode = old_cpsr.mode;
241        CPSR cpsr = val;
242        if (old_mode != cpsr.mode) {
243            tc->getITBPtr()->invalidateMiscReg();
244            tc->getDTBPtr()->invalidateMiscReg();
245        }
246
247        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
248                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
249        PCState pc = tc->pcState();
250        pc.nextThumb(cpsr.t);
251        pc.nextJazelle(cpsr.j);
252        tc->pcState(pc);
253    } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
254        misc_reg < MISCREG_CP15_END) {
255        panic("Unimplemented CP15 register %s wrote with %#x.\n",
256              miscRegName[misc_reg], val);
257    } else {
258        switch (misc_reg) {
259          case MISCREG_ITSTATE:
260            {
261                ITSTATE itstate = newVal;
262                CPSR cpsr = miscRegs[MISCREG_CPSR];
263                cpsr.it1 = itstate.bottom2;
264                cpsr.it2 = itstate.top6;
265                miscRegs[MISCREG_CPSR] = cpsr;
266                DPRINTF(MiscRegs,
267                        "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
268                        (uint8_t)itstate, (uint32_t)cpsr);
269            }
270            break;
271          case MISCREG_CPACR:
272            {
273                CPACR newCpacr = 0;
274                CPACR valCpacr = val;
275                newCpacr.cp10 = valCpacr.cp10;
276                newCpacr.cp11 = valCpacr.cp11;
277                //XXX d32dis isn't implemented. The manual says whether or not
278                //it works is implementation defined.
279                newCpacr.asedis = valCpacr.asedis;
280                newVal = newCpacr;
281            }
282            break;
283          case MISCREG_CSSELR:
284            warn_once("The csselr register isn't implemented.\n");
285            break;
286          case MISCREG_FPSCR:
287            {
288                const uint32_t ones = (uint32_t)(-1);
289                FPSCR fpscrMask = 0;
290                fpscrMask.ioc = ones;
291                fpscrMask.dzc = ones;
292                fpscrMask.ofc = ones;
293                fpscrMask.ufc = ones;
294                fpscrMask.ixc = ones;
295                fpscrMask.idc = ones;
296                fpscrMask.len = ones;
297                fpscrMask.stride = ones;
298                fpscrMask.rMode = ones;
299                fpscrMask.fz = ones;
300                fpscrMask.dn = ones;
301                fpscrMask.ahp = ones;
302                fpscrMask.qc = ones;
303                fpscrMask.v = ones;
304                fpscrMask.c = ones;
305                fpscrMask.z = ones;
306                fpscrMask.n = ones;
307                newVal = (newVal & (uint32_t)fpscrMask) |
308                         (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
309            }
310            break;
311          case MISCREG_FPSCR_QC:
312            {
313                newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
314                misc_reg = MISCREG_FPSCR;
315            }
316            break;
317          case MISCREG_FPSCR_EXC:
318            {
319                newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
320                misc_reg = MISCREG_FPSCR;
321            }
322            break;
323          case MISCREG_FPEXC:
324            {
325                const uint32_t fpexcMask = 0x60000000;
326                newVal = (newVal & fpexcMask) |
327                         (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
328            }
329            break;
330          case MISCREG_SCTLR:
331            {
332                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
333                SCTLR sctlr = miscRegs[MISCREG_SCTLR];
334                SCTLR new_sctlr = newVal;
335                new_sctlr.nmfi =  (bool)sctlr.nmfi;
336                miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
337                tc->getITBPtr()->invalidateMiscReg();
338                tc->getDTBPtr()->invalidateMiscReg();
339                return;
340            }
341          case MISCREG_TLBTR:
342          case MISCREG_MVFR0:
343          case MISCREG_MVFR1:
344          case MISCREG_MPIDR:
345          case MISCREG_FPSID:
346            return;
347          case MISCREG_TLBIALLIS:
348          case MISCREG_TLBIALL:
349            warn_once("Need to flush all TLBs in MP\n");
350            tc->getITBPtr()->flushAll();
351            tc->getDTBPtr()->flushAll();
352            return;
353          case MISCREG_ITLBIALL:
354            tc->getITBPtr()->flushAll();
355            return;
356          case MISCREG_DTLBIALL:
357            tc->getDTBPtr()->flushAll();
358            return;
359          case MISCREG_TLBIMVAIS:
360          case MISCREG_TLBIMVA:
361            warn_once("Need to flush all TLBs in MP\n");
362            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
363                    bits(newVal, 7,0));
364            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
365                    bits(newVal, 7,0));
366            return;
367          case MISCREG_TLBIASIDIS:
368          case MISCREG_TLBIASID:
369            warn_once("Need to flush all TLBs in MP\n");
370            tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
371            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
372            return;
373          case MISCREG_TLBIMVAAIS:
374          case MISCREG_TLBIMVAA:
375            warn_once("Need to flush all TLBs in MP\n");
376            tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
377            tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
378            return;
379          case MISCREG_ITLBIMVA:
380            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
381                    bits(newVal, 7,0));
382            return;
383          case MISCREG_DTLBIMVA:
384            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
385                    bits(newVal, 7,0));
386            return;
387          case MISCREG_ITLBIASID:
388            tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
389            return;
390          case MISCREG_DTLBIASID:
391            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
392            return;
393          case MISCREG_ACTLR:
394            warn("Not doing anything for write of miscreg ACTLR\n");
395            break;
396          case MISCREG_PMCR:
397            {
398              // Performance counters not implemented.  Instead, interpret
399              //   a reset command to this register to reset the simulator
400              //   statistics.
401              // PMCR_E | PMCR_P | PMCR_C
402              const int ResetAndEnableCounters = 0x7;
403              if (newVal == ResetAndEnableCounters) {
404                  inform("Resetting all simobject stats\n");
405                  Stats::schedStatEvent(false, true);
406                  break;
407              }
408            }
409          case MISCREG_PMCCNTR:
410          case MISCREG_PMSELR:
411            warn("Not doing anything for write to miscreg %s\n",
412                    miscRegName[misc_reg]);
413            break;
414          case MISCREG_V2PCWPR:
415          case MISCREG_V2PCWPW:
416          case MISCREG_V2PCWUR:
417          case MISCREG_V2PCWUW:
418          case MISCREG_V2POWPR:
419          case MISCREG_V2POWPW:
420          case MISCREG_V2POWUR:
421          case MISCREG_V2POWUW:
422            {
423              RequestPtr req = new Request;
424              unsigned flags;
425              BaseTLB::Mode mode;
426              Fault fault;
427              switch(misc_reg) {
428                  case MISCREG_V2PCWPR:
429                      flags = TLB::MustBeOne;
430                      mode = BaseTLB::Read;
431                      break;
432                  case MISCREG_V2PCWPW:
433                      flags = TLB::MustBeOne;
434                      mode = BaseTLB::Write;
435                      break;
436                  case MISCREG_V2PCWUR:
437                      flags = TLB::MustBeOne | TLB::UserMode;
438                      mode = BaseTLB::Read;
439                      break;
440                  case MISCREG_V2PCWUW:
441                      flags = TLB::MustBeOne | TLB::UserMode;
442                      mode = BaseTLB::Write;
443                      break;
444                  default:
445                      panic("Security Extensions not implemented!");
446              }
447              req->setVirt(0, val, 1, flags, tc->pcState().pc());
448              fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
449              if (fault == NoFault) {
450                  miscRegs[MISCREG_PAR] =
451                      (req->getPaddr() & 0xfffff000) |
452                      (tc->getDTBPtr()->getAttr() );
453                  DPRINTF(MiscRegs,
454                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
455                          val, miscRegs[MISCREG_PAR]);
456              }
457              else {
458                  // Set fault bit and FSR
459                  FSR fsr = miscRegs[MISCREG_DFSR];
460                  miscRegs[MISCREG_PAR] =
461                      (fsr.ext << 6) |
462                      (fsr.fsHigh << 5) |
463                      (fsr.fsLow << 1) |
464                      0x1; // F bit
465              }
466              return;
467            }
468          case MISCREG_CONTEXTIDR:
469          case MISCREG_PRRR:
470          case MISCREG_NMRR:
471          case MISCREG_DACR:
472            tc->getITBPtr()->invalidateMiscReg();
473            tc->getDTBPtr()->invalidateMiscReg();
474            break;
475
476        }
477    }
478    setMiscRegNoEffect(misc_reg, newVal);
479}
480
481}
482