isa.cc revision 10709
17405SAli.Saidi@ARM.com/* 210338SCurtis.Dunham@arm.com * Copyright (c) 2010-2014 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 448887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 4510461SAndreas.Sandberg@ARM.com#include "cpu/base.hh" 468232Snate@binkert.org#include "debug/Arm.hh" 478232Snate@binkert.org#include "debug/MiscRegs.hh" 489384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 497678Sgblack@eecs.umich.edu#include "sim/faults.hh" 508059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 518284SAli.Saidi@ARM.com#include "sim/system.hh" 527405SAli.Saidi@ARM.com 537405SAli.Saidi@ARM.comnamespace ArmISA 547405SAli.Saidi@ARM.com{ 557405SAli.Saidi@ARM.com 5610037SARM gem5 Developers 5710037SARM gem5 Developers/** 5810037SARM gem5 Developers * Some registers aliase with others, and therefore need to be translated. 5910037SARM gem5 Developers * For each entry: 6010037SARM gem5 Developers * The first value is the misc register that is to be looked up 6110037SARM gem5 Developers * the second value is the lower part of the translation 6210037SARM gem5 Developers * the third the upper part 6310037SARM gem5 Developers */ 6410037SARM gem5 Developersconst struct ISA::MiscRegInitializerEntry 6510037SARM gem5 Developers ISA::MiscRegSwitch[miscRegTranslateMax] = { 6610037SARM gem5 Developers {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}}, 6710037SARM gem5 Developers {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}}, 6810037SARM gem5 Developers {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 6910037SARM gem5 Developers {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}}, 7010037SARM gem5 Developers {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 7110037SARM gem5 Developers {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 7210037SARM gem5 Developers {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 7310037SARM gem5 Developers {MISCREG_HCR_EL2, {MISCREG_HCR, 0}}, 7410037SARM gem5 Developers {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 7510037SARM gem5 Developers {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 7610037SARM gem5 Developers {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 7710037SARM gem5 Developers {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}}, 7810037SARM gem5 Developers {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}}, 7910037SARM gem5 Developers {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 8010037SARM gem5 Developers {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 8110037SARM gem5 Developers {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}}, 8210037SARM gem5 Developers {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 8310037SARM gem5 Developers {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 8410037SARM gem5 Developers {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}}, 8510037SARM gem5 Developers {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}}, 8610037SARM gem5 Developers {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 8710037SARM gem5 Developers {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 8810037SARM gem5 Developers {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 8910037SARM gem5 Developers {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}}, 9010037SARM gem5 Developers {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 9110037SARM gem5 Developers {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 9210037SARM gem5 Developers {MISCREG_PAR_EL1, {MISCREG_PAR, 0}}, 9310037SARM gem5 Developers {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}}, 9410037SARM gem5 Developers {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 9510037SARM gem5 Developers {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}}, 9610037SARM gem5 Developers {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}}, 9710037SARM gem5 Developers {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 9810037SARM gem5 Developers {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}}, 9910037SARM gem5 Developers {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}}, 10010037SARM gem5 Developers {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}}, 10110037SARM gem5 Developers {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}}, 10210037SARM gem5 Developers {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 10310037SARM gem5 Developers {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}}, 10410037SARM gem5 Developers {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 10510037SARM gem5 Developers {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, 10610037SARM gem5 Developers {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, 10710037SARM gem5 Developers {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, 10810037SARM gem5 Developers {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 10910037SARM gem5 Developers {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 11010037SARM gem5 Developers {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}}, 11110037SARM gem5 Developers {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}}, 11210037SARM gem5 Developers {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}}, 11310037SARM gem5 Developers {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 11410037SARM gem5 Developers {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 11510037SARM gem5 Developers {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, 11610037SARM gem5 Developers {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 11710037SARM gem5 Developers {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 11810037SARM gem5 Developers {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, 11910037SARM gem5 Developers {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}}, 12010037SARM gem5 Developers {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}}, 12110037SARM gem5 Developers {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}}, 12210037SARM gem5 Developers {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}} 12310037SARM gem5 Developers}; 12410037SARM gem5 Developers 12510037SARM gem5 Developers 1269384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 12710461SAndreas.Sandberg@ARM.com : SimObject(p), 12810461SAndreas.Sandberg@ARM.com system(NULL), 12910461SAndreas.Sandberg@ARM.com pmu(p->pmu), 13010461SAndreas.Sandberg@ARM.com lookUpMiscReg(NUM_MISCREGS, {0,0}) 1319384SAndreas.Sandberg@arm.com{ 1329384SAndreas.Sandberg@arm.com SCTLR sctlr; 1339384SAndreas.Sandberg@arm.com sctlr = 0; 1349384SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr; 13510037SARM gem5 Developers 13610461SAndreas.Sandberg@ARM.com // Hook up a dummy device if we haven't been configured with a 13710461SAndreas.Sandberg@ARM.com // real PMU. By using a dummy device, we don't need to check that 13810461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 13910461SAndreas.Sandberg@ARM.com if (!pmu) 14010461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 14110461SAndreas.Sandberg@ARM.com 14210609Sandreas.sandberg@arm.com // Give all ISA devices a pointer to this ISA 14310609Sandreas.sandberg@arm.com pmu->setISA(this); 14410609Sandreas.sandberg@arm.com 14510037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 14610037SARM gem5 Developers DPRINTFN("ISA system set to: %p %p\n", system, p->system); 14710037SARM gem5 Developers 14810037SARM gem5 Developers // Cache system-level properties 14910037SARM gem5 Developers if (FullSystem && system) { 15010037SARM gem5 Developers haveSecurity = system->haveSecurity(); 15110037SARM gem5 Developers haveLPAE = system->haveLPAE(); 15210037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 15310037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 15410037SARM gem5 Developers physAddrRange64 = system->physAddrRange64(); 15510037SARM gem5 Developers } else { 15610037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 15710037SARM gem5 Developers haveLargeAsid64 = false; 15810037SARM gem5 Developers physAddrRange64 = 32; // dummy value 15910037SARM gem5 Developers } 16010037SARM gem5 Developers 16110037SARM gem5 Developers /** Fill in the miscReg translation table */ 16210037SARM gem5 Developers for (uint32_t i = 0; i < miscRegTranslateMax; i++) { 16310037SARM gem5 Developers struct MiscRegLUTEntry new_entry; 16410037SARM gem5 Developers 16510037SARM gem5 Developers uint32_t select = MiscRegSwitch[i].index; 16610037SARM gem5 Developers new_entry = MiscRegSwitch[i].entry; 16710037SARM gem5 Developers 16810037SARM gem5 Developers lookUpMiscReg[select] = new_entry; 16910037SARM gem5 Developers } 17010037SARM gem5 Developers 17110037SARM gem5 Developers preUnflattenMiscReg(); 17210037SARM gem5 Developers 1739384SAndreas.Sandberg@arm.com clear(); 1749384SAndreas.Sandberg@arm.com} 1759384SAndreas.Sandberg@arm.com 1769384SAndreas.Sandberg@arm.comconst ArmISAParams * 1779384SAndreas.Sandberg@arm.comISA::params() const 1789384SAndreas.Sandberg@arm.com{ 1799384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 1809384SAndreas.Sandberg@arm.com} 1819384SAndreas.Sandberg@arm.com 1827427Sgblack@eecs.umich.eduvoid 1837427Sgblack@eecs.umich.eduISA::clear() 1847427Sgblack@eecs.umich.edu{ 1859385SAndreas.Sandberg@arm.com const Params *p(params()); 1869385SAndreas.Sandberg@arm.com 1877427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1887427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 18910037SARM gem5 Developers 19010037SARM gem5 Developers // Initialize configurable default values 19110037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 19210037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 19310037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 19410037SARM gem5 Developers 19510037SARM gem5 Developers if (FullSystem && system->highestELIs64()) { 19610037SARM gem5 Developers // Initialize AArch64 state 19710037SARM gem5 Developers clear64(p); 19810037SARM gem5 Developers return; 19910037SARM gem5 Developers } 20010037SARM gem5 Developers 20110037SARM gem5 Developers // Initialize AArch32 state... 20210037SARM gem5 Developers 2037427Sgblack@eecs.umich.edu CPSR cpsr = 0; 2047427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 2057427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 2067427Sgblack@eecs.umich.edu updateRegMap(cpsr); 2077427Sgblack@eecs.umich.edu 2087427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 20910037SARM gem5 Developers sctlr.te = (bool) sctlr_rst.te; 21010037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 21110037SARM gem5 Developers sctlr.v = (bool) sctlr_rst.v; 21210037SARM gem5 Developers sctlr.u = 1; 2137427Sgblack@eecs.umich.edu sctlr.xp = 1; 2147427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 2157427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 21610037SARM gem5 Developers sctlr.rao4 = 0xf; // SCTLR[6:3] 21710204SAli.Saidi@ARM.com sctlr.uci = 1; 21810204SAli.Saidi@ARM.com sctlr.dze = 1; 21910037SARM gem5 Developers miscRegs[MISCREG_SCTLR_NS] = sctlr; 2207427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 22110037SARM gem5 Developers miscRegs[MISCREG_HCPTR] = 0; 2227427Sgblack@eecs.umich.edu 22310037SARM gem5 Developers // Start with an event in the mailbox 2247427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 2257427Sgblack@eecs.umich.edu 22610037SARM gem5 Developers // Separate Instruction and Data TLBs 2277427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 2287427Sgblack@eecs.umich.edu 2297427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 2307427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 2317427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 2327427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 2337427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 2347427Sgblack@eecs.umich.edu mvfr0.divide = 1; 2357427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 2367427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 2377427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 2387427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 2397427Sgblack@eecs.umich.edu 2407427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 2417427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 2427427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 2437427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 2447427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 2457427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 2467427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 2477427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 2487427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 2497427Sgblack@eecs.umich.edu 2507436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 2517436Sdam.sunwoo@arm.com 25210037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 25310037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 2547436Sdam.sunwoo@arm.com (1 << 19) | // 19 2557436Sdam.sunwoo@arm.com (0 << 18) | // 18 2567436Sdam.sunwoo@arm.com (0 << 17) | // 17 2577436Sdam.sunwoo@arm.com (1 << 16) | // 16 2587436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 2597436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 2607436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 2617436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 2627436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 2637436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 2647436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 2657436Sdam.sunwoo@arm.com 0; // 1:0 26610037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 2677436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 2687436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 2697436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 2707436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 2717436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 2727436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 2737436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 2747436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 2757436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 2767436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 2777436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 2787436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 2797436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 2807436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 2817436Sdam.sunwoo@arm.com 0; // 1:0 2827436Sdam.sunwoo@arm.com 2837644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 2848147SAli.Saidi@ARM.com 2859385SAndreas.Sandberg@arm.com 2869385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 2879385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 2889385SAndreas.Sandberg@arm.com 2899385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 2909385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 2919385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 2929385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 2939385SAndreas.Sandberg@arm.com 2949385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 2959385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 2969385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 2979385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 2989385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 2999385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 3009385SAndreas.Sandberg@arm.com 3019385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 3029385SAndreas.Sandberg@arm.com 30310037SARM gem5 Developers if (haveLPAE) { 30410037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 30510037SARM gem5 Developers ttbcr.eae = 0; 30610037SARM gem5 Developers miscRegs[MISCREG_TTBCR_NS] = ttbcr; 30710037SARM gem5 Developers // Enforce consistency with system-level settings 30810037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 30910037SARM gem5 Developers } 31010037SARM gem5 Developers 31110037SARM gem5 Developers if (haveSecurity) { 31210037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 31310037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 31410037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 31510037SARM gem5 Developers } else { 31610037SARM gem5 Developers // we're always non-secure 31710037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 31810037SARM gem5 Developers } 3198147SAli.Saidi@ARM.com 3207427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 3217427Sgblack@eecs.umich.edu} 3227427Sgblack@eecs.umich.edu 32310037SARM gem5 Developersvoid 32410037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 32510037SARM gem5 Developers{ 32610037SARM gem5 Developers CPSR cpsr = 0; 32710037SARM gem5 Developers Addr rvbar = system->resetAddr64(); 32810037SARM gem5 Developers switch (system->highestEL()) { 32910037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 33010037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 33110037SARM gem5 Developers // value 33210037SARM gem5 Developers case EL3: 33310037SARM gem5 Developers cpsr.mode = MODE_EL3H; 33410037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 33510037SARM gem5 Developers break; 33610037SARM gem5 Developers case EL2: 33710037SARM gem5 Developers cpsr.mode = MODE_EL2H; 33810037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 33910037SARM gem5 Developers break; 34010037SARM gem5 Developers case EL1: 34110037SARM gem5 Developers cpsr.mode = MODE_EL1H; 34210037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 34310037SARM gem5 Developers break; 34410037SARM gem5 Developers default: 34510037SARM gem5 Developers panic("Invalid highest implemented exception level"); 34610037SARM gem5 Developers break; 34710037SARM gem5 Developers } 34810037SARM gem5 Developers 34910037SARM gem5 Developers // Initialize rest of CPSR 35010037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 35110037SARM gem5 Developers cpsr.ss = 0; 35210037SARM gem5 Developers cpsr.il = 0; 35310037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 35410037SARM gem5 Developers updateRegMap(cpsr); 35510037SARM gem5 Developers 35610037SARM gem5 Developers // Initialize other control registers 35710037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 35810037SARM gem5 Developers if (haveSecurity) { 35910037SARM gem5 Developers miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 36010037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 36110037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 36210037SARM gem5 Developers // } else if (haveVirtualization) { 36310037SARM gem5 Developers // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 36410037SARM gem5 Developers } else { 36510037SARM gem5 Developers miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 36610037SARM gem5 Developers // Always non-secure 36710037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 36810037SARM gem5 Developers } 36910037SARM gem5 Developers 37010037SARM gem5 Developers // Initialize configurable id registers 37110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 37210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 37310461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 37410461SAndreas.Sandberg@ARM.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 37510461SAndreas.Sandberg@ARM.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 37610461SAndreas.Sandberg@ARM.com 37710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 37810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 37910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 38010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 38110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 38210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 38310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 38410037SARM gem5 Developers 38510461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0_EL1] = 38610461SAndreas.Sandberg@ARM.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 38710461SAndreas.Sandberg@ARM.com 38810461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 38910461SAndreas.Sandberg@ARM.com 39010037SARM gem5 Developers // Enforce consistency with system-level settings... 39110037SARM gem5 Developers 39210037SARM gem5 Developers // EL3 39310037SARM gem5 Developers // (no AArch32/64 interprocessing support for now) 39410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 39510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 39610037SARM gem5 Developers haveSecurity ? 0x1 : 0x0); 39710037SARM gem5 Developers // EL2 39810037SARM gem5 Developers // (no AArch32/64 interprocessing support for now) 39910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 40010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 40110037SARM gem5 Developers haveVirtualization ? 0x1 : 0x0); 40210037SARM gem5 Developers // Large ASID support 40310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 40410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 40510037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 40610037SARM gem5 Developers // Physical address size 40710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 40810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 40910037SARM gem5 Developers encodePhysAddrRange64(physAddrRange64)); 41010037SARM gem5 Developers} 41110037SARM gem5 Developers 4127405SAli.Saidi@ARM.comMiscReg 41310035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 4147405SAli.Saidi@ARM.com{ 4157405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 4167614Sminkyu.jeong@arm.com 41710037SARM gem5 Developers int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 41810037SARM gem5 Developers // registers are left unchanged 41910037SARM gem5 Developers MiscReg val; 4207614Sminkyu.jeong@arm.com 42110037SARM gem5 Developers if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 42210037SARM gem5 Developers || flat_idx == MISCREG_SCTLR_EL1) { 42310037SARM gem5 Developers if (flat_idx == MISCREG_SPSR) 42410037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_SPSR); 42510037SARM gem5 Developers if (flat_idx == MISCREG_SCTLR_EL1) 42610037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_SCTLR); 42710037SARM gem5 Developers val = miscRegs[flat_idx]; 42810037SARM gem5 Developers } else 42910037SARM gem5 Developers if (lookUpMiscReg[flat_idx].upper > 0) 43010037SARM gem5 Developers val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 43110037SARM gem5 Developers | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 43210037SARM gem5 Developers else 43310037SARM gem5 Developers val = miscRegs[lookUpMiscReg[flat_idx].lower]; 43410037SARM gem5 Developers 4357614Sminkyu.jeong@arm.com return val; 4367405SAli.Saidi@ARM.com} 4377405SAli.Saidi@ARM.com 4387405SAli.Saidi@ARM.com 4397405SAli.Saidi@ARM.comMiscReg 4407405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 4417405SAli.Saidi@ARM.com{ 44210037SARM gem5 Developers CPSR cpsr = 0; 44310037SARM gem5 Developers PCState pc = 0; 44410037SARM gem5 Developers SCR scr = 0; 4459050Schander.sudanthi@arm.com 4467405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 44710037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 44810037SARM gem5 Developers pc = tc->pcState(); 4497720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 4507720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 4517405SAli.Saidi@ARM.com return cpsr; 4527405SAli.Saidi@ARM.com } 4537757SAli.Saidi@ARM.com 45410037SARM gem5 Developers#ifndef NDEBUG 45510037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 45610037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 45710037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 45810037SARM gem5 Developers miscRegName[misc_reg]); 45910037SARM gem5 Developers else 46010037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 46110037SARM gem5 Developers miscRegName[misc_reg]); 46210037SARM gem5 Developers } 46310037SARM gem5 Developers#endif 46410037SARM gem5 Developers 46510037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 46610037SARM gem5 Developers case MISCREG_HCR: 46710037SARM gem5 Developers { 46810037SARM gem5 Developers if (!haveVirtualization) 46910037SARM gem5 Developers return 0; 47010037SARM gem5 Developers else 47110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 47210037SARM gem5 Developers } 47310037SARM gem5 Developers case MISCREG_CPACR: 47410037SARM gem5 Developers { 47510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 47610037SARM gem5 Developers CPACR cpacrMask = 0; 47710037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 47810037SARM gem5 Developers // be readable? (straight copy from the write code) 47910037SARM gem5 Developers cpacrMask.cp10 = ones; 48010037SARM gem5 Developers cpacrMask.cp11 = ones; 48110037SARM gem5 Developers cpacrMask.asedis = ones; 48210037SARM gem5 Developers 48310037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 48410037SARM gem5 Developers if (haveSecurity) { 48510037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 48610037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 48710037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 48810037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 48910037SARM gem5 Developers // NB: Skipping the full loop, here 49010037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 49110037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 49210037SARM gem5 Developers } 49310037SARM gem5 Developers } 49410037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 49510037SARM gem5 Developers val &= cpacrMask; 49610037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 49710037SARM gem5 Developers miscRegName[misc_reg], val); 49810037SARM gem5 Developers return val; 49910037SARM gem5 Developers } 5008284SAli.Saidi@ARM.com case MISCREG_MPIDR: 50110037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 50210037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 50310037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 50410037SARM gem5 Developers return getMPIDR(system, tc); 5059050Schander.sudanthi@arm.com } else { 50610037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 50710037SARM gem5 Developers } 50810037SARM gem5 Developers break; 50910037SARM gem5 Developers case MISCREG_MPIDR_EL1: 51010037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 51110037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 51210037SARM gem5 Developers case MISCREG_VMPIDR: 51310037SARM gem5 Developers // top bit defined as RES1 51410037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 51510037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 51610037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 51710037SARM gem5 Developers case MISCREG_MIDR: 51810037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 51910037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 52010037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 52110037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 52210037SARM gem5 Developers } else { 52310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 5249050Schander.sudanthi@arm.com } 5258284SAli.Saidi@ARM.com break; 52610037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 52710037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 52810037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 52910037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 53010037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 53110037SARM gem5 Developers return 0; 53210037SARM gem5 Developers 5337405SAli.Saidi@ARM.com case MISCREG_CLIDR: 5347731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 5358468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 5368468Swade.walker@arm.com "ARM implementations.\n"); 5378468Swade.walker@arm.com return 0x00200000; 5387405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 5397731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 5407405SAli.Saidi@ARM.com "always reads as 0.\n"); 5417405SAli.Saidi@ARM.com break; 5427583SAli.Saidi@arm.com case MISCREG_CTR: 5439130Satgutier@umich.edu { 5449130Satgutier@umich.edu //all caches have the same line size in gem5 5459130Satgutier@umich.edu //4 byte words in ARM 5469130Satgutier@umich.edu unsigned lineSizeWords = 5479814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 5489130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 5499130Satgutier@umich.edu 5509130Satgutier@umich.edu while (lineSizeWords >>= 1) { 5519130Satgutier@umich.edu ++log2LineSizeWords; 5529130Satgutier@umich.edu } 5539130Satgutier@umich.edu 5549130Satgutier@umich.edu CTR ctr = 0; 5559130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 5569130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 5579130Satgutier@umich.edu //b11 - gem5 uses pipt 5589130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 5599130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 5609130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 5619130Satgutier@umich.edu //log2 of max reservation size (words) 5629130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 5639130Satgutier@umich.edu //log2 of max writeback size (words) 5649130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 5659130Satgutier@umich.edu //b100 - gem5 format is ARMv7 5669130Satgutier@umich.edu ctr.format = 0x4; 5679130Satgutier@umich.edu 5689130Satgutier@umich.edu return ctr; 5699130Satgutier@umich.edu } 5707583SAli.Saidi@arm.com case MISCREG_ACTLR: 5717583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 5727583SAli.Saidi@arm.com break; 57310461SAndreas.Sandberg@ARM.com 57410461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 57510461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 57610461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 57710461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 57810461SAndreas.Sandberg@ARM.com return pmu->readMiscReg(misc_reg); 57910461SAndreas.Sandberg@ARM.com 5808302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 5818302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 5827783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 5837783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5847783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 5857783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 58610037SARM gem5 Developers case MISCREG_FPSR: 58710037SARM gem5 Developers { 58810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 58910037SARM gem5 Developers FPSCR fpscrMask = 0; 59010037SARM gem5 Developers fpscrMask.ioc = ones; 59110037SARM gem5 Developers fpscrMask.dzc = ones; 59210037SARM gem5 Developers fpscrMask.ofc = ones; 59310037SARM gem5 Developers fpscrMask.ufc = ones; 59410037SARM gem5 Developers fpscrMask.ixc = ones; 59510037SARM gem5 Developers fpscrMask.idc = ones; 59610037SARM gem5 Developers fpscrMask.qc = ones; 59710037SARM gem5 Developers fpscrMask.v = ones; 59810037SARM gem5 Developers fpscrMask.c = ones; 59910037SARM gem5 Developers fpscrMask.z = ones; 60010037SARM gem5 Developers fpscrMask.n = ones; 60110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 60210037SARM gem5 Developers } 60310037SARM gem5 Developers case MISCREG_FPCR: 60410037SARM gem5 Developers { 60510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 60610037SARM gem5 Developers FPSCR fpscrMask = 0; 60710037SARM gem5 Developers fpscrMask.ioe = ones; 60810037SARM gem5 Developers fpscrMask.dze = ones; 60910037SARM gem5 Developers fpscrMask.ofe = ones; 61010037SARM gem5 Developers fpscrMask.ufe = ones; 61110037SARM gem5 Developers fpscrMask.ixe = ones; 61210037SARM gem5 Developers fpscrMask.ide = ones; 61310037SARM gem5 Developers fpscrMask.len = ones; 61410037SARM gem5 Developers fpscrMask.stride = ones; 61510037SARM gem5 Developers fpscrMask.rMode = ones; 61610037SARM gem5 Developers fpscrMask.fz = ones; 61710037SARM gem5 Developers fpscrMask.dn = ones; 61810037SARM gem5 Developers fpscrMask.ahp = ones; 61910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 62010037SARM gem5 Developers } 62110037SARM gem5 Developers case MISCREG_NZCV: 62210037SARM gem5 Developers { 62310037SARM gem5 Developers CPSR cpsr = 0; 62410338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 62510338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 62610338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 62710037SARM gem5 Developers return cpsr; 62810037SARM gem5 Developers } 62910037SARM gem5 Developers case MISCREG_DAIF: 63010037SARM gem5 Developers { 63110037SARM gem5 Developers CPSR cpsr = 0; 63210037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 63310037SARM gem5 Developers return cpsr; 63410037SARM gem5 Developers } 63510037SARM gem5 Developers case MISCREG_SP_EL0: 63610037SARM gem5 Developers { 63710037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 63810037SARM gem5 Developers } 63910037SARM gem5 Developers case MISCREG_SP_EL1: 64010037SARM gem5 Developers { 64110037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 64210037SARM gem5 Developers } 64310037SARM gem5 Developers case MISCREG_SP_EL2: 64410037SARM gem5 Developers { 64510037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 64610037SARM gem5 Developers } 64710037SARM gem5 Developers case MISCREG_SPSEL: 64810037SARM gem5 Developers { 64910037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 65010037SARM gem5 Developers } 65110037SARM gem5 Developers case MISCREG_CURRENTEL: 65210037SARM gem5 Developers { 65310037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 65410037SARM gem5 Developers } 6558549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 6568868SMatt.Horsnell@arm.com { 6578868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 6588868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 6598868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 6608868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 6618868SMatt.Horsnell@arm.com return l2ctlr; 6628868SMatt.Horsnell@arm.com } 6638868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 6648868SMatt.Horsnell@arm.com /* For now just implement the version number. 66510461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 6668868SMatt.Horsnell@arm.com */ 66710461SAndreas.Sandberg@ARM.com return 0x5 << 16; 66810037SARM gem5 Developers case MISCREG_DBGDSCRint: 6698868SMatt.Horsnell@arm.com return 0; 67010037SARM gem5 Developers case MISCREG_ISR: 67110037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController()->getISR( 67210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 67310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 67410037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 67510037SARM gem5 Developers case MISCREG_ISR_EL1: 67610037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController()->getISR( 67710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 67810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 67910037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 68010037SARM gem5 Developers case MISCREG_DCZID_EL0: 68110037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 68210037SARM gem5 Developers case MISCREG_HCPTR: 68310037SARM gem5 Developers { 68410037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 68510037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 68610037SARM gem5 Developers val &= ~(1 << 14); 68710037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 68810037SARM gem5 Developers // HCPTR is RAO/WI 68910037SARM gem5 Developers bool secure_lookup = haveSecurity && 69010037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 69110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 69210037SARM gem5 Developers if (!secure_lookup) { 69310037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 69410037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 69510037SARM gem5 Developers } 69610037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 69710037SARM gem5 Developers val |= 0x33FF; 69810037SARM gem5 Developers return (val); 69910037SARM gem5 Developers } 70010037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 70110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 70210037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 70310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 70410037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 70510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 70610037SARM gem5 Developers case MISCREG_SCTLR: // Some bits hardwired 70710037SARM gem5 Developers // The FI field (bit 21) is common between S/NS versions of the register 70810037SARM gem5 Developers return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 70910037SARM gem5 Developers (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 71010037SARM gem5 Developers case MISCREG_SCTLR_EL1: 71110037SARM gem5 Developers // The FI field (bit 21) is common between S/NS versions of the register 71210037SARM gem5 Developers return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 71310037SARM gem5 Developers (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 71410037SARM gem5 Developers case MISCREG_SCTLR_EL3: 71510037SARM gem5 Developers // The FI field (bit 21) is common between S/NS versions of the register 71610037SARM gem5 Developers return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 71710037SARM gem5 Developers (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 71810037SARM gem5 Developers case MISCREG_HSCTLR: // FI comes from SCTLR 71910037SARM gem5 Developers { 72010037SARM gem5 Developers uint32_t mask = 1 << 27; 72110037SARM gem5 Developers return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 72210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 72310037SARM gem5 Developers } 72410037SARM gem5 Developers case MISCREG_SCR: 72510037SARM gem5 Developers { 72610037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 72710037SARM gem5 Developers if (cpsr.width) { 72810037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_SCR); 72910037SARM gem5 Developers } else { 73010037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_SCR_EL3); 73110037SARM gem5 Developers } 73210037SARM gem5 Developers } 73310037SARM gem5 Developers // Generic Timer registers 73410037SARM gem5 Developers case MISCREG_CNTFRQ: 73510037SARM gem5 Developers case MISCREG_CNTFRQ_EL0: 73610037SARM gem5 Developers inform_once("Read CNTFREQ_EL0 frequency\n"); 73710037SARM gem5 Developers return getSystemCounter(tc)->freq(); 73810037SARM gem5 Developers case MISCREG_CNTPCT: 73910037SARM gem5 Developers case MISCREG_CNTPCT_EL0: 74010037SARM gem5 Developers return getSystemCounter(tc)->value(); 74110037SARM gem5 Developers case MISCREG_CNTVCT: 74210037SARM gem5 Developers return getSystemCounter(tc)->value(); 74310037SARM gem5 Developers case MISCREG_CNTVCT_EL0: 74410037SARM gem5 Developers return getSystemCounter(tc)->value(); 74510037SARM gem5 Developers case MISCREG_CNTP_CVAL: 74610037SARM gem5 Developers case MISCREG_CNTP_CVAL_EL0: 74710037SARM gem5 Developers return getArchTimer(tc, tc->cpuId())->compareValue(); 74810037SARM gem5 Developers case MISCREG_CNTP_TVAL: 74910037SARM gem5 Developers case MISCREG_CNTP_TVAL_EL0: 75010037SARM gem5 Developers return getArchTimer(tc, tc->cpuId())->timerValue(); 75110037SARM gem5 Developers case MISCREG_CNTP_CTL: 75210037SARM gem5 Developers case MISCREG_CNTP_CTL_EL0: 75310037SARM gem5 Developers return getArchTimer(tc, tc->cpuId())->control(); 75410037SARM gem5 Developers // PL1 phys. timer, secure 75510037SARM gem5 Developers // AArch64 75610188Sgeoffrey.blake@arm.com // case MISCREG_CNTPS_CVAL_EL1: 75710188Sgeoffrey.blake@arm.com // case MISCREG_CNTPS_TVAL_EL1: 75810188Sgeoffrey.blake@arm.com // case MISCREG_CNTPS_CTL_EL1: 75910037SARM gem5 Developers // PL2 phys. timer, non-secure 76010037SARM gem5 Developers // AArch32 76110188Sgeoffrey.blake@arm.com // case MISCREG_CNTHCTL: 76210188Sgeoffrey.blake@arm.com // case MISCREG_CNTHP_CVAL: 76310188Sgeoffrey.blake@arm.com // case MISCREG_CNTHP_TVAL: 76410188Sgeoffrey.blake@arm.com // case MISCREG_CNTHP_CTL: 76510037SARM gem5 Developers // AArch64 76610188Sgeoffrey.blake@arm.com // case MISCREG_CNTHCTL_EL2: 76710188Sgeoffrey.blake@arm.com // case MISCREG_CNTHP_CVAL_EL2: 76810188Sgeoffrey.blake@arm.com // case MISCREG_CNTHP_TVAL_EL2: 76910188Sgeoffrey.blake@arm.com // case MISCREG_CNTHP_CTL_EL2: 77010037SARM gem5 Developers // Virtual timer 77110037SARM gem5 Developers // AArch32 77210188Sgeoffrey.blake@arm.com // case MISCREG_CNTV_CVAL: 77310188Sgeoffrey.blake@arm.com // case MISCREG_CNTV_TVAL: 77410188Sgeoffrey.blake@arm.com // case MISCREG_CNTV_CTL: 77510037SARM gem5 Developers // AArch64 77610037SARM gem5 Developers // case MISCREG_CNTV_CVAL_EL2: 77710037SARM gem5 Developers // case MISCREG_CNTV_TVAL_EL2: 77810037SARM gem5 Developers // case MISCREG_CNTV_CTL_EL2: 77910188Sgeoffrey.blake@arm.com default: 78010037SARM gem5 Developers break; 78110037SARM gem5 Developers 7827405SAli.Saidi@ARM.com } 7837405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 7847405SAli.Saidi@ARM.com} 7857405SAli.Saidi@ARM.com 7867405SAli.Saidi@ARM.comvoid 7877405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 7887405SAli.Saidi@ARM.com{ 7897405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 7907614Sminkyu.jeong@arm.com 79110037SARM gem5 Developers int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 79210037SARM gem5 Developers // registers are left unchanged 7937614Sminkyu.jeong@arm.com 79410037SARM gem5 Developers int flat_idx2 = lookUpMiscReg[flat_idx].upper; 79510037SARM gem5 Developers 79610037SARM gem5 Developers if (flat_idx2 > 0) { 79710037SARM gem5 Developers miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 79810037SARM gem5 Developers miscRegs[flat_idx2] = bits(val, 63, 32); 79910037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 80010037SARM gem5 Developers misc_reg, flat_idx, flat_idx2, val); 80110037SARM gem5 Developers } else { 80210037SARM gem5 Developers if (flat_idx == MISCREG_SPSR) 80310037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_SPSR); 80410037SARM gem5 Developers else if (flat_idx == MISCREG_SCTLR_EL1) 80510037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_SCTLR); 80610037SARM gem5 Developers else 80710037SARM gem5 Developers flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 80810037SARM gem5 Developers lookUpMiscReg[flat_idx].lower : flat_idx; 80910037SARM gem5 Developers miscRegs[flat_idx] = val; 81010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 81110037SARM gem5 Developers misc_reg, flat_idx, val); 81210037SARM gem5 Developers } 8137405SAli.Saidi@ARM.com} 8147405SAli.Saidi@ARM.com 8157405SAli.Saidi@ARM.comvoid 8167405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 8177405SAli.Saidi@ARM.com{ 8187749SAli.Saidi@ARM.com 8197405SAli.Saidi@ARM.com MiscReg newVal = val; 8208284SAli.Saidi@ARM.com int x; 82110037SARM gem5 Developers bool secure_lookup; 82210037SARM gem5 Developers bool hyp; 8238284SAli.Saidi@ARM.com System *sys; 8248284SAli.Saidi@ARM.com ThreadContext *oc; 82510037SARM gem5 Developers uint8_t target_el; 82610037SARM gem5 Developers uint16_t asid; 82710037SARM gem5 Developers SCR scr; 8288284SAli.Saidi@ARM.com 8297405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 8307405SAli.Saidi@ARM.com updateRegMap(val); 8317749SAli.Saidi@ARM.com 8327749SAli.Saidi@ARM.com 8337749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 8347749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 8357405SAli.Saidi@ARM.com CPSR cpsr = val; 8367749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 8377749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 8387749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 8397749SAli.Saidi@ARM.com } 8407749SAli.Saidi@ARM.com 8417614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 8427614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 8437720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 8447720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 8457720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 8468887Sgeoffrey.blake@arm.com 8478887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 8488887Sgeoffrey.blake@arm.com // is connected 8498887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 8508887Sgeoffrey.blake@arm.com if (checker) { 8518887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 8528887Sgeoffrey.blake@arm.com } else { 8538887Sgeoffrey.blake@arm.com tc->pcState(pc); 8548887Sgeoffrey.blake@arm.com } 8557408Sgblack@eecs.umich.edu } else { 85610037SARM gem5 Developers#ifndef NDEBUG 85710037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 85810037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 85910037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 86010037SARM gem5 Developers miscRegName[misc_reg], val); 86110037SARM gem5 Developers else 86210037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 86310037SARM gem5 Developers miscRegName[misc_reg], val); 86410037SARM gem5 Developers } 86510037SARM gem5 Developers#endif 86610037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 8677408Sgblack@eecs.umich.edu case MISCREG_CPACR: 8687408Sgblack@eecs.umich.edu { 8698206SWilliam.Wang@arm.com 8708206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 8718206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 8728206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 8738206SWilliam.Wang@arm.com // be writable 8748206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 8758206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 8768206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 87710037SARM gem5 Developers 87810037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 87910037SARM gem5 Developers if (haveSecurity) { 88010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 88110037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 88210037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 88310037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 88410037SARM gem5 Developers // NB: Skipping the full loop, here 88510037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 88610037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 88710037SARM gem5 Developers } 88810037SARM gem5 Developers } 88910037SARM gem5 Developers 89010037SARM gem5 Developers MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 8918206SWilliam.Wang@arm.com newVal &= cpacrMask; 89210037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 89310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 89410037SARM gem5 Developers miscRegName[misc_reg], newVal); 89510037SARM gem5 Developers } 89610037SARM gem5 Developers break; 89710037SARM gem5 Developers case MISCREG_CPACR_EL1: 89810037SARM gem5 Developers { 89910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 90010037SARM gem5 Developers CPACR cpacrMask = 0; 90110037SARM gem5 Developers cpacrMask.tta = ones; 90210037SARM gem5 Developers cpacrMask.fpen = ones; 90310037SARM gem5 Developers newVal &= cpacrMask; 90410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 90510037SARM gem5 Developers miscRegName[misc_reg], newVal); 90610037SARM gem5 Developers } 90710037SARM gem5 Developers break; 90810037SARM gem5 Developers case MISCREG_CPTR_EL2: 90910037SARM gem5 Developers { 91010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 91110037SARM gem5 Developers CPTR cptrMask = 0; 91210037SARM gem5 Developers cptrMask.tcpac = ones; 91310037SARM gem5 Developers cptrMask.tta = ones; 91410037SARM gem5 Developers cptrMask.tfp = ones; 91510037SARM gem5 Developers newVal &= cptrMask; 91610037SARM gem5 Developers cptrMask = 0; 91710037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 91810037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 91910037SARM gem5 Developers newVal |= cptrMask; 92010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 92110037SARM gem5 Developers miscRegName[misc_reg], newVal); 92210037SARM gem5 Developers } 92310037SARM gem5 Developers break; 92410037SARM gem5 Developers case MISCREG_CPTR_EL3: 92510037SARM gem5 Developers { 92610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 92710037SARM gem5 Developers CPTR cptrMask = 0; 92810037SARM gem5 Developers cptrMask.tcpac = ones; 92910037SARM gem5 Developers cptrMask.tta = ones; 93010037SARM gem5 Developers cptrMask.tfp = ones; 93110037SARM gem5 Developers newVal &= cptrMask; 9328206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 9338206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 9347408Sgblack@eecs.umich.edu } 9357408Sgblack@eecs.umich.edu break; 9367408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 9377731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 9388206SWilliam.Wang@arm.com return; 93910037SARM gem5 Developers 94010037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 94110037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 94210037SARM gem5 Developers return; 94310037SARM gem5 Developers 9447408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 9457408Sgblack@eecs.umich.edu { 9467408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 9477408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 9487408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 9497408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 9507408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 9517408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 9527408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 9537408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 95410037SARM gem5 Developers fpscrMask.ioe = ones; 95510037SARM gem5 Developers fpscrMask.dze = ones; 95610037SARM gem5 Developers fpscrMask.ofe = ones; 95710037SARM gem5 Developers fpscrMask.ufe = ones; 95810037SARM gem5 Developers fpscrMask.ixe = ones; 95910037SARM gem5 Developers fpscrMask.ide = ones; 9607408Sgblack@eecs.umich.edu fpscrMask.len = ones; 9617408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 9627408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 9637408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 9647408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 9657408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 9667408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 9677408Sgblack@eecs.umich.edu fpscrMask.v = ones; 9687408Sgblack@eecs.umich.edu fpscrMask.c = ones; 9697408Sgblack@eecs.umich.edu fpscrMask.z = ones; 9707408Sgblack@eecs.umich.edu fpscrMask.n = ones; 9717408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 97210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 97310037SARM gem5 Developers ~(uint32_t)fpscrMask); 9749377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 9757408Sgblack@eecs.umich.edu } 9767408Sgblack@eecs.umich.edu break; 97710037SARM gem5 Developers case MISCREG_FPSR: 97810037SARM gem5 Developers { 97910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 98010037SARM gem5 Developers FPSCR fpscrMask = 0; 98110037SARM gem5 Developers fpscrMask.ioc = ones; 98210037SARM gem5 Developers fpscrMask.dzc = ones; 98310037SARM gem5 Developers fpscrMask.ofc = ones; 98410037SARM gem5 Developers fpscrMask.ufc = ones; 98510037SARM gem5 Developers fpscrMask.ixc = ones; 98610037SARM gem5 Developers fpscrMask.idc = ones; 98710037SARM gem5 Developers fpscrMask.qc = ones; 98810037SARM gem5 Developers fpscrMask.v = ones; 98910037SARM gem5 Developers fpscrMask.c = ones; 99010037SARM gem5 Developers fpscrMask.z = ones; 99110037SARM gem5 Developers fpscrMask.n = ones; 99210037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 99310037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 99410037SARM gem5 Developers ~(uint32_t)fpscrMask); 99510037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 99610037SARM gem5 Developers } 99710037SARM gem5 Developers break; 99810037SARM gem5 Developers case MISCREG_FPCR: 99910037SARM gem5 Developers { 100010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 100110037SARM gem5 Developers FPSCR fpscrMask = 0; 100210037SARM gem5 Developers fpscrMask.ioe = ones; 100310037SARM gem5 Developers fpscrMask.dze = ones; 100410037SARM gem5 Developers fpscrMask.ofe = ones; 100510037SARM gem5 Developers fpscrMask.ufe = ones; 100610037SARM gem5 Developers fpscrMask.ixe = ones; 100710037SARM gem5 Developers fpscrMask.ide = ones; 100810037SARM gem5 Developers fpscrMask.len = ones; 100910037SARM gem5 Developers fpscrMask.stride = ones; 101010037SARM gem5 Developers fpscrMask.rMode = ones; 101110037SARM gem5 Developers fpscrMask.fz = ones; 101210037SARM gem5 Developers fpscrMask.dn = ones; 101310037SARM gem5 Developers fpscrMask.ahp = ones; 101410037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 101510037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 101610037SARM gem5 Developers ~(uint32_t)fpscrMask); 101710037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 101810037SARM gem5 Developers } 101910037SARM gem5 Developers break; 10208302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 10218302SAli.Saidi@ARM.com { 10228302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 102310037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 10248302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 10258302SAli.Saidi@ARM.com } 10268302SAli.Saidi@ARM.com break; 10277783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 10287783SGiacomo.Gabrielli@arm.com { 102910037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 103010037SARM gem5 Developers (newVal & FpscrQcMask); 10317783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 10327783SGiacomo.Gabrielli@arm.com } 10337783SGiacomo.Gabrielli@arm.com break; 10347783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 10357783SGiacomo.Gabrielli@arm.com { 103610037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 103710037SARM gem5 Developers (newVal & FpscrExcMask); 10387783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 10397783SGiacomo.Gabrielli@arm.com } 10407783SGiacomo.Gabrielli@arm.com break; 10417408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 10427408Sgblack@eecs.umich.edu { 10438206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 10448206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 10457408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 10467408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 104710037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 10487408Sgblack@eecs.umich.edu } 10497408Sgblack@eecs.umich.edu break; 105010037SARM gem5 Developers case MISCREG_HCR: 105110037SARM gem5 Developers { 105210037SARM gem5 Developers if (!haveVirtualization) 105310037SARM gem5 Developers return; 105410037SARM gem5 Developers } 105510037SARM gem5 Developers break; 105610037SARM gem5 Developers case MISCREG_IFSR: 105710037SARM gem5 Developers { 105810037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 105910037SARM gem5 Developers const uint32_t ifsrMask = 106010037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 106110037SARM gem5 Developers newVal = newVal & ~ifsrMask; 106210037SARM gem5 Developers } 106310037SARM gem5 Developers break; 106410037SARM gem5 Developers case MISCREG_DFSR: 106510037SARM gem5 Developers { 106610037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 106710037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 106810037SARM gem5 Developers newVal = newVal & ~dfsrMask; 106910037SARM gem5 Developers } 107010037SARM gem5 Developers break; 107110037SARM gem5 Developers case MISCREG_AMAIR0: 107210037SARM gem5 Developers case MISCREG_AMAIR1: 107310037SARM gem5 Developers { 107410037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 107510037SARM gem5 Developers // Valid only with LPAE 107610037SARM gem5 Developers if (!haveLPAE) 107710037SARM gem5 Developers return; 107810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 107910037SARM gem5 Developers } 108010037SARM gem5 Developers break; 108110037SARM gem5 Developers case MISCREG_SCR: 108210037SARM gem5 Developers tc->getITBPtr()->invalidateMiscReg(); 108310037SARM gem5 Developers tc->getDTBPtr()->invalidateMiscReg(); 108410037SARM gem5 Developers break; 10857408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 10867408Sgblack@eecs.umich.edu { 10877408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 108810037SARM gem5 Developers MiscRegIndex sctlr_idx; 108910037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 109010037SARM gem5 Developers if (haveSecurity && !scr.ns) { 109110037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_S; 109210037SARM gem5 Developers } else { 109310037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_NS; 109410037SARM gem5 Developers // The FI field (bit 21) is common between S/NS versions 109510037SARM gem5 Developers // of the register, we store this in the secure copy of 109610037SARM gem5 Developers // the reg 109710037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 109810037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 109910037SARM gem5 Developers } 110010037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 11017408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 110210037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 110310037SARM gem5 Developers miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 11047749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 11057749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 11068527SAli.Saidi@ARM.com 110710508SAli.Saidi@ARM.com if (new_sctlr.c) 110810508SAli.Saidi@ARM.com updateBootUncacheable(sctlr_idx, tc); 11097408Sgblack@eecs.umich.edu return; 11107408Sgblack@eecs.umich.edu } 11119385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 11129385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 11139385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 111410461SAndreas.Sandberg@ARM.com case MISCREG_ID_DFR0: 11159385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 11169385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 11179385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 11189385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 11199385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 11209385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 11219385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 11229385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 11239385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 11249385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 11259385SAndreas.Sandberg@arm.com 11269385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 11279385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 11287408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 11297408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 11307408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 113110037SARM gem5 Developers 113210037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 113310037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 113410037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 113510037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 113610037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 113710037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 113810037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 113910037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 114010037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 114110037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 11429385SAndreas.Sandberg@arm.com // ID registers are constants. 11437408Sgblack@eecs.umich.edu return; 11449385SAndreas.Sandberg@arm.com 114510037SARM gem5 Developers // TLBI all entries, EL0&1 inner sharable (ignored) 11467408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 114710037SARM gem5 Developers case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 114810037SARM gem5 Developers assert32(tc); 114910037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 115010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 115110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 11528284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 11538284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 11548284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 11558284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 115610037SARM gem5 Developers oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 115710037SARM gem5 Developers oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 11588887Sgeoffrey.blake@arm.com 11598887Sgeoffrey.blake@arm.com // If CheckerCPU is connected, need to notify it of a flush 11608887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 11618733Sgeoffrey.blake@arm.com if (checker) { 116210037SARM gem5 Developers checker->getITBPtr()->flushAllSecurity(secure_lookup, 116310037SARM gem5 Developers target_el); 116410037SARM gem5 Developers checker->getDTBPtr()->flushAllSecurity(secure_lookup, 116510037SARM gem5 Developers target_el); 11668733Sgeoffrey.blake@arm.com } 11678284SAli.Saidi@ARM.com } 11687408Sgblack@eecs.umich.edu return; 116910037SARM gem5 Developers // TLBI all entries, EL0&1, instruction side 11707408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 117110037SARM gem5 Developers assert32(tc); 117210037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 117310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 117410037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 117510037SARM gem5 Developers tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 11767408Sgblack@eecs.umich.edu return; 117710037SARM gem5 Developers // TLBI all entries, EL0&1, data side 11787408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 117910037SARM gem5 Developers assert32(tc); 118010037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 118110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 118210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 118310037SARM gem5 Developers tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 11847408Sgblack@eecs.umich.edu return; 118510037SARM gem5 Developers // TLBI based on VA, EL0&1 inner sharable (ignored) 11867408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 11877408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 118810037SARM gem5 Developers assert32(tc); 118910037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 119010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 119110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 11928284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 11938284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 11948284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 11958284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 11968284SAli.Saidi@ARM.com oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 119710037SARM gem5 Developers bits(newVal, 7,0), 119810037SARM gem5 Developers secure_lookup, target_el); 11998284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 120010037SARM gem5 Developers bits(newVal, 7,0), 120110037SARM gem5 Developers secure_lookup, target_el); 12028887Sgeoffrey.blake@arm.com 12038887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 12048733Sgeoffrey.blake@arm.com if (checker) { 12058733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 120610037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 12078733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 120810037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 12098733Sgeoffrey.blake@arm.com } 12108284SAli.Saidi@ARM.com } 12117408Sgblack@eecs.umich.edu return; 121210037SARM gem5 Developers // TLBI by ASID, EL0&1, inner sharable 12137408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 12147408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 121510037SARM gem5 Developers assert32(tc); 121610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 121710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 121810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 12198284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 12208284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 12218284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 12228284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 122310037SARM gem5 Developers oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 122410037SARM gem5 Developers secure_lookup, target_el); 122510037SARM gem5 Developers oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 122610037SARM gem5 Developers secure_lookup, target_el); 12278887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 12288733Sgeoffrey.blake@arm.com if (checker) { 122910037SARM gem5 Developers checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 123010037SARM gem5 Developers secure_lookup, target_el); 123110037SARM gem5 Developers checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 123210037SARM gem5 Developers secure_lookup, target_el); 12338733Sgeoffrey.blake@arm.com } 12348284SAli.Saidi@ARM.com } 12357408Sgblack@eecs.umich.edu return; 123610037SARM gem5 Developers // TLBI by address, EL0&1, inner sharable (ignored) 12377408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 12387408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 123910037SARM gem5 Developers assert32(tc); 124010037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 124110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 124210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 124310037SARM gem5 Developers hyp = 0; 124410037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 124510037SARM gem5 Developers return; 124610037SARM gem5 Developers // TLBI by address, EL2, hypervisor mode 124710037SARM gem5 Developers case MISCREG_TLBIMVAH: 124810037SARM gem5 Developers case MISCREG_TLBIMVAHIS: 124910037SARM gem5 Developers assert32(tc); 125010037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 125110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 125210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 125310037SARM gem5 Developers hyp = 1; 125410037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 125510037SARM gem5 Developers return; 125610037SARM gem5 Developers // TLBI by address and asid, EL0&1, instruction side only 125710037SARM gem5 Developers case MISCREG_ITLBIMVA: 125810037SARM gem5 Developers assert32(tc); 125910037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 126010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 126110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 126210037SARM gem5 Developers tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 126310037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 126410037SARM gem5 Developers return; 126510037SARM gem5 Developers // TLBI by address and asid, EL0&1, data side only 126610037SARM gem5 Developers case MISCREG_DTLBIMVA: 126710037SARM gem5 Developers assert32(tc); 126810037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 126910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127010037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 127110037SARM gem5 Developers tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 127210037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 127310037SARM gem5 Developers return; 127410037SARM gem5 Developers // TLBI by ASID, EL0&1, instrution side only 127510037SARM gem5 Developers case MISCREG_ITLBIASID: 127610037SARM gem5 Developers assert32(tc); 127710037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 127810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127910037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 128010037SARM gem5 Developers tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 128110037SARM gem5 Developers target_el); 128210037SARM gem5 Developers return; 128310037SARM gem5 Developers // TLBI by ASID EL0&1 data size only 128410037SARM gem5 Developers case MISCREG_DTLBIASID: 128510037SARM gem5 Developers assert32(tc); 128610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 128710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 128810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 128910037SARM gem5 Developers tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 129010037SARM gem5 Developers target_el); 129110037SARM gem5 Developers return; 129210037SARM gem5 Developers // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 129310037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 129410037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 129510037SARM gem5 Developers assert32(tc); 129610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 129710037SARM gem5 Developers hyp = 0; 129810037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 129910037SARM gem5 Developers return; 130010037SARM gem5 Developers // TLBI all entries, EL2, hyp, 130110037SARM gem5 Developers case MISCREG_TLBIALLH: 130210037SARM gem5 Developers case MISCREG_TLBIALLHIS: 130310037SARM gem5 Developers assert32(tc); 130410037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 130510037SARM gem5 Developers hyp = 1; 130610037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 130710037SARM gem5 Developers return; 130810037SARM gem5 Developers // AArch64 TLBI: invalidate all entries EL3 130910037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 131010037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 131110037SARM gem5 Developers assert64(tc); 131210037SARM gem5 Developers target_el = 3; 131310037SARM gem5 Developers secure_lookup = true; 131410037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 131510037SARM gem5 Developers return; 131610037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 131710037SARM gem5 Developers // case MISCREG_TLBI_ALLE2IS: 131810037SARM gem5 Developers // case MISCREG_TLBI_ALLE2: 131910037SARM gem5 Developers // TLBI all entries, EL0&1 132010037SARM gem5 Developers case MISCREG_TLBI_ALLE1IS: 132110037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 132210037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stage 1, current VMID 132310037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 132410037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 132510037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 132610037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 132710037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 132810037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 132910037SARM gem5 Developers assert64(tc); 133010037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 133110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 133210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 133310037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 133410037SARM gem5 Developers return; 133510037SARM gem5 Developers // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 133610037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 133710037SARM gem5 Developers // from the last level of translation table walks 133810037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 133910037SARM gem5 Developers // TLBI all entries, EL0&1 134010037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 134110037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 134210037SARM gem5 Developers // TLBI by VA, EL3 regime stage 1, last level walk 134310037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 134410037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 134510037SARM gem5 Developers assert64(tc); 134610037SARM gem5 Developers target_el = 3; 134710037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 134810037SARM gem5 Developers secure_lookup = true; 134910037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 135010037SARM gem5 Developers return; 135110037SARM gem5 Developers // TLBI by VA, EL2 135210037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 135310037SARM gem5 Developers case MISCREG_TLBI_VAE2_Xt: 135410037SARM gem5 Developers // TLBI by VA, EL2, stage1 last level walk 135510037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 135610037SARM gem5 Developers case MISCREG_TLBI_VALE2_Xt: 135710037SARM gem5 Developers assert64(tc); 135810037SARM gem5 Developers target_el = 2; 135910037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 136010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 136110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 136210037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 136310037SARM gem5 Developers return; 136410037SARM gem5 Developers // TLBI by VA EL1 & 0, stage1, ASID, current VMID 136510037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 136610037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 136710037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 136810037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 136910037SARM gem5 Developers assert64(tc); 137010037SARM gem5 Developers asid = bits(newVal, 63, 48); 137110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 137210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 137310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 137410037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 137510037SARM gem5 Developers return; 137610037SARM gem5 Developers // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 137710037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 137810037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 137910037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 138010037SARM gem5 Developers assert64(tc); 138110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 138210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 138310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 13848284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 13858284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 13868284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 13878284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 138810037SARM gem5 Developers asid = bits(newVal, 63, 48); 138910709SAndreas.Sandberg@ARM.com if (!haveLargeAsid64) 139010037SARM gem5 Developers asid &= mask(8); 139110037SARM gem5 Developers oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 139210037SARM gem5 Developers oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 139310037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 139410037SARM gem5 Developers if (checker) { 139510037SARM gem5 Developers checker->getITBPtr()->flushAsid(asid, 139610037SARM gem5 Developers secure_lookup, target_el); 139710037SARM gem5 Developers checker->getDTBPtr()->flushAsid(asid, 139810037SARM gem5 Developers secure_lookup, target_el); 139910037SARM gem5 Developers } 140010037SARM gem5 Developers } 140110037SARM gem5 Developers return; 140210037SARM gem5 Developers // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 140310037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 140410037SARM gem5 Developers // entries from the last level of translation table walks 140510037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 140610037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 140710037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 140810037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 140910037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 141010037SARM gem5 Developers assert64(tc); 141110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 141210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 141310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 141410037SARM gem5 Developers sys = tc->getSystemPtr(); 141510037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 141610037SARM gem5 Developers // @todo: extra controls on TLBI broadcast? 141710037SARM gem5 Developers oc = sys->getThreadContext(x); 141810037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 141910037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 142010037SARM gem5 Developers oc->getITBPtr()->flushMva(va, 142110037SARM gem5 Developers secure_lookup, false, target_el); 142210037SARM gem5 Developers oc->getDTBPtr()->flushMva(va, 142310037SARM gem5 Developers secure_lookup, false, target_el); 14248887Sgeoffrey.blake@arm.com 14258887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 14268733Sgeoffrey.blake@arm.com if (checker) { 142710037SARM gem5 Developers checker->getITBPtr()->flushMva(va, 142810037SARM gem5 Developers secure_lookup, false, target_el); 142910037SARM gem5 Developers checker->getDTBPtr()->flushMva(va, 143010037SARM gem5 Developers secure_lookup, false, target_el); 14318733Sgeoffrey.blake@arm.com } 14328284SAli.Saidi@ARM.com } 14337408Sgblack@eecs.umich.edu return; 143410037SARM gem5 Developers // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 143510037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 143610037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1_Xt: 143710037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 143810037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1_Xt: 143910037SARM gem5 Developers assert64(tc); 144010037SARM gem5 Developers // @todo: implement these as part of Virtualization 144110037SARM gem5 Developers warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); 14427405SAli.Saidi@ARM.com return; 14437583SAli.Saidi@arm.com case MISCREG_ACTLR: 14447583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 14457583SAli.Saidi@arm.com break; 144610461SAndreas.Sandberg@ARM.com 144710461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 144810461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 144910461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 145010461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 145110461SAndreas.Sandberg@ARM.com pmu->setMiscReg(misc_reg, newVal); 14527583SAli.Saidi@arm.com break; 145310461SAndreas.Sandberg@ARM.com 145410461SAndreas.Sandberg@ARM.com 145510037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 145610037SARM gem5 Developers { 145710037SARM gem5 Developers HSTR hstrMask = 0; 145810037SARM gem5 Developers hstrMask.tjdbx = 1; 145910037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 146010037SARM gem5 Developers break; 146110037SARM gem5 Developers } 146210037SARM gem5 Developers case MISCREG_HCPTR: 146310037SARM gem5 Developers { 146410037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 146510037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 146610037SARM gem5 Developers secure_lookup = haveSecurity && 146710037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 146810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 146910037SARM gem5 Developers if (!secure_lookup) { 147010037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 147110037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 147210037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 147310037SARM gem5 Developers } 147410037SARM gem5 Developers break; 147510037SARM gem5 Developers } 147610037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 147710037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 147810037SARM gem5 Developers break; 147910037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 148010037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 148110037SARM gem5 Developers break; 148210037SARM gem5 Developers case MISCREG_ATS1CPR: 148310037SARM gem5 Developers case MISCREG_ATS1CPW: 148410037SARM gem5 Developers case MISCREG_ATS1CUR: 148510037SARM gem5 Developers case MISCREG_ATS1CUW: 148610037SARM gem5 Developers case MISCREG_ATS12NSOPR: 148710037SARM gem5 Developers case MISCREG_ATS12NSOPW: 148810037SARM gem5 Developers case MISCREG_ATS12NSOUR: 148910037SARM gem5 Developers case MISCREG_ATS12NSOUW: 149010037SARM gem5 Developers case MISCREG_ATS1HR: 149110037SARM gem5 Developers case MISCREG_ATS1HW: 14927436Sdam.sunwoo@arm.com { 149310037SARM gem5 Developers unsigned flags = 0; 149410037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 149510037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 14967436Sdam.sunwoo@arm.com Fault fault; 14977436Sdam.sunwoo@arm.com switch(misc_reg) { 149810037SARM gem5 Developers case MISCREG_ATS1CPR: 149910037SARM gem5 Developers flags = TLB::MustBeOne; 150010037SARM gem5 Developers tranType = TLB::S1CTran; 150110037SARM gem5 Developers mode = BaseTLB::Read; 150210037SARM gem5 Developers break; 150310037SARM gem5 Developers case MISCREG_ATS1CPW: 150410037SARM gem5 Developers flags = TLB::MustBeOne; 150510037SARM gem5 Developers tranType = TLB::S1CTran; 150610037SARM gem5 Developers mode = BaseTLB::Write; 150710037SARM gem5 Developers break; 150810037SARM gem5 Developers case MISCREG_ATS1CUR: 150910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 151010037SARM gem5 Developers tranType = TLB::S1CTran; 151110037SARM gem5 Developers mode = BaseTLB::Read; 151210037SARM gem5 Developers break; 151310037SARM gem5 Developers case MISCREG_ATS1CUW: 151410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 151510037SARM gem5 Developers tranType = TLB::S1CTran; 151610037SARM gem5 Developers mode = BaseTLB::Write; 151710037SARM gem5 Developers break; 151810037SARM gem5 Developers case MISCREG_ATS12NSOPR: 151910037SARM gem5 Developers if (!haveSecurity) 152010037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 152110037SARM gem5 Developers flags = TLB::MustBeOne; 152210037SARM gem5 Developers tranType = TLB::S1S2NsTran; 152310037SARM gem5 Developers mode = BaseTLB::Read; 152410037SARM gem5 Developers break; 152510037SARM gem5 Developers case MISCREG_ATS12NSOPW: 152610037SARM gem5 Developers if (!haveSecurity) 152710037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 152810037SARM gem5 Developers flags = TLB::MustBeOne; 152910037SARM gem5 Developers tranType = TLB::S1S2NsTran; 153010037SARM gem5 Developers mode = BaseTLB::Write; 153110037SARM gem5 Developers break; 153210037SARM gem5 Developers case MISCREG_ATS12NSOUR: 153310037SARM gem5 Developers if (!haveSecurity) 153410037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 153510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 153610037SARM gem5 Developers tranType = TLB::S1S2NsTran; 153710037SARM gem5 Developers mode = BaseTLB::Read; 153810037SARM gem5 Developers break; 153910037SARM gem5 Developers case MISCREG_ATS12NSOUW: 154010037SARM gem5 Developers if (!haveSecurity) 154110037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 154210037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 154310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 154410037SARM gem5 Developers mode = BaseTLB::Write; 154510037SARM gem5 Developers break; 154610037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 154710037SARM gem5 Developers flags = TLB::MustBeOne; 154810037SARM gem5 Developers tranType = TLB::HypMode; 154910037SARM gem5 Developers mode = BaseTLB::Read; 155010037SARM gem5 Developers break; 155110037SARM gem5 Developers case MISCREG_ATS1HW: 155210037SARM gem5 Developers flags = TLB::MustBeOne; 155310037SARM gem5 Developers tranType = TLB::HypMode; 155410037SARM gem5 Developers mode = BaseTLB::Write; 155510037SARM gem5 Developers break; 15567436Sdam.sunwoo@arm.com } 155710037SARM gem5 Developers // If we're in timing mode then doing the translation in 155810037SARM gem5 Developers // functional mode then we're slightly distorting performance 155910037SARM gem5 Developers // results obtained from simulations. The translation should be 156010037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 156110037SARM gem5 Developers // can't be an atomic translation because that causes problems 156210037SARM gem5 Developers // with unexpected atomic snoop requests. 156310037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 156410653Sandreas.hansson@arm.com Request req(0, val, 1, flags, Request::funcMasterId, 156510653Sandreas.hansson@arm.com tc->pcState().pc(), tc->contextId(), 156610653Sandreas.hansson@arm.com tc->threadId()); 156710653Sandreas.hansson@arm.com fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 156810037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 156910037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 157010037SARM gem5 Developers 157110037SARM gem5 Developers MiscReg newVal; 15727436Sdam.sunwoo@arm.com if (fault == NoFault) { 157310653Sandreas.hansson@arm.com Addr paddr = req.getPaddr(); 157410037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 157510037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 157610037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 157710037SARM gem5 Developers (tc->getDTBPtr()->getAttr()); 157810037SARM gem5 Developers } else { 157910037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 158010037SARM gem5 Developers (tc->getDTBPtr()->getAttr()); 158110037SARM gem5 Developers } 15827436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 15837436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 158410037SARM gem5 Developers val, newVal); 158510037SARM gem5 Developers } else { 158610037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 158710037SARM gem5 Developers // Set fault bit and FSR 158810037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 158910037SARM gem5 Developers 159010037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 159110037SARM gem5 Developers if (newVal) { 159210037SARM gem5 Developers // LPAE - rearange fault status 159310037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 159410037SARM gem5 Developers } else { 159510037SARM gem5 Developers // VMSA - rearange fault status 159610037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 159710037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 159810037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 159910037SARM gem5 Developers } 160010037SARM gem5 Developers newVal |= 0x1; // F bit 160110037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 160210037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 160310037SARM gem5 Developers DPRINTF(MiscRegs, 160410037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 160510037SARM gem5 Developers val, fsr, newVal); 16067436Sdam.sunwoo@arm.com } 160710037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 16087436Sdam.sunwoo@arm.com return; 16097436Sdam.sunwoo@arm.com } 161010037SARM gem5 Developers case MISCREG_TTBCR: 161110037SARM gem5 Developers { 161210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 161310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 161410037SARM gem5 Developers TTBCR ttbcrMask = 0; 161510037SARM gem5 Developers TTBCR ttbcrNew = newVal; 161610037SARM gem5 Developers 161710037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 161810037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 161910037SARM gem5 Developers if (haveSecurity) { 162010037SARM gem5 Developers ttbcrMask.pd0 = ones; 162110037SARM gem5 Developers ttbcrMask.pd1 = ones; 162210037SARM gem5 Developers } 162310037SARM gem5 Developers ttbcrMask.epd0 = ones; 162410037SARM gem5 Developers ttbcrMask.irgn0 = ones; 162510037SARM gem5 Developers ttbcrMask.orgn0 = ones; 162610037SARM gem5 Developers ttbcrMask.sh0 = ones; 162710037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 162810037SARM gem5 Developers ttbcrMask.a1 = ones; 162910037SARM gem5 Developers ttbcrMask.epd1 = ones; 163010037SARM gem5 Developers ttbcrMask.irgn1 = ones; 163110037SARM gem5 Developers ttbcrMask.orgn1 = ones; 163210037SARM gem5 Developers ttbcrMask.sh1 = ones; 163310037SARM gem5 Developers if (haveLPAE) 163410037SARM gem5 Developers ttbcrMask.eae = ones; 163510037SARM gem5 Developers 163610037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 163710037SARM gem5 Developers newVal = newVal & ttbcrMask; 163810037SARM gem5 Developers } else { 163910037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 164010037SARM gem5 Developers } 164110037SARM gem5 Developers } 164210037SARM gem5 Developers case MISCREG_TTBR0: 164310037SARM gem5 Developers case MISCREG_TTBR1: 164410037SARM gem5 Developers { 164510037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 164610037SARM gem5 Developers if (haveLPAE) { 164710037SARM gem5 Developers if (ttbcr.eae) { 164810037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 164910037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 165010037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 165110037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 165210037SARM gem5 Developers } 165310037SARM gem5 Developers } 165410037SARM gem5 Developers } 165510508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL1: 165610508SAli.Saidi@ARM.com { 165710508SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 165810508SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 165910508SAli.Saidi@ARM.com SCTLR new_sctlr = newVal; 166010508SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 166110508SAli.Saidi@ARM.com if (new_sctlr.c) 166210508SAli.Saidi@ARM.com updateBootUncacheable(misc_reg, tc); 166310508SAli.Saidi@ARM.com return; 166410508SAli.Saidi@ARM.com } 16657749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 16667749SAli.Saidi@ARM.com case MISCREG_PRRR: 16677749SAli.Saidi@ARM.com case MISCREG_NMRR: 166810037SARM gem5 Developers case MISCREG_MAIR0: 166910037SARM gem5 Developers case MISCREG_MAIR1: 16707749SAli.Saidi@ARM.com case MISCREG_DACR: 167110037SARM gem5 Developers case MISCREG_VTTBR: 167210037SARM gem5 Developers case MISCREG_SCR_EL3: 167310037SARM gem5 Developers case MISCREG_TCR_EL1: 167410037SARM gem5 Developers case MISCREG_TCR_EL2: 167510037SARM gem5 Developers case MISCREG_TCR_EL3: 167610508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 167710508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 167810037SARM gem5 Developers case MISCREG_TTBR0_EL1: 167910037SARM gem5 Developers case MISCREG_TTBR1_EL1: 168010037SARM gem5 Developers case MISCREG_TTBR0_EL2: 168110037SARM gem5 Developers case MISCREG_TTBR0_EL3: 16827749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 16837749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 16847749SAli.Saidi@ARM.com break; 168510037SARM gem5 Developers case MISCREG_NZCV: 168610037SARM gem5 Developers { 168710037SARM gem5 Developers CPSR cpsr = val; 168810037SARM gem5 Developers 168910338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_NZ, cpsr.nz); 169010338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_C, cpsr.c); 169110338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_V, cpsr.v); 169210037SARM gem5 Developers } 169310037SARM gem5 Developers break; 169410037SARM gem5 Developers case MISCREG_DAIF: 169510037SARM gem5 Developers { 169610037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 169710037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 169810037SARM gem5 Developers newVal = cpsr; 169910037SARM gem5 Developers misc_reg = MISCREG_CPSR; 170010037SARM gem5 Developers } 170110037SARM gem5 Developers break; 170210037SARM gem5 Developers case MISCREG_SP_EL0: 170310037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 170410037SARM gem5 Developers break; 170510037SARM gem5 Developers case MISCREG_SP_EL1: 170610037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 170710037SARM gem5 Developers break; 170810037SARM gem5 Developers case MISCREG_SP_EL2: 170910037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 171010037SARM gem5 Developers break; 171110037SARM gem5 Developers case MISCREG_SPSEL: 171210037SARM gem5 Developers { 171310037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 171410037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 171510037SARM gem5 Developers newVal = cpsr; 171610037SARM gem5 Developers misc_reg = MISCREG_CPSR; 171710037SARM gem5 Developers } 171810037SARM gem5 Developers break; 171910037SARM gem5 Developers case MISCREG_CURRENTEL: 172010037SARM gem5 Developers { 172110037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 172210037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 172310037SARM gem5 Developers newVal = cpsr; 172410037SARM gem5 Developers misc_reg = MISCREG_CPSR; 172510037SARM gem5 Developers } 172610037SARM gem5 Developers break; 172710037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 172810037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 172910037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 173010037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 173110037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 173210037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 173310037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 173410037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 173510037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 173610037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 173710037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 173810037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 173910037SARM gem5 Developers { 174010037SARM gem5 Developers RequestPtr req = new Request; 174110037SARM gem5 Developers unsigned flags = 0; 174210037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 174310037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 174410037SARM gem5 Developers Fault fault; 174510037SARM gem5 Developers switch(misc_reg) { 174610037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 174710037SARM gem5 Developers flags = TLB::MustBeOne; 174810037SARM gem5 Developers tranType = TLB::S1CTran; 174910037SARM gem5 Developers mode = BaseTLB::Read; 175010037SARM gem5 Developers break; 175110037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 175210037SARM gem5 Developers flags = TLB::MustBeOne; 175310037SARM gem5 Developers tranType = TLB::S1CTran; 175410037SARM gem5 Developers mode = BaseTLB::Write; 175510037SARM gem5 Developers break; 175610037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 175710037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 175810037SARM gem5 Developers tranType = TLB::S1CTran; 175910037SARM gem5 Developers mode = BaseTLB::Read; 176010037SARM gem5 Developers break; 176110037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 176210037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 176310037SARM gem5 Developers tranType = TLB::S1CTran; 176410037SARM gem5 Developers mode = BaseTLB::Write; 176510037SARM gem5 Developers break; 176610037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 176710037SARM gem5 Developers flags = TLB::MustBeOne; 176810037SARM gem5 Developers tranType = TLB::HypMode; 176910037SARM gem5 Developers mode = BaseTLB::Read; 177010037SARM gem5 Developers break; 177110037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 177210037SARM gem5 Developers flags = TLB::MustBeOne; 177310037SARM gem5 Developers tranType = TLB::HypMode; 177410037SARM gem5 Developers mode = BaseTLB::Write; 177510037SARM gem5 Developers break; 177610037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 177710037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 177810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 177910037SARM gem5 Developers mode = BaseTLB::Read; 178010037SARM gem5 Developers break; 178110037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 178210037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 178310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 178410037SARM gem5 Developers mode = BaseTLB::Write; 178510037SARM gem5 Developers break; 178610037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 178710037SARM gem5 Developers flags = TLB::MustBeOne; 178810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 178910037SARM gem5 Developers mode = BaseTLB::Read; 179010037SARM gem5 Developers break; 179110037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 179210037SARM gem5 Developers flags = TLB::MustBeOne; 179310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 179410037SARM gem5 Developers mode = BaseTLB::Write; 179510037SARM gem5 Developers break; 179610037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 179710037SARM gem5 Developers flags = TLB::MustBeOne; 179810037SARM gem5 Developers tranType = TLB::HypMode; // There is no TZ mode defined. 179910037SARM gem5 Developers mode = BaseTLB::Read; 180010037SARM gem5 Developers break; 180110037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 180210037SARM gem5 Developers flags = TLB::MustBeOne; 180310037SARM gem5 Developers tranType = TLB::HypMode; // There is no TZ mode defined. 180410037SARM gem5 Developers mode = BaseTLB::Write; 180510037SARM gem5 Developers break; 180610037SARM gem5 Developers } 180710037SARM gem5 Developers // If we're in timing mode then doing the translation in 180810037SARM gem5 Developers // functional mode then we're slightly distorting performance 180910037SARM gem5 Developers // results obtained from simulations. The translation should be 181010037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 181110037SARM gem5 Developers // can't be an atomic translation because that causes problems 181210037SARM gem5 Developers // with unexpected atomic snoop requests. 181310037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 181410037SARM gem5 Developers req->setVirt(0, val, 1, flags, Request::funcMasterId, 181510037SARM gem5 Developers tc->pcState().pc()); 181610037SARM gem5 Developers req->setThreadContext(tc->contextId(), tc->threadId()); 181710037SARM gem5 Developers fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 181810037SARM gem5 Developers tranType); 181910037SARM gem5 Developers 182010037SARM gem5 Developers MiscReg newVal; 182110037SARM gem5 Developers if (fault == NoFault) { 182210037SARM gem5 Developers Addr paddr = req->getPaddr(); 182310037SARM gem5 Developers uint64_t attr = tc->getDTBPtr()->getAttr(); 182410037SARM gem5 Developers uint64_t attr1 = attr >> 56; 182510037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 182610037SARM gem5 Developers attr |= 0x100; 182710037SARM gem5 Developers attr &= ~ uint64_t(0x80); 182810037SARM gem5 Developers } 182910037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 183010037SARM gem5 Developers DPRINTF(MiscRegs, 183110037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 183210037SARM gem5 Developers val, newVal); 183310037SARM gem5 Developers } else { 183410037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 183510037SARM gem5 Developers // Set fault bit and FSR 183610037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 183710037SARM gem5 Developers 183810037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 183910037SARM gem5 Developers // rearange fault status 184010037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 184110037SARM gem5 Developers newVal |= 0x1; // F bit 184210037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 184310037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 184410037SARM gem5 Developers DPRINTF(MiscRegs, 184510037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 184610037SARM gem5 Developers val, fsr, newVal); 184710037SARM gem5 Developers } 184810037SARM gem5 Developers delete req; 184910037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 185010037SARM gem5 Developers return; 185110037SARM gem5 Developers } 185210037SARM gem5 Developers case MISCREG_SPSR_EL3: 185310037SARM gem5 Developers case MISCREG_SPSR_EL2: 185410037SARM gem5 Developers case MISCREG_SPSR_EL1: 185510037SARM gem5 Developers // Force bits 23:21 to 0 185610037SARM gem5 Developers newVal = val & ~(0x7 << 21); 185710037SARM gem5 Developers break; 18588549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 18598549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 18608549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 186110037SARM gem5 Developers break; 186210037SARM gem5 Developers 186310037SARM gem5 Developers // Generic Timer registers 186410037SARM gem5 Developers case MISCREG_CNTFRQ: 186510037SARM gem5 Developers case MISCREG_CNTFRQ_EL0: 186610037SARM gem5 Developers getSystemCounter(tc)->setFreq(val); 186710037SARM gem5 Developers break; 186810037SARM gem5 Developers case MISCREG_CNTP_CVAL: 186910037SARM gem5 Developers case MISCREG_CNTP_CVAL_EL0: 187010037SARM gem5 Developers getArchTimer(tc, tc->cpuId())->setCompareValue(val); 187110037SARM gem5 Developers break; 187210037SARM gem5 Developers case MISCREG_CNTP_TVAL: 187310037SARM gem5 Developers case MISCREG_CNTP_TVAL_EL0: 187410037SARM gem5 Developers getArchTimer(tc, tc->cpuId())->setTimerValue(val); 187510037SARM gem5 Developers break; 187610037SARM gem5 Developers case MISCREG_CNTP_CTL: 187710037SARM gem5 Developers case MISCREG_CNTP_CTL_EL0: 187810037SARM gem5 Developers getArchTimer(tc, tc->cpuId())->setControl(val); 187910037SARM gem5 Developers break; 188010037SARM gem5 Developers // PL1 phys. timer, secure 188110037SARM gem5 Developers // AArch64 188210037SARM gem5 Developers case MISCREG_CNTPS_CVAL_EL1: 188310037SARM gem5 Developers case MISCREG_CNTPS_TVAL_EL1: 188410037SARM gem5 Developers case MISCREG_CNTPS_CTL_EL1: 188510037SARM gem5 Developers // PL2 phys. timer, non-secure 188610037SARM gem5 Developers // AArch32 188710037SARM gem5 Developers case MISCREG_CNTHCTL: 188810037SARM gem5 Developers case MISCREG_CNTHP_CVAL: 188910037SARM gem5 Developers case MISCREG_CNTHP_TVAL: 189010037SARM gem5 Developers case MISCREG_CNTHP_CTL: 189110037SARM gem5 Developers // AArch64 189210037SARM gem5 Developers case MISCREG_CNTHCTL_EL2: 189310037SARM gem5 Developers case MISCREG_CNTHP_CVAL_EL2: 189410037SARM gem5 Developers case MISCREG_CNTHP_TVAL_EL2: 189510037SARM gem5 Developers case MISCREG_CNTHP_CTL_EL2: 189610037SARM gem5 Developers // Virtual timer 189710037SARM gem5 Developers // AArch32 189810037SARM gem5 Developers case MISCREG_CNTV_CVAL: 189910037SARM gem5 Developers case MISCREG_CNTV_TVAL: 190010037SARM gem5 Developers case MISCREG_CNTV_CTL: 190110037SARM gem5 Developers // AArch64 190210037SARM gem5 Developers // case MISCREG_CNTV_CVAL_EL2: 190310037SARM gem5 Developers // case MISCREG_CNTV_TVAL_EL2: 190410037SARM gem5 Developers // case MISCREG_CNTV_CTL_EL2: 190510037SARM gem5 Developers break; 19067405SAli.Saidi@ARM.com } 19077405SAli.Saidi@ARM.com } 19087405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 19097405SAli.Saidi@ARM.com} 19107405SAli.Saidi@ARM.com 191110037SARM gem5 Developersvoid 191210508SAli.Saidi@ARM.comISA::updateBootUncacheable(int sctlr_idx, ThreadContext *tc) 191310508SAli.Saidi@ARM.com{ 191410508SAli.Saidi@ARM.com System *sys; 191510508SAli.Saidi@ARM.com ThreadContext *oc; 191610508SAli.Saidi@ARM.com 191710508SAli.Saidi@ARM.com // Check if all CPUs are booted with caches enabled 191810508SAli.Saidi@ARM.com // so we can stop enforcing coherency of some kernel 191910508SAli.Saidi@ARM.com // structures manually. 192010508SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 192110508SAli.Saidi@ARM.com for (int x = 0; x < sys->numContexts(); x++) { 192210508SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 192310508SAli.Saidi@ARM.com // @todo: double check this for security 192410508SAli.Saidi@ARM.com SCTLR other_sctlr = oc->readMiscRegNoEffect(sctlr_idx); 192510508SAli.Saidi@ARM.com if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 192610508SAli.Saidi@ARM.com return; 192710508SAli.Saidi@ARM.com } 192810508SAli.Saidi@ARM.com 192910508SAli.Saidi@ARM.com for (int x = 0; x < sys->numContexts(); x++) { 193010508SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 193110508SAli.Saidi@ARM.com oc->getDTBPtr()->allCpusCaching(); 193210508SAli.Saidi@ARM.com oc->getITBPtr()->allCpusCaching(); 193310508SAli.Saidi@ARM.com 193410508SAli.Saidi@ARM.com // If CheckerCPU is connected, need to notify it. 193510508SAli.Saidi@ARM.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 193610508SAli.Saidi@ARM.com if (checker) { 193710508SAli.Saidi@ARM.com checker->getDTBPtr()->allCpusCaching(); 193810508SAli.Saidi@ARM.com checker->getITBPtr()->allCpusCaching(); 193910508SAli.Saidi@ARM.com } 194010508SAli.Saidi@ARM.com } 194110508SAli.Saidi@ARM.com} 194210508SAli.Saidi@ARM.com 194310508SAli.Saidi@ARM.comvoid 194410709SAndreas.Sandberg@ARM.comISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 194510709SAndreas.Sandberg@ARM.com bool secure_lookup, uint8_t target_el) 194610037SARM gem5 Developers{ 194710709SAndreas.Sandberg@ARM.com if (!haveLargeAsid64) 194810037SARM gem5 Developers asid &= mask(8); 194910037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 195010037SARM gem5 Developers System *sys = tc->getSystemPtr(); 195110037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 195210037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 195310037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 195410037SARM gem5 Developers oc->getITBPtr()->flushMvaAsid(va, asid, 195510037SARM gem5 Developers secure_lookup, target_el); 195610037SARM gem5 Developers oc->getDTBPtr()->flushMvaAsid(va, asid, 195710037SARM gem5 Developers secure_lookup, target_el); 195810037SARM gem5 Developers 195910037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 196010037SARM gem5 Developers if (checker) { 196110037SARM gem5 Developers checker->getITBPtr()->flushMvaAsid( 196210037SARM gem5 Developers va, asid, secure_lookup, target_el); 196310037SARM gem5 Developers checker->getDTBPtr()->flushMvaAsid( 196410037SARM gem5 Developers va, asid, secure_lookup, target_el); 196510037SARM gem5 Developers } 196610037SARM gem5 Developers } 196710037SARM gem5 Developers} 196810037SARM gem5 Developers 196910037SARM gem5 Developersvoid 197010037SARM gem5 DevelopersISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 197110037SARM gem5 Developers{ 197210037SARM gem5 Developers System *sys = tc->getSystemPtr(); 197310037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 197410037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 197510037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 197610037SARM gem5 Developers oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 197710037SARM gem5 Developers oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 197810037SARM gem5 Developers 197910037SARM gem5 Developers // If CheckerCPU is connected, need to notify it of a flush 198010037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 198110037SARM gem5 Developers if (checker) { 198210037SARM gem5 Developers checker->getITBPtr()->flushAllSecurity(secure_lookup, 198310037SARM gem5 Developers target_el); 198410037SARM gem5 Developers checker->getDTBPtr()->flushAllSecurity(secure_lookup, 198510037SARM gem5 Developers target_el); 198610037SARM gem5 Developers } 198710037SARM gem5 Developers } 198810037SARM gem5 Developers} 198910037SARM gem5 Developers 199010037SARM gem5 Developersvoid 199110037SARM gem5 DevelopersISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 199210037SARM gem5 Developers{ 199310037SARM gem5 Developers System *sys = tc->getSystemPtr(); 199410037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 199510037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 199610037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 199710037SARM gem5 Developers oc->getITBPtr()->flushAllNs(hyp, target_el); 199810037SARM gem5 Developers oc->getDTBPtr()->flushAllNs(hyp, target_el); 199910037SARM gem5 Developers 200010037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 200110037SARM gem5 Developers if (checker) { 200210037SARM gem5 Developers checker->getITBPtr()->flushAllNs(hyp, target_el); 200310037SARM gem5 Developers checker->getDTBPtr()->flushAllNs(hyp, target_el); 200410037SARM gem5 Developers } 200510037SARM gem5 Developers } 200610037SARM gem5 Developers} 200710037SARM gem5 Developers 200810037SARM gem5 Developersvoid 200910037SARM gem5 DevelopersISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 201010037SARM gem5 Developers uint8_t target_el) 201110037SARM gem5 Developers{ 201210037SARM gem5 Developers System *sys = tc->getSystemPtr(); 201310037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 201410037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 201510037SARM gem5 Developers assert(oc->getITBPtr() && oc->getDTBPtr()); 201610037SARM gem5 Developers oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 201710037SARM gem5 Developers secure_lookup, hyp, target_el); 201810037SARM gem5 Developers oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 201910037SARM gem5 Developers secure_lookup, hyp, target_el); 202010037SARM gem5 Developers 202110037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 202210037SARM gem5 Developers if (checker) { 202310037SARM gem5 Developers checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 202410037SARM gem5 Developers secure_lookup, hyp, target_el); 202510037SARM gem5 Developers checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 202610037SARM gem5 Developers secure_lookup, hyp, target_el); 202710037SARM gem5 Developers } 202810037SARM gem5 Developers } 202910037SARM gem5 Developers} 203010037SARM gem5 Developers 203110037SARM gem5 Developers::GenericTimer::SystemCounter * 203210037SARM gem5 DevelopersISA::getSystemCounter(ThreadContext *tc) 203310037SARM gem5 Developers{ 203410037SARM gem5 Developers ::GenericTimer::SystemCounter *cnt = ((ArmSystem *) tc->getSystemPtr())-> 203510037SARM gem5 Developers getSystemCounter(); 203610037SARM gem5 Developers if (cnt == NULL) { 203710037SARM gem5 Developers panic("System counter not available\n"); 203810037SARM gem5 Developers } 203910037SARM gem5 Developers return cnt; 204010037SARM gem5 Developers} 204110037SARM gem5 Developers 204210037SARM gem5 Developers::GenericTimer::ArchTimer * 204310037SARM gem5 DevelopersISA::getArchTimer(ThreadContext *tc, int cpu_id) 204410037SARM gem5 Developers{ 204510037SARM gem5 Developers ::GenericTimer::ArchTimer *timer = ((ArmSystem *) tc->getSystemPtr())-> 204610037SARM gem5 Developers getArchTimer(cpu_id); 204710037SARM gem5 Developers if (timer == NULL) { 204810037SARM gem5 Developers panic("Architected timer not available\n"); 204910037SARM gem5 Developers } 205010037SARM gem5 Developers return timer; 205110037SARM gem5 Developers} 205210037SARM gem5 Developers 20537405SAli.Saidi@ARM.com} 20549384SAndreas.Sandberg@arm.com 20559384SAndreas.Sandberg@arm.comArmISA::ISA * 20569384SAndreas.Sandberg@arm.comArmISAParams::create() 20579384SAndreas.Sandberg@arm.com{ 20589384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 20599384SAndreas.Sandberg@arm.com} 2060