misc64.cc revision 14001:11216534c23e 
1/*
2 * Copyright (c) 2011-2013,2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/misc64.hh"
41#include "arch/arm/isa.hh"
42
43std::string
44ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
45{
46    std::stringstream ss;
47    printMnemonic(ss, "", false);
48    ccprintf(ss, "#0x%x", imm);
49    return ss.str();
50}
51
52std::string
53RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
54{
55    std::stringstream ss;
56    printMnemonic(ss, "", false);
57    printIntReg(ss, dest);
58    ss << ", ";
59    printIntReg(ss, op1);
60    ccprintf(ss, ", #%d, #%d", imm1, imm2);
61    return ss.str();
62}
63
64std::string
65RegRegRegImmOp64::generateDisassembly(
66    Addr pc, const SymbolTable *symtab) const
67{
68    std::stringstream ss;
69    printMnemonic(ss, "", false);
70    printIntReg(ss, dest);
71    ss << ", ";
72    printIntReg(ss, op1);
73    ss << ", ";
74    printIntReg(ss, op2);
75    ccprintf(ss, ", #%d", imm);
76    return ss.str();
77}
78
79std::string
80UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
81{
82    return csprintf("%-10s (inst %#08x)", "unknown", encoding());
83}
84
85Fault
86MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
87                  ExceptionLevel el, uint32_t immediate) const
88{
89    bool is_vfp_neon = false;
90
91    // Check for traps to supervisor (FP/SIMD regs)
92    if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) {
93
94        return std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
95                                                EC_TRAPPED_SIMD_FP);
96    }
97
98    // Check for traps to hypervisor
99    if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
100        checkEL2Trap(tc, misc_reg, el, &is_vfp_neon)) {
101
102        return std::make_shared<HypervisorTrap>(
103            machInst, is_vfp_neon ? 0x1E00000 : immediate,
104            is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
105    }
106
107    // Check for traps to secure monitor
108    if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
109        checkEL3Trap(tc, misc_reg, el, &is_vfp_neon)) {
110
111        return std::make_shared<SecureMonitorTrap>(
112            machInst,
113            is_vfp_neon ? 0x1E00000 : immediate,
114            is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
115    }
116
117    return NoFault;
118}
119
120bool
121MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
122                          ExceptionLevel el) const
123{
124    const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
125
126    bool trap_to_sup = false;
127    switch (misc_reg) {
128      case MISCREG_FPCR:
129      case MISCREG_FPSR:
130      case MISCREG_FPEXC32_EL2:
131        if ((el == EL0 && cpacr.fpen != 0x3) ||
132            (el == EL1 && !(cpacr.fpen & 0x1)))
133            trap_to_sup = true;
134        break;
135      default:
136        break;
137    }
138    return trap_to_sup;
139}
140
141bool
142MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
143                          ExceptionLevel el, bool * is_vfp_neon) const
144{
145    const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
146    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
147    const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
148    const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
149
150    bool trap_to_hyp = false;
151    *is_vfp_neon = false;
152
153    if (!inSecureState(scr, cpsr) && (el != EL2)) {
154        switch (misc_reg) {
155          // FP/SIMD regs
156          case MISCREG_FPCR:
157          case MISCREG_FPSR:
158          case MISCREG_FPEXC32_EL2:
159            trap_to_hyp = cptr.tfp;
160            *is_vfp_neon = true;
161            break;
162          // CPACR
163          case MISCREG_CPACR_EL1:
164            trap_to_hyp = cptr.tcpac && el == EL1;
165            break;
166          // Virtual memory control regs
167          case MISCREG_SCTLR_EL1:
168          case MISCREG_TTBR0_EL1:
169          case MISCREG_TTBR1_EL1:
170          case MISCREG_TCR_EL1:
171          case MISCREG_ESR_EL1:
172          case MISCREG_FAR_EL1:
173          case MISCREG_AFSR0_EL1:
174          case MISCREG_AFSR1_EL1:
175          case MISCREG_MAIR_EL1:
176          case MISCREG_AMAIR_EL1:
177          case MISCREG_CONTEXTIDR_EL1:
178            trap_to_hyp =
179                ((hcr.trvm && miscRead) || (hcr.tvm && !miscRead)) &&
180                el == EL1;
181            break;
182          // TLB maintenance instructions
183          case MISCREG_TLBI_VMALLE1:
184          case MISCREG_TLBI_VAE1_Xt:
185          case MISCREG_TLBI_ASIDE1_Xt:
186          case MISCREG_TLBI_VAAE1_Xt:
187          case MISCREG_TLBI_VALE1_Xt:
188          case MISCREG_TLBI_VAALE1_Xt:
189          case MISCREG_TLBI_VMALLE1IS:
190          case MISCREG_TLBI_VAE1IS_Xt:
191          case MISCREG_TLBI_ASIDE1IS_Xt:
192          case MISCREG_TLBI_VAAE1IS_Xt:
193          case MISCREG_TLBI_VALE1IS_Xt:
194          case MISCREG_TLBI_VAALE1IS_Xt:
195            trap_to_hyp = hcr.ttlb && el == EL1;
196            break;
197          // Cache maintenance instructions to the point of unification
198          case MISCREG_IC_IVAU_Xt:
199          case MISCREG_ICIALLU:
200          case MISCREG_ICIALLUIS:
201          case MISCREG_DC_CVAU_Xt:
202            trap_to_hyp = hcr.tpu && el <= EL1;
203            break;
204          // Data/Unified cache maintenance instructions to the
205          // point of coherency
206          case MISCREG_DC_IVAC_Xt:
207          case MISCREG_DC_CIVAC_Xt:
208          case MISCREG_DC_CVAC_Xt:
209            trap_to_hyp = hcr.tpc && el <= EL1;
210            break;
211          // Data/Unified cache maintenance instructions by set/way
212          case MISCREG_DC_ISW_Xt:
213          case MISCREG_DC_CSW_Xt:
214          case MISCREG_DC_CISW_Xt:
215            trap_to_hyp = hcr.tsw && el == EL1;
216            break;
217          // ACTLR
218          case MISCREG_ACTLR_EL1:
219            trap_to_hyp = hcr.tacr && el == EL1;
220            break;
221
222          // @todo: Trap implementation-dependent functionality based on
223          // hcr.tidcp
224
225          // ID regs, group 3
226          case MISCREG_ID_PFR0_EL1:
227          case MISCREG_ID_PFR1_EL1:
228          case MISCREG_ID_DFR0_EL1:
229          case MISCREG_ID_AFR0_EL1:
230          case MISCREG_ID_MMFR0_EL1:
231          case MISCREG_ID_MMFR1_EL1:
232          case MISCREG_ID_MMFR2_EL1:
233          case MISCREG_ID_MMFR3_EL1:
234          case MISCREG_ID_ISAR0_EL1:
235          case MISCREG_ID_ISAR1_EL1:
236          case MISCREG_ID_ISAR2_EL1:
237          case MISCREG_ID_ISAR3_EL1:
238          case MISCREG_ID_ISAR4_EL1:
239          case MISCREG_ID_ISAR5_EL1:
240          case MISCREG_MVFR0_EL1:
241          case MISCREG_MVFR1_EL1:
242          case MISCREG_MVFR2_EL1:
243          case MISCREG_ID_AA64PFR0_EL1:
244          case MISCREG_ID_AA64PFR1_EL1:
245          case MISCREG_ID_AA64DFR0_EL1:
246          case MISCREG_ID_AA64DFR1_EL1:
247          case MISCREG_ID_AA64ISAR0_EL1:
248          case MISCREG_ID_AA64ISAR1_EL1:
249          case MISCREG_ID_AA64MMFR0_EL1:
250          case MISCREG_ID_AA64MMFR1_EL1:
251          case MISCREG_ID_AA64MMFR2_EL1:
252          case MISCREG_ID_AA64AFR0_EL1:
253          case MISCREG_ID_AA64AFR1_EL1:
254            assert(miscRead);
255            trap_to_hyp = hcr.tid3 && el == EL1;
256            break;
257          // ID regs, group 2
258          case MISCREG_CTR_EL0:
259          case MISCREG_CCSIDR_EL1:
260          case MISCREG_CLIDR_EL1:
261          case MISCREG_CSSELR_EL1:
262            trap_to_hyp = hcr.tid2 && el <= EL1;
263            break;
264          // ID regs, group 1
265          case MISCREG_AIDR_EL1:
266          case MISCREG_REVIDR_EL1:
267            assert(miscRead);
268            trap_to_hyp = hcr.tid1 && el == EL1;
269            break;
270          case MISCREG_IMPDEF_UNIMPL:
271            trap_to_hyp = hcr.tidcp && el == EL1;
272          // GICv3 regs
273          case MISCREG_ICC_SGI0R_EL1:
274            if (tc->getIsaPtr()->haveGICv3CpuIfc())
275                trap_to_hyp = hcr.fmo && el == EL1;
276            break;
277          case MISCREG_ICC_SGI1R_EL1:
278          case MISCREG_ICC_ASGI1R_EL1:
279            if (tc->getIsaPtr()->haveGICv3CpuIfc())
280                trap_to_hyp = hcr.imo && el == EL1;
281            break;
282          default:
283            break;
284        }
285    }
286    return trap_to_hyp;
287}
288
289bool
290MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
291                          ExceptionLevel el, bool * is_vfp_neon) const
292{
293    const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
294
295    bool trap_to_mon = false;
296    *is_vfp_neon = false;
297
298    switch (misc_reg) {
299      // FP/SIMD regs
300      case MISCREG_FPCR:
301      case MISCREG_FPSR:
302      case MISCREG_FPEXC32_EL2:
303        trap_to_mon = cptr.tfp;
304        *is_vfp_neon = true;
305        break;
306      // CPACR, CPTR
307      case MISCREG_CPACR_EL1:
308        if (el == EL1 || el == EL2) {
309           trap_to_mon = cptr.tcpac;
310        }
311        break;
312      case MISCREG_CPTR_EL2:
313        if (el == EL2) {
314            trap_to_mon = cptr.tcpac;
315        }
316        break;
317      default:
318        break;
319    }
320    return trap_to_mon;
321}
322
323std::string
324MiscRegRegImmOp64::generateDisassembly(
325    Addr pc, const SymbolTable *symtab) const
326{
327    std::stringstream ss;
328    printMnemonic(ss);
329    printMiscReg(ss, dest);
330    ss << ", ";
331    printIntReg(ss, op1);
332    return ss.str();
333}
334
335std::string
336RegMiscRegImmOp64::generateDisassembly(
337    Addr pc, const SymbolTable *symtab) const
338{
339    std::stringstream ss;
340    printMnemonic(ss);
341    printIntReg(ss, dest);
342    ss << ", ";
343    printMiscReg(ss, op1);
344    return ss.str();
345}
346
347Fault
348MiscRegImplDefined64::execute(ExecContext *xc,
349                              Trace::InstRecord *traceData) const
350{
351    auto tc = xc->tcBase();
352    const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
353    const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
354
355    Fault fault = trap(tc, miscReg, el, imm);
356
357    if (fault != NoFault) {
358        return fault;
359
360    } else if (warning) {
361        warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str());
362        return NoFault;
363
364    } else {
365        return std::make_shared<UndefinedInstruction>(machInst, false,
366                                                      mnemonic);
367    }
368}
369
370std::string
371MiscRegImplDefined64::generateDisassembly(Addr pc,
372                                          const SymbolTable *symtab) const
373{
374    return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
375}
376