misc64.cc revision 13895:5762b3dc79c6 
1/*
2 * Copyright (c) 2011-2013,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/misc64.hh"
41
42std::string
43ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
44{
45    std::stringstream ss;
46    printMnemonic(ss, "", false);
47    ccprintf(ss, "#0x%x", imm);
48    return ss.str();
49}
50
51std::string
52RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
53{
54    std::stringstream ss;
55    printMnemonic(ss, "", false);
56    printIntReg(ss, dest);
57    ss << ", ";
58    printIntReg(ss, op1);
59    ccprintf(ss, ", #%d, #%d", imm1, imm2);
60    return ss.str();
61}
62
63std::string
64RegRegRegImmOp64::generateDisassembly(
65    Addr pc, const SymbolTable *symtab) const
66{
67    std::stringstream ss;
68    printMnemonic(ss, "", false);
69    printIntReg(ss, dest);
70    ss << ", ";
71    printIntReg(ss, op1);
72    ss << ", ";
73    printIntReg(ss, op2);
74    ccprintf(ss, ", #%d", imm);
75    return ss.str();
76}
77
78std::string
79UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
80{
81    return csprintf("%-10s (inst %#08x)", "unknown", encoding());
82}
83
84Fault
85MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
86                  ExceptionLevel el, uint32_t immediate) const
87{
88    bool is_vfp_neon = false;
89
90    // Check for traps to supervisor (FP/SIMD regs)
91    if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) {
92
93        return std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
94                                                EC_TRAPPED_SIMD_FP);
95    }
96
97    // Check for traps to hypervisor
98    if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
99        checkEL2Trap(tc, misc_reg, el, &is_vfp_neon)) {
100
101        return std::make_shared<HypervisorTrap>(
102            machInst, is_vfp_neon ? 0x1E00000 : immediate,
103            is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
104    }
105
106    // Check for traps to secure monitor
107    if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
108        checkEL3Trap(tc, misc_reg, el, &is_vfp_neon)) {
109
110        return std::make_shared<SecureMonitorTrap>(
111            machInst,
112            is_vfp_neon ? 0x1E00000 : immediate,
113            is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
114    }
115
116    return NoFault;
117}
118
119bool
120MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
121                          ExceptionLevel el) const
122{
123    const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
124
125    bool trap_to_sup = false;
126    switch (misc_reg) {
127      case MISCREG_FPCR:
128      case MISCREG_FPSR:
129      case MISCREG_FPEXC32_EL2:
130        if ((el == EL0 && cpacr.fpen != 0x3) ||
131            (el == EL1 && !(cpacr.fpen & 0x1)))
132            trap_to_sup = true;
133        break;
134      default:
135        break;
136    }
137    return trap_to_sup;
138}
139
140bool
141MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
142                          ExceptionLevel el, bool * is_vfp_neon) const
143{
144    const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
145    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
146    const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
147    const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
148
149    bool trap_to_hyp = false;
150    *is_vfp_neon = false;
151
152    if (!inSecureState(scr, cpsr) && (el != EL2)) {
153        switch (misc_reg) {
154          // FP/SIMD regs
155          case MISCREG_FPCR:
156          case MISCREG_FPSR:
157          case MISCREG_FPEXC32_EL2:
158            trap_to_hyp = cptr.tfp;
159            *is_vfp_neon = true;
160            break;
161          // CPACR
162          case MISCREG_CPACR_EL1:
163            trap_to_hyp = cptr.tcpac && el == EL1;
164            break;
165          // Virtual memory control regs
166          case MISCREG_SCTLR_EL1:
167          case MISCREG_TTBR0_EL1:
168          case MISCREG_TTBR1_EL1:
169          case MISCREG_TCR_EL1:
170          case MISCREG_ESR_EL1:
171          case MISCREG_FAR_EL1:
172          case MISCREG_AFSR0_EL1:
173          case MISCREG_AFSR1_EL1:
174          case MISCREG_MAIR_EL1:
175          case MISCREG_AMAIR_EL1:
176          case MISCREG_CONTEXTIDR_EL1:
177            trap_to_hyp =
178                ((hcr.trvm && miscRead) || (hcr.tvm && !miscRead)) &&
179                el == EL1;
180            break;
181          // TLB maintenance instructions
182          case MISCREG_TLBI_VMALLE1:
183          case MISCREG_TLBI_VAE1_Xt:
184          case MISCREG_TLBI_ASIDE1_Xt:
185          case MISCREG_TLBI_VAAE1_Xt:
186          case MISCREG_TLBI_VALE1_Xt:
187          case MISCREG_TLBI_VAALE1_Xt:
188          case MISCREG_TLBI_VMALLE1IS:
189          case MISCREG_TLBI_VAE1IS_Xt:
190          case MISCREG_TLBI_ASIDE1IS_Xt:
191          case MISCREG_TLBI_VAAE1IS_Xt:
192          case MISCREG_TLBI_VALE1IS_Xt:
193          case MISCREG_TLBI_VAALE1IS_Xt:
194            trap_to_hyp = hcr.ttlb && el == EL1;
195            break;
196          // Cache maintenance instructions to the point of unification
197          case MISCREG_IC_IVAU_Xt:
198          case MISCREG_ICIALLU:
199          case MISCREG_ICIALLUIS:
200          case MISCREG_DC_CVAU_Xt:
201            trap_to_hyp = hcr.tpu && el <= EL1;
202            break;
203          // Data/Unified cache maintenance instructions to the
204          // point of coherency
205          case MISCREG_DC_IVAC_Xt:
206          case MISCREG_DC_CIVAC_Xt:
207          case MISCREG_DC_CVAC_Xt:
208            trap_to_hyp = hcr.tpc && el <= EL1;
209            break;
210          // Data/Unified cache maintenance instructions by set/way
211          case MISCREG_DC_ISW_Xt:
212          case MISCREG_DC_CSW_Xt:
213          case MISCREG_DC_CISW_Xt:
214            trap_to_hyp = hcr.tsw && el == EL1;
215            break;
216          // ACTLR
217          case MISCREG_ACTLR_EL1:
218            trap_to_hyp = hcr.tacr && el == EL1;
219            break;
220
221          // @todo: Trap implementation-dependent functionality based on
222          // hcr.tidcp
223
224          // ID regs, group 3
225          case MISCREG_ID_PFR0_EL1:
226          case MISCREG_ID_PFR1_EL1:
227          case MISCREG_ID_DFR0_EL1:
228          case MISCREG_ID_AFR0_EL1:
229          case MISCREG_ID_MMFR0_EL1:
230          case MISCREG_ID_MMFR1_EL1:
231          case MISCREG_ID_MMFR2_EL1:
232          case MISCREG_ID_MMFR3_EL1:
233          case MISCREG_ID_ISAR0_EL1:
234          case MISCREG_ID_ISAR1_EL1:
235          case MISCREG_ID_ISAR2_EL1:
236          case MISCREG_ID_ISAR3_EL1:
237          case MISCREG_ID_ISAR4_EL1:
238          case MISCREG_ID_ISAR5_EL1:
239          case MISCREG_MVFR0_EL1:
240          case MISCREG_MVFR1_EL1:
241          case MISCREG_MVFR2_EL1:
242          case MISCREG_ID_AA64PFR0_EL1:
243          case MISCREG_ID_AA64PFR1_EL1:
244          case MISCREG_ID_AA64DFR0_EL1:
245          case MISCREG_ID_AA64DFR1_EL1:
246          case MISCREG_ID_AA64ISAR0_EL1:
247          case MISCREG_ID_AA64ISAR1_EL1:
248          case MISCREG_ID_AA64MMFR0_EL1:
249          case MISCREG_ID_AA64MMFR1_EL1:
250          case MISCREG_ID_AA64MMFR2_EL1:
251          case MISCREG_ID_AA64AFR0_EL1:
252          case MISCREG_ID_AA64AFR1_EL1:
253            assert(miscRead);
254            trap_to_hyp = hcr.tid3 && el == EL1;
255            break;
256          // ID regs, group 2
257          case MISCREG_CTR_EL0:
258          case MISCREG_CCSIDR_EL1:
259          case MISCREG_CLIDR_EL1:
260          case MISCREG_CSSELR_EL1:
261            trap_to_hyp = hcr.tid2 && el <= EL1;
262            break;
263          // ID regs, group 1
264          case MISCREG_AIDR_EL1:
265          case MISCREG_REVIDR_EL1:
266            assert(miscRead);
267            trap_to_hyp = hcr.tid1 && el == EL1;
268            break;
269          case MISCREG_IMPDEF_UNIMPL:
270            trap_to_hyp = hcr.tidcp && el == EL1;
271          default:
272            break;
273        }
274    }
275    return trap_to_hyp;
276}
277
278bool
279MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
280                          ExceptionLevel el, bool * is_vfp_neon) const
281{
282    const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
283
284    bool trap_to_mon = false;
285    *is_vfp_neon = false;
286
287    switch (misc_reg) {
288      // FP/SIMD regs
289      case MISCREG_FPCR:
290      case MISCREG_FPSR:
291      case MISCREG_FPEXC32_EL2:
292        trap_to_mon = cptr.tfp;
293        *is_vfp_neon = true;
294        break;
295      // CPACR, CPTR
296      case MISCREG_CPACR_EL1:
297        if (el == EL1 || el == EL2) {
298           trap_to_mon = cptr.tcpac;
299        }
300        break;
301      case MISCREG_CPTR_EL2:
302        if (el == EL2) {
303            trap_to_mon = cptr.tcpac;
304        }
305        break;
306      default:
307        break;
308    }
309    return trap_to_mon;
310}
311
312std::string
313MiscRegRegImmOp64::generateDisassembly(
314    Addr pc, const SymbolTable *symtab) const
315{
316    std::stringstream ss;
317    printMnemonic(ss);
318    printMiscReg(ss, dest);
319    ss << ", ";
320    printIntReg(ss, op1);
321    return ss.str();
322}
323
324std::string
325RegMiscRegImmOp64::generateDisassembly(
326    Addr pc, const SymbolTable *symtab) const
327{
328    std::stringstream ss;
329    printMnemonic(ss);
330    printIntReg(ss, dest);
331    ss << ", ";
332    printMiscReg(ss, op1);
333    return ss.str();
334}
335
336Fault
337MiscRegImplDefined64::execute(ExecContext *xc,
338                              Trace::InstRecord *traceData) const
339{
340    auto tc = xc->tcBase();
341    const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
342    const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
343
344    Fault fault = trap(tc, miscReg, el, imm);
345
346    if (fault != NoFault) {
347        return fault;
348
349    } else if (warning) {
350        warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str());
351        return NoFault;
352
353    } else {
354        return std::make_shared<UndefinedInstruction>(machInst, false,
355                                                      mnemonic);
356    }
357}
358
359std::string
360MiscRegImplDefined64::generateDisassembly(Addr pc,
361                                          const SymbolTable *symtab) const
362{
363    return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
364}
365