misc64.cc revision 12674
110037SARM gem5 Developers/* 212538Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2013,2017-2018 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Gabe Black 3810037SARM gem5 Developers */ 3910037SARM gem5 Developers 4010037SARM gem5 Developers#include "arch/arm/insts/misc64.hh" 4110037SARM gem5 Developers 4210037SARM gem5 Developersstd::string 4312538Sgiacomo.travaglini@arm.comImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 4412538Sgiacomo.travaglini@arm.com{ 4512538Sgiacomo.travaglini@arm.com std::stringstream ss; 4612538Sgiacomo.travaglini@arm.com printMnemonic(ss, "", false); 4712538Sgiacomo.travaglini@arm.com ccprintf(ss, "#0x%x", imm); 4812538Sgiacomo.travaglini@arm.com return ss.str(); 4912538Sgiacomo.travaglini@arm.com} 5012538Sgiacomo.travaglini@arm.com 5112538Sgiacomo.travaglini@arm.comstd::string 5210037SARM gem5 DevelopersRegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 5310037SARM gem5 Developers{ 5410037SARM gem5 Developers std::stringstream ss; 5510037SARM gem5 Developers printMnemonic(ss, "", false); 5612104Snathanael.premillieu@arm.com printIntReg(ss, dest); 5710037SARM gem5 Developers ss << ", "; 5812104Snathanael.premillieu@arm.com printIntReg(ss, op1); 5910037SARM gem5 Developers ccprintf(ss, ", #%d, #%d", imm1, imm2); 6010037SARM gem5 Developers return ss.str(); 6110037SARM gem5 Developers} 6210037SARM gem5 Developers 6310037SARM gem5 Developersstd::string 6410037SARM gem5 DevelopersRegRegRegImmOp64::generateDisassembly( 6512280Sgiacomo.travaglini@arm.com Addr pc, const SymbolTable *symtab) const 6610037SARM gem5 Developers{ 6710037SARM gem5 Developers std::stringstream ss; 6810037SARM gem5 Developers printMnemonic(ss, "", false); 6912104Snathanael.premillieu@arm.com printIntReg(ss, dest); 7010037SARM gem5 Developers ss << ", "; 7112104Snathanael.premillieu@arm.com printIntReg(ss, op1); 7210037SARM gem5 Developers ss << ", "; 7312104Snathanael.premillieu@arm.com printIntReg(ss, op2); 7410037SARM gem5 Developers ccprintf(ss, ", #%d", imm); 7510037SARM gem5 Developers return ss.str(); 7610037SARM gem5 Developers} 7710037SARM gem5 Developers 7810037SARM gem5 Developersstd::string 7910037SARM gem5 DevelopersUnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8010037SARM gem5 Developers{ 8112674Sgiacomo.travaglini@arm.com return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32)); 8210037SARM gem5 Developers} 8312280Sgiacomo.travaglini@arm.com 8412280Sgiacomo.travaglini@arm.comstd::string 8512280Sgiacomo.travaglini@arm.comMiscRegRegImmOp64::generateDisassembly( 8612280Sgiacomo.travaglini@arm.com Addr pc, const SymbolTable *symtab) const 8712280Sgiacomo.travaglini@arm.com{ 8812280Sgiacomo.travaglini@arm.com std::stringstream ss; 8912280Sgiacomo.travaglini@arm.com printMnemonic(ss); 9012280Sgiacomo.travaglini@arm.com printMiscReg(ss, dest); 9112280Sgiacomo.travaglini@arm.com ss << ", "; 9212280Sgiacomo.travaglini@arm.com printIntReg(ss, op1); 9312280Sgiacomo.travaglini@arm.com return ss.str(); 9412280Sgiacomo.travaglini@arm.com} 9512280Sgiacomo.travaglini@arm.com 9612280Sgiacomo.travaglini@arm.comstd::string 9712280Sgiacomo.travaglini@arm.comRegMiscRegImmOp64::generateDisassembly( 9812280Sgiacomo.travaglini@arm.com Addr pc, const SymbolTable *symtab) const 9912280Sgiacomo.travaglini@arm.com{ 10012280Sgiacomo.travaglini@arm.com std::stringstream ss; 10112280Sgiacomo.travaglini@arm.com printMnemonic(ss); 10212280Sgiacomo.travaglini@arm.com printIntReg(ss, dest); 10312280Sgiacomo.travaglini@arm.com ss << ", "; 10412280Sgiacomo.travaglini@arm.com printMiscReg(ss, op1); 10512280Sgiacomo.travaglini@arm.com return ss.str(); 10612280Sgiacomo.travaglini@arm.com} 107