misc.cc revision 7232
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/arm/insts/misc.hh" 41 42std::string 43MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 44{ 45 std::stringstream ss; 46 printMnemonic(ss); 47 printReg(ss, dest); 48 ss << ", "; 49 bool foundPsr = false; 50 for (unsigned i = 0; i < numSrcRegs(); i++) { 51 int idx = srcRegIdx(i); 52 if (idx < Ctrl_Base_DepTag) { 53 continue; 54 } 55 idx -= Ctrl_Base_DepTag; 56 if (idx == MISCREG_CPSR) { 57 ss << "cpsr"; 58 foundPsr = true; 59 break; 60 } 61 if (idx == MISCREG_SPSR) { 62 ss << "spsr"; 63 foundPsr = true; 64 break; 65 } 66 } 67 if (!foundPsr) { 68 ss << "????"; 69 } 70 return ss.str(); 71} 72 73void 74MsrBase::printMsrBase(std::ostream &os) const 75{ 76 printMnemonic(os); 77 bool apsr = false; 78 bool foundPsr = false; 79 for (unsigned i = 0; i < numDestRegs(); i++) { 80 int idx = destRegIdx(i); 81 if (idx < Ctrl_Base_DepTag) { 82 continue; 83 } 84 idx -= Ctrl_Base_DepTag; 85 if (idx == MISCREG_CPSR) { 86 os << "cpsr_"; 87 foundPsr = true; 88 break; 89 } 90 if (idx == MISCREG_SPSR) { 91 if (bits(byteMask, 1, 0)) { 92 os << "spsr_"; 93 } else { 94 os << "apsr_"; 95 apsr = true; 96 } 97 foundPsr = true; 98 break; 99 } 100 } 101 if (!foundPsr) { 102 os << "????"; 103 return; 104 } 105 if (bits(byteMask, 3)) { 106 if (apsr) { 107 os << "nzcvq"; 108 } else { 109 os << "f"; 110 } 111 } 112 if (bits(byteMask, 2)) { 113 if (apsr) { 114 os << "g"; 115 } else { 116 os << "s"; 117 } 118 } 119 if (bits(byteMask, 1)) { 120 os << "x"; 121 } 122 if (bits(byteMask, 0)) { 123 os << "c"; 124 } 125} 126 127std::string 128MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 129{ 130 std::stringstream ss; 131 printMsrBase(ss); 132 ccprintf(ss, ", #%#x", imm); 133 return ss.str(); 134} 135 136std::string 137MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 138{ 139 std::stringstream ss; 140 printMsrBase(ss); 141 ss << ", "; 142 printReg(ss, op1); 143 return ss.str(); 144} 145 146std::string 147RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 148{ 149 std::stringstream ss; 150 printMnemonic(ss); 151 printReg(ss, dest); 152 ss << ", "; 153 printReg(ss, op1); 154 return ss.str(); 155} 156 157std::string 158RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 159{ 160 std::stringstream ss; 161 printMnemonic(ss); 162 printReg(ss, dest); 163 ccprintf(ss, ", #%d, ", imm); 164 printReg(ss, op1); 165 return ss.str(); 166} 167 168std::string 169RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 170{ 171 std::stringstream ss; 172 printMnemonic(ss); 173 printReg(ss, dest); 174 ccprintf(ss, ", #%d, ", imm); 175 printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType); 176 printReg(ss, op1); 177 return ss.str(); 178} 179