misc.cc revision 7409 
14604Sgblack@eecs.umich.edu/*
24604Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited
34604Sgblack@eecs.umich.edu * All rights reserved
44604Sgblack@eecs.umich.edu *
57087Snate@binkert.org * The license below extends only to copyright in the software and shall
67087Snate@binkert.org * not be construed as granting a license to any other intellectual
77087Snate@binkert.org * property including but not limited to intellectual property relating
87087Snate@binkert.org * to a hardware implementation of the functionality of the software
97087Snate@binkert.org * licensed hereunder.  You may use the software subject to the license
107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated
117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software,
127087Snate@binkert.org * modified or unmodified, in source code or in binary form.
134604Sgblack@eecs.umich.edu *
147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without
157087Snate@binkert.org * modification, are permitted provided that the following conditions are
167087Snate@binkert.org * met: redistributions of source code must retain the above copyright
177087Snate@binkert.org * notice, this list of conditions and the following disclaimer;
187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright
197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the
207087Snate@binkert.org * documentation and/or other materials provided with the distribution;
217087Snate@binkert.org * neither the name of the copyright holders nor the names of its
224604Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
237087Snate@binkert.org * this software without specific prior written permission.
244604Sgblack@eecs.umich.edu *
254604Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
264604Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
274604Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
284604Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
294604Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
304604Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
314604Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
324604Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
334604Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
344604Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
354604Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
364604Sgblack@eecs.umich.edu *
374604Sgblack@eecs.umich.edu * Authors: Gabe Black
384604Sgblack@eecs.umich.edu */
394604Sgblack@eecs.umich.edu
404604Sgblack@eecs.umich.edu#include "arch/arm/insts/misc.hh"
414604Sgblack@eecs.umich.edu
424604Sgblack@eecs.umich.edustd::string
437629Sgblack@eecs.umich.eduMrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
447629Sgblack@eecs.umich.edu{
458229Snate@binkert.org    std::stringstream ss;
464604Sgblack@eecs.umich.edu    printMnemonic(ss);
474604Sgblack@eecs.umich.edu    printReg(ss, dest);
484604Sgblack@eecs.umich.edu    ss << ", ";
494604Sgblack@eecs.umich.edu    bool foundPsr = false;
504604Sgblack@eecs.umich.edu    for (unsigned i = 0; i < numSrcRegs(); i++) {
514604Sgblack@eecs.umich.edu        int idx = srcRegIdx(i);
524604Sgblack@eecs.umich.edu        if (idx < Ctrl_Base_DepTag) {
534604Sgblack@eecs.umich.edu            continue;
544863Sgblack@eecs.umich.edu        }
554604Sgblack@eecs.umich.edu        idx -= Ctrl_Base_DepTag;
564604Sgblack@eecs.umich.edu        if (idx == MISCREG_CPSR) {
574604Sgblack@eecs.umich.edu            ss << "cpsr";
584604Sgblack@eecs.umich.edu            foundPsr = true;
594604Sgblack@eecs.umich.edu            break;
604604Sgblack@eecs.umich.edu        }
614604Sgblack@eecs.umich.edu        if (idx == MISCREG_SPSR) {
624604Sgblack@eecs.umich.edu            ss << "spsr";
634604Sgblack@eecs.umich.edu            foundPsr = true;
644863Sgblack@eecs.umich.edu            break;
654604Sgblack@eecs.umich.edu        }
664604Sgblack@eecs.umich.edu    }
674604Sgblack@eecs.umich.edu    if (!foundPsr) {
684604Sgblack@eecs.umich.edu        ss << "????";
694604Sgblack@eecs.umich.edu    }
704604Sgblack@eecs.umich.edu    return ss.str();
714604Sgblack@eecs.umich.edu}
725966Sgblack@eecs.umich.edu
734604Sgblack@eecs.umich.eduvoid
748902Sandreas.hansson@arm.comMsrBase::printMsrBase(std::ostream &os) const
754604Sgblack@eecs.umich.edu{
764604Sgblack@eecs.umich.edu    printMnemonic(os);
77    bool apsr = false;
78    bool foundPsr = false;
79    for (unsigned i = 0; i < numDestRegs(); i++) {
80        int idx = destRegIdx(i);
81        if (idx < Ctrl_Base_DepTag) {
82            continue;
83        }
84        idx -= Ctrl_Base_DepTag;
85        if (idx == MISCREG_CPSR) {
86            os << "cpsr_";
87            foundPsr = true;
88            break;
89        }
90        if (idx == MISCREG_SPSR) {
91            if (bits(byteMask, 1, 0)) {
92                os << "spsr_";
93            } else {
94                os << "apsr_";
95                apsr = true;
96            }
97            foundPsr = true;
98            break;
99        }
100    }
101    if (!foundPsr) {
102        os << "????";
103        return;
104    }
105    if (bits(byteMask, 3)) {
106        if (apsr) {
107            os << "nzcvq";
108        } else {
109            os << "f";
110        }
111    }
112    if (bits(byteMask, 2)) {
113        if (apsr) {
114            os << "g";
115        } else {
116            os << "s";
117        }
118    }
119    if (bits(byteMask, 1)) {
120        os << "x";
121    }
122    if (bits(byteMask, 0)) {
123        os << "c";
124    }
125}
126
127std::string
128MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
129{
130    std::stringstream ss;
131    printMsrBase(ss);
132    ccprintf(ss, ", #%#x", imm);
133    return ss.str();
134}
135
136std::string
137MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
138{
139    std::stringstream ss;
140    printMsrBase(ss);
141    ss << ", ";
142    printReg(ss, op1);
143    return ss.str();
144}
145
146std::string
147ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
148{
149    std::stringstream ss;
150    printMnemonic(ss);
151    ccprintf(ss, "#%d", imm);
152    return ss.str();
153}
154
155std::string
156RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
157{
158    std::stringstream ss;
159    printMnemonic(ss);
160    printReg(ss, dest);
161    ccprintf(ss, ", #%d", imm);
162    return ss.str();
163}
164
165std::string
166RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
167{
168    std::stringstream ss;
169    printMnemonic(ss);
170    printReg(ss, dest);
171    ss << ", ";
172    printReg(ss, op1);
173    return ss.str();
174}
175
176std::string
177RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
178{
179    std::stringstream ss;
180    printMnemonic(ss);
181    printReg(ss, dest);
182    ss << ", ";
183    printReg(ss, op1);
184    ss << ", ";
185    printReg(ss, op2);
186    ccprintf(ss, ", #%d", imm);
187    return ss.str();
188}
189
190std::string
191RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
192{
193    std::stringstream ss;
194    printMnemonic(ss);
195    printReg(ss, dest);
196    ss << ", ";
197    printReg(ss, op1);
198    ss << ", ";
199    printReg(ss, op2);
200    ss << ", ";
201    printReg(ss, op3);
202    return ss.str();
203}
204
205std::string
206RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
207{
208    std::stringstream ss;
209    printMnemonic(ss);
210    printReg(ss, dest);
211    ss << ", ";
212    printReg(ss, op1);
213    ss << ", ";
214    printReg(ss, op2);
215    return ss.str();
216}
217
218std::string
219RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
220{
221    std::stringstream ss;
222    printMnemonic(ss);
223    printReg(ss, dest);
224    ss << ", ";
225    printReg(ss, op1);
226    ccprintf(ss, ", #%d", imm);
227    return ss.str();
228}
229
230std::string
231RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
232{
233    std::stringstream ss;
234    printMnemonic(ss);
235    printReg(ss, dest);
236    ss << ", ";
237    printReg(ss, op1);
238    ccprintf(ss, ", #%d, #%d", imm1, imm2);
239    return ss.str();
240}
241
242std::string
243RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
244{
245    std::stringstream ss;
246    printMnemonic(ss);
247    printReg(ss, dest);
248    ccprintf(ss, ", #%d, ", imm);
249    printReg(ss, op1);
250    return ss.str();
251}
252
253std::string
254RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
255{
256    std::stringstream ss;
257    printMnemonic(ss);
258    printReg(ss, dest);
259    ccprintf(ss, ", #%d, ", imm);
260    printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
261    printReg(ss, op1);
262    return ss.str();
263}
264
265std::string
266UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
267{
268    return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
269                    "unknown", machInst, machInst.opcode,
270                    inst2string(machInst));
271}
272