faults.cc revision 13895
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include "arch/arm/faults.hh" 4811793Sbrandon.potter@amd.com 4911793Sbrandon.potter@amd.com#include "arch/arm/insts/static_inst.hh" 5010037SARM gem5 Developers#include "arch/arm/system.hh" 5110037SARM gem5 Developers#include "arch/arm/utility.hh" 5210037SARM gem5 Developers#include "base/compiler.hh" 538229Snate@binkert.org#include "base/trace.hh" 548229Snate@binkert.org#include "cpu/base.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 568232Snate@binkert.org#include "debug/Faults.hh" 578782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 616019Shines@cs.fsu.edu 6210037SARM gem5 Developersuint8_t ArmFault::shortDescFaultSources[] = { 6310037SARM gem5 Developers 0x01, // AlignmentFault 6410037SARM gem5 Developers 0x04, // InstructionCacheMaintenance 6510037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 6610037SARM gem5 Developers 0x0c, // SynchExtAbtOnTranslTableWalkL1 6710037SARM gem5 Developers 0x0e, // SynchExtAbtOnTranslTableWalkL2 6810037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 6910037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 7010037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL1 7110037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 7210037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 7310037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 7410037SARM gem5 Developers 0x05, // TranslationL1 7510037SARM gem5 Developers 0x07, // TranslationL2 7610037SARM gem5 Developers 0xff, // TranslationL3 (INVALID) 7710037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 7810037SARM gem5 Developers 0x03, // AccessFlagL1 7910037SARM gem5 Developers 0x06, // AccessFlagL2 8010037SARM gem5 Developers 0xff, // AccessFlagL3 (INVALID) 8110037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 8210037SARM gem5 Developers 0x09, // DomainL1 8310037SARM gem5 Developers 0x0b, // DomainL2 8410037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 8510037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 8610037SARM gem5 Developers 0x0d, // PermissionL1 8710037SARM gem5 Developers 0x0f, // PermissionL2 8810037SARM gem5 Developers 0xff, // PermissionL3 (INVALID) 8910037SARM gem5 Developers 0x02, // DebugEvent 9010037SARM gem5 Developers 0x08, // SynchronousExternalAbort 9110037SARM gem5 Developers 0x10, // TLBConflictAbort 9210037SARM gem5 Developers 0x19, // SynchPtyErrOnMemoryAccess 9310037SARM gem5 Developers 0x16, // AsynchronousExternalAbort 9410037SARM gem5 Developers 0x18, // AsynchPtyErrOnMemoryAccess 9510037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 9610037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 9710037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 9810037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 9910037SARM gem5 Developers 0x40, // PrefetchTLBMiss 10010037SARM gem5 Developers 0x80 // PrefetchUncacheable 10110037SARM gem5 Developers}; 1026019Shines@cs.fsu.edu 10310037SARM gem5 Developersstatic_assert(sizeof(ArmFault::shortDescFaultSources) == 10410037SARM gem5 Developers ArmFault::NumFaultSources, 10510037SARM gem5 Developers "Invalid size of ArmFault::shortDescFaultSources[]"); 1066019Shines@cs.fsu.edu 10710037SARM gem5 Developersuint8_t ArmFault::longDescFaultSources[] = { 10810037SARM gem5 Developers 0x21, // AlignmentFault 10910037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 11010037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 11110037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 11210037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 11310037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 11410037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 11510037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 11610037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 11710037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 11810037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 11910037SARM gem5 Developers 0x05, // TranslationL1 12010037SARM gem5 Developers 0x06, // TranslationL2 12110037SARM gem5 Developers 0x07, // TranslationL3 12210037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 12310037SARM gem5 Developers 0x09, // AccessFlagL1 12410037SARM gem5 Developers 0x0a, // AccessFlagL2 12510037SARM gem5 Developers 0x0b, // AccessFlagL3 12610037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 12710037SARM gem5 Developers 0x3d, // DomainL1 12810037SARM gem5 Developers 0x3e, // DomainL2 12910037SARM gem5 Developers 0xff, // DomainL3 (RESERVED) 13010037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 13110037SARM gem5 Developers 0x0d, // PermissionL1 13210037SARM gem5 Developers 0x0e, // PermissionL2 13310037SARM gem5 Developers 0x0f, // PermissionL3 13410037SARM gem5 Developers 0x22, // DebugEvent 13510037SARM gem5 Developers 0x10, // SynchronousExternalAbort 13610037SARM gem5 Developers 0x30, // TLBConflictAbort 13710037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 13810037SARM gem5 Developers 0x11, // AsynchronousExternalAbort 13910037SARM gem5 Developers 0x19, // AsynchPtyErrOnMemoryAccess 14010037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 14110037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 14210037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 14310037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 14410037SARM gem5 Developers 0x40, // PrefetchTLBMiss 14510037SARM gem5 Developers 0x80 // PrefetchUncacheable 14610037SARM gem5 Developers}; 1476019Shines@cs.fsu.edu 14810037SARM gem5 Developersstatic_assert(sizeof(ArmFault::longDescFaultSources) == 14910037SARM gem5 Developers ArmFault::NumFaultSources, 15010037SARM gem5 Developers "Invalid size of ArmFault::longDescFaultSources[]"); 1516019Shines@cs.fsu.edu 15210037SARM gem5 Developersuint8_t ArmFault::aarch64FaultSources[] = { 15310037SARM gem5 Developers 0x21, // AlignmentFault 15410037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 15510037SARM gem5 Developers 0x14, // SynchExtAbtOnTranslTableWalkL0 15610037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 15710037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 15810037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 15910037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL0 16010037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 16110037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 16210037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 16310037SARM gem5 Developers 0x04, // TranslationL0 16410037SARM gem5 Developers 0x05, // TranslationL1 16510037SARM gem5 Developers 0x06, // TranslationL2 16610037SARM gem5 Developers 0x07, // TranslationL3 16710037SARM gem5 Developers 0x08, // AccessFlagL0 16810037SARM gem5 Developers 0x09, // AccessFlagL1 16910037SARM gem5 Developers 0x0a, // AccessFlagL2 17010037SARM gem5 Developers 0x0b, // AccessFlagL3 17110037SARM gem5 Developers // @todo: Section & Page Domain Fault in AArch64? 17210037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 17310037SARM gem5 Developers 0xff, // DomainL1 (INVALID) 17410037SARM gem5 Developers 0xff, // DomainL2 (INVALID) 17510037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 17610037SARM gem5 Developers 0x0c, // PermissionL0 17710037SARM gem5 Developers 0x0d, // PermissionL1 17810037SARM gem5 Developers 0x0e, // PermissionL2 17910037SARM gem5 Developers 0x0f, // PermissionL3 18012571Sgiacomo.travaglini@arm.com 0x22, // DebugEvent 18110037SARM gem5 Developers 0x10, // SynchronousExternalAbort 18210037SARM gem5 Developers 0x30, // TLBConflictAbort 18310037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 18410037SARM gem5 Developers 0xff, // AsynchronousExternalAbort (INVALID) 18510037SARM gem5 Developers 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 18610037SARM gem5 Developers 0x00, // AddressSizeL0 18710037SARM gem5 Developers 0x01, // AddressSizeL1 18810037SARM gem5 Developers 0x02, // AddressSizeL2 18910037SARM gem5 Developers 0x03, // AddressSizeL3 19010037SARM gem5 Developers 0x40, // PrefetchTLBMiss 19110037SARM gem5 Developers 0x80 // PrefetchUncacheable 19210037SARM gem5 Developers}; 1936019Shines@cs.fsu.edu 19410037SARM gem5 Developersstatic_assert(sizeof(ArmFault::aarch64FaultSources) == 19510037SARM gem5 Developers ArmFault::NumFaultSources, 19610037SARM gem5 Developers "Invalid size of ArmFault::aarch64FaultSources[]"); 1976019Shines@cs.fsu.edu 19810037SARM gem5 Developers// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 19910037SARM gem5 Developers// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 20010037SARM gem5 Developers// {A, F} disable, class, stat 20112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals( 20210037SARM gem5 Developers // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 20310037SARM gem5 Developers // location in AArch64) 20410037SARM gem5 Developers "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 20512517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_UNKNOWN 20612517Srekai.gonzalezalberquilla@arm.com); 20712517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals( 20810037SARM gem5 Developers "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 20912517Srekai.gonzalezalberquilla@arm.com 4, 2, 0, 0, true, false, false, EC_UNKNOWN 21012517Srekai.gonzalezalberquilla@arm.com); 21112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals( 21210037SARM gem5 Developers "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 21312517Srekai.gonzalezalberquilla@arm.com 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP 21412517Srekai.gonzalezalberquilla@arm.com); 21512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals( 21610037SARM gem5 Developers "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 21712517Srekai.gonzalezalberquilla@arm.com 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP 21812517Srekai.gonzalezalberquilla@arm.com); 21912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals( 22010037SARM gem5 Developers "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 22112517Srekai.gonzalezalberquilla@arm.com 4, 4, 4, 4, true, false, false, EC_HVC 22212517Srekai.gonzalezalberquilla@arm.com); 22312517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals( 22410037SARM gem5 Developers "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22512517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP 22612517Srekai.gonzalezalberquilla@arm.com); 22712517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals( 22810037SARM gem5 Developers "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22912517Srekai.gonzalezalberquilla@arm.com 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP 23012517Srekai.gonzalezalberquilla@arm.com); 23112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals( 23210037SARM gem5 Developers "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 23312517Srekai.gonzalezalberquilla@arm.com 8, 8, 0, 0, true, true, false, EC_INVALID 23412517Srekai.gonzalezalberquilla@arm.com); 23512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals( 23610037SARM gem5 Developers // @todo: double check these values 23710037SARM gem5 Developers "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 23812517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, false, false, EC_UNKNOWN 23912517Srekai.gonzalezalberquilla@arm.com); 24012517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals( 24112512Sgiacomo.travaglini@arm.com "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 24212517Srekai.gonzalezalberquilla@arm.com 4, 2, 0, 0, false, false, false, EC_UNKNOWN 24312517Srekai.gonzalezalberquilla@arm.com); 24412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals( 24510037SARM gem5 Developers "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 24612517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, false, EC_UNKNOWN 24712517Srekai.gonzalezalberquilla@arm.com); 24812517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals( 24910037SARM gem5 Developers "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 25012517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, false, EC_INVALID 25112517Srekai.gonzalezalberquilla@arm.com); 25212517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals( 25310037SARM gem5 Developers "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25412517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, true, EC_UNKNOWN 25512517Srekai.gonzalezalberquilla@arm.com); 25612517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals( 25710037SARM gem5 Developers "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25812517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, true, EC_INVALID 25912517Srekai.gonzalezalberquilla@arm.com); 26012764Sgiacomo.travaglini@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals( 26112764Sgiacomo.travaglini@arm.com "Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 26212764Sgiacomo.travaglini@arm.com 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST 26312764Sgiacomo.travaglini@arm.com); 26412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals( 26510037SARM gem5 Developers // Some dummy values (SupervisorTrap is AArch64-only) 26610037SARM gem5 Developers "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 26712517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, false, false, EC_UNKNOWN 26812517Srekai.gonzalezalberquilla@arm.com); 26912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals( 27010037SARM gem5 Developers // Some dummy values (PCAlignmentFault is AArch64-only) 27110037SARM gem5 Developers "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 27212517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT 27312517Srekai.gonzalezalberquilla@arm.com); 27412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals( 27510037SARM gem5 Developers // Some dummy values (SPAlignmentFault is AArch64-only) 27610037SARM gem5 Developers "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 27712517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT 27812517Srekai.gonzalezalberquilla@arm.com); 27912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals( 28010037SARM gem5 Developers // Some dummy values (SError is AArch64-only) 28110037SARM gem5 Developers "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 28212517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_SERROR 28312517Srekai.gonzalezalberquilla@arm.com); 28412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals( 28512299Sandreas.sandberg@arm.com // Some dummy values (SoftwareBreakpoint is AArch64-only) 28612299Sandreas.sandberg@arm.com "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 28712517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT 28812517Srekai.gonzalezalberquilla@arm.com); 28912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals( 29010037SARM gem5 Developers // Some dummy values 29110037SARM gem5 Developers "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 29212517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_UNKNOWN 29312517Srekai.gonzalezalberquilla@arm.com); 2946019Shines@cs.fsu.edu 29510037SARM gem5 DevelopersAddr 2967362Sgblack@eecs.umich.eduArmFault::getVector(ThreadContext *tc) 2976735Sgblack@eecs.umich.edu{ 29810037SARM gem5 Developers Addr base; 2996019Shines@cs.fsu.edu 30010037SARM gem5 Developers // Check for invalid modes 30110037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 30213396Sgiacomo.travaglini@arm.com assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON); 30310037SARM gem5 Developers assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 3047400SAli.Saidi@ARM.com 30510037SARM gem5 Developers switch (cpsr.mode) 30610037SARM gem5 Developers { 30710037SARM gem5 Developers case MODE_MON: 30810037SARM gem5 Developers base = tc->readMiscReg(MISCREG_MVBAR); 30910037SARM gem5 Developers break; 31010037SARM gem5 Developers case MODE_HYP: 31110037SARM gem5 Developers base = tc->readMiscReg(MISCREG_HVBAR); 31210037SARM gem5 Developers break; 31310037SARM gem5 Developers default: 31413394Sgiacomo.travaglini@arm.com SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 31510037SARM gem5 Developers if (sctlr.v) { 31610037SARM gem5 Developers base = HighVecs; 31710037SARM gem5 Developers } else { 31813396Sgiacomo.travaglini@arm.com base = ArmSystem::haveSecurity(tc) ? 31913396Sgiacomo.travaglini@arm.com tc->readMiscReg(MISCREG_VBAR) : 0; 32010037SARM gem5 Developers } 32110037SARM gem5 Developers break; 32210037SARM gem5 Developers } 32313396Sgiacomo.travaglini@arm.com 32410037SARM gem5 Developers return base + offset(tc); 3256019Shines@cs.fsu.edu} 3266019Shines@cs.fsu.edu 32710037SARM gem5 DevelopersAddr 32810037SARM gem5 DevelopersArmFault::getVector64(ThreadContext *tc) 32910037SARM gem5 Developers{ 33010037SARM gem5 Developers Addr vbar; 33110037SARM gem5 Developers switch (toEL) { 33210037SARM gem5 Developers case EL3: 33310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 33410037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 33510037SARM gem5 Developers break; 33611574SCurtis.Dunham@arm.com case EL2: 33711574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 33811574SCurtis.Dunham@arm.com vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 33911574SCurtis.Dunham@arm.com break; 34010037SARM gem5 Developers case EL1: 34110037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 34210037SARM gem5 Developers break; 34310037SARM gem5 Developers default: 34410037SARM gem5 Developers panic("Invalid target exception level"); 34510037SARM gem5 Developers break; 34610037SARM gem5 Developers } 34712511Schuan.zhu@arm.com return vbar + offset64(tc); 34810037SARM gem5 Developers} 34910037SARM gem5 Developers 35010037SARM gem5 DevelopersMiscRegIndex 35110037SARM gem5 DevelopersArmFault::getSyndromeReg64() const 35210037SARM gem5 Developers{ 35310037SARM gem5 Developers switch (toEL) { 35410037SARM gem5 Developers case EL1: 35510037SARM gem5 Developers return MISCREG_ESR_EL1; 35610037SARM gem5 Developers case EL2: 35710037SARM gem5 Developers return MISCREG_ESR_EL2; 35810037SARM gem5 Developers case EL3: 35910037SARM gem5 Developers return MISCREG_ESR_EL3; 36010037SARM gem5 Developers default: 36110037SARM gem5 Developers panic("Invalid exception level"); 36210037SARM gem5 Developers break; 36310037SARM gem5 Developers } 36410037SARM gem5 Developers} 36510037SARM gem5 Developers 36610037SARM gem5 DevelopersMiscRegIndex 36710037SARM gem5 DevelopersArmFault::getFaultAddrReg64() const 36810037SARM gem5 Developers{ 36910037SARM gem5 Developers switch (toEL) { 37010037SARM gem5 Developers case EL1: 37110037SARM gem5 Developers return MISCREG_FAR_EL1; 37210037SARM gem5 Developers case EL2: 37310037SARM gem5 Developers return MISCREG_FAR_EL2; 37410037SARM gem5 Developers case EL3: 37510037SARM gem5 Developers return MISCREG_FAR_EL3; 37610037SARM gem5 Developers default: 37710037SARM gem5 Developers panic("Invalid exception level"); 37810037SARM gem5 Developers break; 37910037SARM gem5 Developers } 38010037SARM gem5 Developers} 38110037SARM gem5 Developers 38210037SARM gem5 Developersvoid 38310037SARM gem5 DevelopersArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 38410037SARM gem5 Developers{ 38510037SARM gem5 Developers uint32_t value; 38610037SARM gem5 Developers uint32_t exc_class = (uint32_t) ec(tc); 38710037SARM gem5 Developers uint32_t issVal = iss(); 38812402Sgiacomo.travaglini@arm.com 38910037SARM gem5 Developers assert(!from64 || ArmSystem::highestELIs64(tc)); 39010037SARM gem5 Developers 39110037SARM gem5 Developers value = exc_class << 26; 39210037SARM gem5 Developers 39310037SARM gem5 Developers // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 39410037SARM gem5 Developers // 0x25) for which the ISS information is not valid (ARMv7). 39510037SARM gem5 Developers // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 39610037SARM gem5 Developers // valid it is treated as RES1. 39710037SARM gem5 Developers if (to64) { 39810037SARM gem5 Developers value |= 1 << 25; 39910037SARM gem5 Developers } else if ((bits(exc_class, 5, 3) != 4) || 40010037SARM gem5 Developers (bits(exc_class, 2) && bits(issVal, 24))) { 40110037SARM gem5 Developers if (!machInst.thumb || machInst.bigThumb) 40210037SARM gem5 Developers value |= 1 << 25; 40310037SARM gem5 Developers } 40410037SARM gem5 Developers // Condition code valid for EC[5:4] nonzero 40510037SARM gem5 Developers if (!from64 && ((bits(exc_class, 5, 4) == 0) && 40610037SARM gem5 Developers (bits(exc_class, 3, 0) != 0))) { 40710037SARM gem5 Developers if (!machInst.thumb) { 40810037SARM gem5 Developers uint32_t cond; 40910037SARM gem5 Developers ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 41010037SARM gem5 Developers // If its on unconditional instruction report with a cond code of 41110037SARM gem5 Developers // 0xE, ie the unconditional code 41210037SARM gem5 Developers cond = (condCode == COND_UC) ? COND_AL : condCode; 41310037SARM gem5 Developers value |= cond << 20; 41410037SARM gem5 Developers value |= 1 << 24; 41510037SARM gem5 Developers } 41610037SARM gem5 Developers value |= bits(issVal, 19, 0); 41710037SARM gem5 Developers } else { 41810037SARM gem5 Developers value |= issVal; 41910037SARM gem5 Developers } 42010037SARM gem5 Developers tc->setMiscReg(syndrome_reg, value); 42110037SARM gem5 Developers} 42210037SARM gem5 Developers 42310037SARM gem5 Developersvoid 42412569Sgiacomo.travaglini@arm.comArmFault::update(ThreadContext *tc) 4256019Shines@cs.fsu.edu{ 42610037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 42710037SARM gem5 Developers 42812569Sgiacomo.travaglini@arm.com // Determine source exception level and mode 42912569Sgiacomo.travaglini@arm.com fromMode = (OperatingMode) (uint8_t) cpsr.mode; 43012569Sgiacomo.travaglini@arm.com fromEL = opModeToEL(fromMode); 43112569Sgiacomo.travaglini@arm.com if (opModeIs64(fromMode)) 43212569Sgiacomo.travaglini@arm.com from64 = true; 43310037SARM gem5 Developers 43412569Sgiacomo.travaglini@arm.com // Determine target exception level (aarch64) or target execution 43512569Sgiacomo.travaglini@arm.com // mode (aarch32). 43612569Sgiacomo.travaglini@arm.com if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) { 43712569Sgiacomo.travaglini@arm.com toMode = MODE_MON; 43812569Sgiacomo.travaglini@arm.com toEL = EL3; 43912569Sgiacomo.travaglini@arm.com } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) { 44012569Sgiacomo.travaglini@arm.com toMode = MODE_HYP; 44112569Sgiacomo.travaglini@arm.com toEL = EL2; 44212569Sgiacomo.travaglini@arm.com hypRouted = true; 44312569Sgiacomo.travaglini@arm.com } else { 44412569Sgiacomo.travaglini@arm.com toMode = nextMode(); 44512569Sgiacomo.travaglini@arm.com toEL = opModeToEL(toMode); 44612569Sgiacomo.travaglini@arm.com } 44712402Sgiacomo.travaglini@arm.com 44812569Sgiacomo.travaglini@arm.com if (fromEL > toEL) 44912569Sgiacomo.travaglini@arm.com toEL = fromEL; 45010037SARM gem5 Developers 45112569Sgiacomo.travaglini@arm.com to64 = ELIs64(tc, toEL); 45212569Sgiacomo.travaglini@arm.com 45312569Sgiacomo.travaglini@arm.com // The fault specific informations have been updated; it is 45412569Sgiacomo.travaglini@arm.com // now possible to use them inside the fault. 45512569Sgiacomo.travaglini@arm.com faultUpdated = true; 45612569Sgiacomo.travaglini@arm.com} 45712569Sgiacomo.travaglini@arm.com 45812569Sgiacomo.travaglini@arm.comvoid 45912569Sgiacomo.travaglini@arm.comArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 46012569Sgiacomo.travaglini@arm.com{ 46112569Sgiacomo.travaglini@arm.com 46212569Sgiacomo.travaglini@arm.com // Update fault state informations, like the starting mode (aarch32) 46312569Sgiacomo.travaglini@arm.com // or EL (aarch64) and the ending mode or EL. 46412569Sgiacomo.travaglini@arm.com // From the update function we are also evaluating if the fault must 46512569Sgiacomo.travaglini@arm.com // be handled in AArch64 mode (to64). 46612569Sgiacomo.travaglini@arm.com update(tc); 46712569Sgiacomo.travaglini@arm.com 46812569Sgiacomo.travaglini@arm.com if (to64) { 46912569Sgiacomo.travaglini@arm.com // Invoke exception handler in AArch64 state 47012569Sgiacomo.travaglini@arm.com invoke64(tc, inst); 47112569Sgiacomo.travaglini@arm.com return; 47210037SARM gem5 Developers } 47310037SARM gem5 Developers 47410037SARM gem5 Developers // ARMv7 (ARM ARM issue C B1.9) 47510037SARM gem5 Developers 47610037SARM gem5 Developers bool have_security = ArmSystem::haveSecurity(tc); 47710037SARM gem5 Developers 4786735Sgblack@eecs.umich.edu FaultBase::invoke(tc); 4798782Sgblack@eecs.umich.edu if (!FullSystem) 4808782Sgblack@eecs.umich.edu return; 4816735Sgblack@eecs.umich.edu countStat()++; 4826019Shines@cs.fsu.edu 4836735Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 48410037SARM gem5 Developers SCR scr = tc->readMiscReg(MISCREG_SCR); 4858303SAli.Saidi@ARM.com CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 48610338SCurtis.Dunham@arm.com saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 48710338SCurtis.Dunham@arm.com saved_cpsr.c = tc->readCCReg(CCREG_C); 48810338SCurtis.Dunham@arm.com saved_cpsr.v = tc->readCCReg(CCREG_V); 48910338SCurtis.Dunham@arm.com saved_cpsr.ge = tc->readCCReg(CCREG_GE); 4908303SAli.Saidi@ARM.com 4917720Sgblack@eecs.umich.edu Addr curPc M5_VAR_USED = tc->pcState().pc(); 4928205SAli.Saidi@ARM.com ITSTATE it = tc->pcState().itstate(); 4938205SAli.Saidi@ARM.com saved_cpsr.it2 = it.top6; 4948205SAli.Saidi@ARM.com saved_cpsr.it1 = it.bottom2; 4956735Sgblack@eecs.umich.edu 49610037SARM gem5 Developers // if we have a valid instruction then use it to annotate this fault with 49710037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 49810037SARM gem5 Developers // information 49910037SARM gem5 Developers if (inst) { 50012398Sgiacomo.travaglini@arm.com ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get()); 50110037SARM gem5 Developers armInst->annotateFault(this); 50210037SARM gem5 Developers } 50310037SARM gem5 Developers 50410037SARM gem5 Developers // Ensure Secure state if initially in Monitor mode 50510037SARM gem5 Developers if (have_security && saved_cpsr.mode == MODE_MON) { 50610037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 50710037SARM gem5 Developers if (scr.ns) { 50810037SARM gem5 Developers scr.ns = 0; 50910037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_SCR, scr); 51010037SARM gem5 Developers } 51110037SARM gem5 Developers } 51210037SARM gem5 Developers 51312569Sgiacomo.travaglini@arm.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 51412569Sgiacomo.travaglini@arm.com cpsr.mode = toMode; 51512569Sgiacomo.travaglini@arm.com 51610037SARM gem5 Developers // some bits are set differently if we have been routed to hyp mode 51710037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 51810037SARM gem5 Developers SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 51910037SARM gem5 Developers cpsr.t = hsctlr.te; 52010037SARM gem5 Developers cpsr.e = hsctlr.ee; 52110037SARM gem5 Developers if (!scr.ea) {cpsr.a = 1;} 52210037SARM gem5 Developers if (!scr.fiq) {cpsr.f = 1;} 52310037SARM gem5 Developers if (!scr.irq) {cpsr.i = 1;} 52410037SARM gem5 Developers } else if (cpsr.mode == MODE_MON) { 52510037SARM gem5 Developers // Special case handling when entering monitor mode 52610037SARM gem5 Developers cpsr.t = sctlr.te; 52710037SARM gem5 Developers cpsr.e = sctlr.ee; 52810037SARM gem5 Developers cpsr.a = 1; 52910037SARM gem5 Developers cpsr.f = 1; 53010037SARM gem5 Developers cpsr.i = 1; 53110037SARM gem5 Developers } else { 53210037SARM gem5 Developers cpsr.t = sctlr.te; 53310037SARM gem5 Developers cpsr.e = sctlr.ee; 53410037SARM gem5 Developers 53510037SARM gem5 Developers // The *Disable functions are virtual and different per fault 53610037SARM gem5 Developers cpsr.a = cpsr.a | abortDisable(tc); 53710037SARM gem5 Developers cpsr.f = cpsr.f | fiqDisable(tc); 53810037SARM gem5 Developers cpsr.i = 1; 53910037SARM gem5 Developers } 5406735Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 5416735Sgblack@eecs.umich.edu cpsr.j = 0; 5426735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 54310037SARM gem5 Developers 5448518Sgeoffrey.blake@arm.com // Make sure mailbox sets to one always 5458518Sgeoffrey.blake@arm.com tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 5466735Sgblack@eecs.umich.edu 54710037SARM gem5 Developers // Clear the exclusive monitor 54810037SARM gem5 Developers tc->setMiscReg(MISCREG_LOCKFLAG, 0); 54910037SARM gem5 Developers 55010037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 55110037SARM gem5 Developers tc->setMiscReg(MISCREG_ELR_HYP, curPc + 55210037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 55310037SARM gem5 Developers } else { 55410037SARM gem5 Developers tc->setIntReg(INTREG_LR, curPc + 55510037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 55610037SARM gem5 Developers } 55710037SARM gem5 Developers 55810037SARM gem5 Developers switch (cpsr.mode) { 5596735Sgblack@eecs.umich.edu case MODE_FIQ: 5606735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 5616735Sgblack@eecs.umich.edu break; 5626735Sgblack@eecs.umich.edu case MODE_IRQ: 5636735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 5646735Sgblack@eecs.umich.edu break; 5656735Sgblack@eecs.umich.edu case MODE_SVC: 5666735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 5676735Sgblack@eecs.umich.edu break; 56810037SARM gem5 Developers case MODE_MON: 56910037SARM gem5 Developers assert(have_security); 57010037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 5716735Sgblack@eecs.umich.edu break; 5726735Sgblack@eecs.umich.edu case MODE_ABORT: 5736735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 5746735Sgblack@eecs.umich.edu break; 57510037SARM gem5 Developers case MODE_UNDEFINED: 57610037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 57710037SARM gem5 Developers if (ec(tc) != EC_UNKNOWN) 57810037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 57910037SARM gem5 Developers break; 58010037SARM gem5 Developers case MODE_HYP: 58112589Snikos.nikoleris@arm.com assert(ArmSystem::haveVirtualization(tc)); 58210037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 58310037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 58410037SARM gem5 Developers break; 5856735Sgblack@eecs.umich.edu default: 5866735Sgblack@eecs.umich.edu panic("unknown Mode\n"); 5877093Sgblack@eecs.umich.edu } 5887093Sgblack@eecs.umich.edu 5897720Sgblack@eecs.umich.edu Addr newPc = getVector(tc); 5907585SAli.Saidi@arm.com DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 5917720Sgblack@eecs.umich.edu name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 5927720Sgblack@eecs.umich.edu PCState pc(newPc); 5937720Sgblack@eecs.umich.edu pc.thumb(cpsr.t); 5947720Sgblack@eecs.umich.edu pc.nextThumb(pc.thumb()); 5957720Sgblack@eecs.umich.edu pc.jazelle(cpsr.j); 5967720Sgblack@eecs.umich.edu pc.nextJazelle(pc.jazelle()); 59710037SARM gem5 Developers pc.aarch64(!cpsr.width); 59810037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 59912763Sgiacomo.travaglini@arm.com pc.illegalExec(false); 6007720Sgblack@eecs.umich.edu tc->pcState(pc); 6016019Shines@cs.fsu.edu} 6027189Sgblack@eecs.umich.edu 6037400SAli.Saidi@ARM.comvoid 60410417Sandreas.hansson@arm.comArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 60510037SARM gem5 Developers{ 60610037SARM gem5 Developers // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 60710037SARM gem5 Developers MiscRegIndex elr_idx, spsr_idx; 60810037SARM gem5 Developers switch (toEL) { 60910037SARM gem5 Developers case EL1: 61010037SARM gem5 Developers elr_idx = MISCREG_ELR_EL1; 61110037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL1; 61210037SARM gem5 Developers break; 61311574SCurtis.Dunham@arm.com case EL2: 61411574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 61511574SCurtis.Dunham@arm.com elr_idx = MISCREG_ELR_EL2; 61611574SCurtis.Dunham@arm.com spsr_idx = MISCREG_SPSR_EL2; 61711574SCurtis.Dunham@arm.com break; 61810037SARM gem5 Developers case EL3: 61910037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 62010037SARM gem5 Developers elr_idx = MISCREG_ELR_EL3; 62110037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL3; 62210037SARM gem5 Developers break; 62310037SARM gem5 Developers default: 62410037SARM gem5 Developers panic("Invalid target exception level"); 62510037SARM gem5 Developers break; 62610037SARM gem5 Developers } 62710037SARM gem5 Developers 62810037SARM gem5 Developers // Save process state into SPSR_ELx 62910037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 63010037SARM gem5 Developers CPSR spsr = cpsr; 63110338SCurtis.Dunham@arm.com spsr.nz = tc->readCCReg(CCREG_NZ); 63210338SCurtis.Dunham@arm.com spsr.c = tc->readCCReg(CCREG_C); 63310338SCurtis.Dunham@arm.com spsr.v = tc->readCCReg(CCREG_V); 63410037SARM gem5 Developers if (from64) { 63510037SARM gem5 Developers // Force some bitfields to 0 63610037SARM gem5 Developers spsr.q = 0; 63710037SARM gem5 Developers spsr.it1 = 0; 63810037SARM gem5 Developers spsr.j = 0; 63910037SARM gem5 Developers spsr.res0_23_22 = 0; 64010037SARM gem5 Developers spsr.ge = 0; 64110037SARM gem5 Developers spsr.it2 = 0; 64210037SARM gem5 Developers spsr.t = 0; 64310037SARM gem5 Developers } else { 64410338SCurtis.Dunham@arm.com spsr.ge = tc->readCCReg(CCREG_GE); 64510037SARM gem5 Developers ITSTATE it = tc->pcState().itstate(); 64610037SARM gem5 Developers spsr.it2 = it.top6; 64710037SARM gem5 Developers spsr.it1 = it.bottom2; 64810037SARM gem5 Developers // Force some bitfields to 0 64910037SARM gem5 Developers spsr.res0_23_22 = 0; 65010037SARM gem5 Developers spsr.ss = 0; 65110037SARM gem5 Developers } 65210037SARM gem5 Developers tc->setMiscReg(spsr_idx, spsr); 65310037SARM gem5 Developers 65410037SARM gem5 Developers // Save preferred return address into ELR_ELx 65510037SARM gem5 Developers Addr curr_pc = tc->pcState().pc(); 65610037SARM gem5 Developers Addr ret_addr = curr_pc; 65710037SARM gem5 Developers if (from64) 65810037SARM gem5 Developers ret_addr += armPcElrOffset(); 65910037SARM gem5 Developers else 66010037SARM gem5 Developers ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 66110037SARM gem5 Developers tc->setMiscReg(elr_idx, ret_addr); 66210037SARM gem5 Developers 66312511Schuan.zhu@arm.com Addr vec_address = getVector64(tc); 66412511Schuan.zhu@arm.com 66510037SARM gem5 Developers // Update process state 66610037SARM gem5 Developers OperatingMode64 mode = 0; 66710037SARM gem5 Developers mode.spX = 1; 66810037SARM gem5 Developers mode.el = toEL; 66910037SARM gem5 Developers mode.width = 0; 67010037SARM gem5 Developers cpsr.mode = mode; 67110037SARM gem5 Developers cpsr.daif = 0xf; 67210037SARM gem5 Developers cpsr.il = 0; 67310037SARM gem5 Developers cpsr.ss = 0; 67410037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 67510037SARM gem5 Developers 67610037SARM gem5 Developers // Set PC to start of exception handler 67712511Schuan.zhu@arm.com Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL); 67810037SARM gem5 Developers DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 67910037SARM gem5 Developers "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); 68010037SARM gem5 Developers PCState pc(new_pc); 68110037SARM gem5 Developers pc.aarch64(!cpsr.width); 68210037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 68312763Sgiacomo.travaglini@arm.com pc.illegalExec(false); 68410037SARM gem5 Developers tc->pcState(pc); 68510037SARM gem5 Developers 68610037SARM gem5 Developers // If we have a valid instruction then use it to annotate this fault with 68710037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 68810037SARM gem5 Developers // information 68910037SARM gem5 Developers if (inst) 69012398Sgiacomo.travaglini@arm.com static_cast<ArmStaticInst *>(inst.get())->annotateFault(this); 69110037SARM gem5 Developers // Save exception syndrome 69210037SARM gem5 Developers if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 69310037SARM gem5 Developers setSyndrome(tc, getSyndromeReg64()); 69410037SARM gem5 Developers} 69510037SARM gem5 Developers 69613396Sgiacomo.travaglini@arm.comAddr 69713396Sgiacomo.travaglini@arm.comReset::getVector(ThreadContext *tc) 69813396Sgiacomo.travaglini@arm.com{ 69913396Sgiacomo.travaglini@arm.com Addr base; 70013396Sgiacomo.travaglini@arm.com 70113396Sgiacomo.travaglini@arm.com // Check for invalid modes 70213396Sgiacomo.travaglini@arm.com CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 70313396Sgiacomo.travaglini@arm.com assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON); 70413396Sgiacomo.travaglini@arm.com assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 70513396Sgiacomo.travaglini@arm.com 70613396Sgiacomo.travaglini@arm.com // RVBAR is aliased (implemented as) MVBAR in gem5, since the two 70713396Sgiacomo.travaglini@arm.com // are mutually exclusive; there is no need to check here for 70813396Sgiacomo.travaglini@arm.com // which register to use since they hold the same value 70913396Sgiacomo.travaglini@arm.com base = tc->readMiscReg(MISCREG_MVBAR); 71013396Sgiacomo.travaglini@arm.com 71113396Sgiacomo.travaglini@arm.com return base + offset(tc); 71213396Sgiacomo.travaglini@arm.com} 71313396Sgiacomo.travaglini@arm.com 71410037SARM gem5 Developersvoid 71510417Sandreas.hansson@arm.comReset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7167400SAli.Saidi@ARM.com{ 7178782Sgblack@eecs.umich.edu if (FullSystem) { 71811150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupts(tc->threadId()); 7198782Sgblack@eecs.umich.edu tc->clearArchRegs(); 7208782Sgblack@eecs.umich.edu } 72110037SARM gem5 Developers if (!ArmSystem::highestELIs64(tc)) { 72210037SARM gem5 Developers ArmFault::invoke(tc, inst); 72310037SARM gem5 Developers tc->setMiscReg(MISCREG_VMPIDR, 72410037SARM gem5 Developers getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 72510037SARM gem5 Developers 72610037SARM gem5 Developers // Unless we have SMC code to get us there, boot in HYP! 72710037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc) && 72810037SARM gem5 Developers !ArmSystem::haveSecurity(tc)) { 72910037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 73010037SARM gem5 Developers cpsr.mode = MODE_HYP; 73110037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 73210037SARM gem5 Developers } 73310037SARM gem5 Developers } else { 73410037SARM gem5 Developers // Advance the PC to the IMPLEMENTATION DEFINED reset value 73513396Sgiacomo.travaglini@arm.com PCState pc = ArmSystem::resetAddr(tc); 73610037SARM gem5 Developers pc.aarch64(true); 73710037SARM gem5 Developers pc.nextAArch64(true); 73810037SARM gem5 Developers tc->pcState(pc); 73910037SARM gem5 Developers } 7407400SAli.Saidi@ARM.com} 7417400SAli.Saidi@ARM.com 7427189Sgblack@eecs.umich.eduvoid 74310417Sandreas.hansson@arm.comUndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7447189Sgblack@eecs.umich.edu{ 7458782Sgblack@eecs.umich.edu if (FullSystem) { 7468782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 7478806Sgblack@eecs.umich.edu return; 7488806Sgblack@eecs.umich.edu } 7498806Sgblack@eecs.umich.edu 7508806Sgblack@eecs.umich.edu // If the mnemonic isn't defined this has to be an unknown instruction. 7518806Sgblack@eecs.umich.edu assert(unknown || mnemonic != NULL); 75213895Sgiacomo.travaglini@arm.com auto arm_inst = static_cast<ArmStaticInst *>(inst.get()); 7538806Sgblack@eecs.umich.edu if (disabled) { 7548806Sgblack@eecs.umich.edu panic("Attempted to execute disabled instruction " 75513895Sgiacomo.travaglini@arm.com "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); 7568806Sgblack@eecs.umich.edu } else if (unknown) { 7578806Sgblack@eecs.umich.edu panic("Attempted to execute unknown instruction (inst 0x%08x)", 75813895Sgiacomo.travaglini@arm.com arm_inst->encoding()); 7597189Sgblack@eecs.umich.edu } else { 7608806Sgblack@eecs.umich.edu panic("Attempted to execute unimplemented instruction " 76113895Sgiacomo.travaglini@arm.com "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); 7627189Sgblack@eecs.umich.edu } 7637189Sgblack@eecs.umich.edu} 7647189Sgblack@eecs.umich.edu 76510037SARM gem5 Developersbool 76610037SARM gem5 DevelopersUndefinedInstruction::routeToHyp(ThreadContext *tc) const 76710037SARM gem5 Developers{ 76810037SARM gem5 Developers bool toHyp; 76910037SARM gem5 Developers 77010037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 77110037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 77210037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 77310037SARM gem5 Developers 77410037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 77510037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 77610037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 77710037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 77810037SARM gem5 Developers return toHyp; 77910037SARM gem5 Developers} 78010037SARM gem5 Developers 78110037SARM gem5 Developersuint32_t 78210037SARM gem5 DevelopersUndefinedInstruction::iss() const 78310037SARM gem5 Developers{ 78412402Sgiacomo.travaglini@arm.com 78512402Sgiacomo.travaglini@arm.com // If UndefinedInstruction is routed to hypervisor, iss field is 0. 78612402Sgiacomo.travaglini@arm.com if (hypRouted) { 78712402Sgiacomo.travaglini@arm.com return 0; 78812402Sgiacomo.travaglini@arm.com } 78912402Sgiacomo.travaglini@arm.com 79010037SARM gem5 Developers if (overrideEc == EC_INVALID) 79110037SARM gem5 Developers return issRaw; 79210037SARM gem5 Developers 79310037SARM gem5 Developers uint32_t new_iss = 0; 79410037SARM gem5 Developers uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 79510037SARM gem5 Developers 79610037SARM gem5 Developers dir = bits(machInst, 21, 21); 79710037SARM gem5 Developers op0 = bits(machInst, 20, 19); 79810037SARM gem5 Developers op1 = bits(machInst, 18, 16); 79910037SARM gem5 Developers CRn = bits(machInst, 15, 12); 80010037SARM gem5 Developers CRm = bits(machInst, 11, 8); 80110037SARM gem5 Developers op2 = bits(machInst, 7, 5); 80210037SARM gem5 Developers Rt = bits(machInst, 4, 0); 80310037SARM gem5 Developers 80410037SARM gem5 Developers new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 80510037SARM gem5 Developers Rt << 5 | CRm << 1 | dir; 80610037SARM gem5 Developers 80710037SARM gem5 Developers return new_iss; 80810037SARM gem5 Developers} 80910037SARM gem5 Developers 8107197Sgblack@eecs.umich.eduvoid 81110417Sandreas.hansson@arm.comSupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 8127197Sgblack@eecs.umich.edu{ 8138782Sgblack@eecs.umich.edu if (FullSystem) { 8148782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 8158806Sgblack@eecs.umich.edu return; 8168806Sgblack@eecs.umich.edu } 8177197Sgblack@eecs.umich.edu 8188806Sgblack@eecs.umich.edu // As of now, there isn't a 32 bit thumb version of this instruction. 8198806Sgblack@eecs.umich.edu assert(!machInst.bigThumb); 8208806Sgblack@eecs.umich.edu uint32_t callNum; 82110037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 82210037SARM gem5 Developers OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 82310037SARM gem5 Developers if (opModeIs64(mode)) 82410037SARM gem5 Developers callNum = tc->readIntReg(INTREG_X8); 82510037SARM gem5 Developers else 82610037SARM gem5 Developers callNum = tc->readIntReg(INTREG_R7); 82711877Sbrandon.potter@amd.com Fault fault; 82811877Sbrandon.potter@amd.com tc->syscall(callNum, &fault); 8298806Sgblack@eecs.umich.edu 8308806Sgblack@eecs.umich.edu // Advance the PC since that won't happen automatically. 8318806Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 8328806Sgblack@eecs.umich.edu assert(inst); 8338806Sgblack@eecs.umich.edu inst->advancePC(pc); 8348806Sgblack@eecs.umich.edu tc->pcState(pc); 8357197Sgblack@eecs.umich.edu} 8367197Sgblack@eecs.umich.edu 83710037SARM gem5 Developersbool 83810037SARM gem5 DevelopersSupervisorCall::routeToHyp(ThreadContext *tc) const 83910037SARM gem5 Developers{ 84010037SARM gem5 Developers bool toHyp; 84110037SARM gem5 Developers 84210037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 84310037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 84410037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 84510037SARM gem5 Developers 84610037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 84710037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 84810037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 84910037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 85010037SARM gem5 Developers return toHyp; 85110037SARM gem5 Developers} 85210037SARM gem5 Developers 85310037SARM gem5 DevelopersExceptionClass 85410037SARM gem5 DevelopersSupervisorCall::ec(ThreadContext *tc) const 85510037SARM gem5 Developers{ 85610037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 85710037SARM gem5 Developers (from64 ? EC_SVC_64 : vals.ec); 85810037SARM gem5 Developers} 85910037SARM gem5 Developers 86010037SARM gem5 Developersuint32_t 86110037SARM gem5 DevelopersSupervisorCall::iss() const 86210037SARM gem5 Developers{ 86310037SARM gem5 Developers // Even if we have a 24 bit imm from an arm32 instruction then we only use 86410037SARM gem5 Developers // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 86510037SARM gem5 Developers return issRaw & 0xFFFF; 86610037SARM gem5 Developers} 86710037SARM gem5 Developers 86810037SARM gem5 Developersuint32_t 86910037SARM gem5 DevelopersSecureMonitorCall::iss() const 87010037SARM gem5 Developers{ 87110037SARM gem5 Developers if (from64) 87210037SARM gem5 Developers return bits(machInst, 20, 5); 87310037SARM gem5 Developers return 0; 87410037SARM gem5 Developers} 87510037SARM gem5 Developers 87610037SARM gem5 DevelopersExceptionClass 87710037SARM gem5 DevelopersUndefinedInstruction::ec(ThreadContext *tc) const 87810037SARM gem5 Developers{ 87912402Sgiacomo.travaglini@arm.com // If UndefinedInstruction is routed to hypervisor, 88012402Sgiacomo.travaglini@arm.com // HSR.EC field is 0. 88112402Sgiacomo.travaglini@arm.com if (hypRouted) 88212402Sgiacomo.travaglini@arm.com return EC_UNKNOWN; 88312402Sgiacomo.travaglini@arm.com else 88412402Sgiacomo.travaglini@arm.com return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 88510037SARM gem5 Developers} 88610037SARM gem5 Developers 88710037SARM gem5 Developers 88810037SARM gem5 DevelopersHypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 88910037SARM gem5 Developers ArmFaultVals<HypervisorCall>(_machInst, _imm) 89010037SARM gem5 Developers{} 89110037SARM gem5 Developers 89210037SARM gem5 DevelopersExceptionClass 89311576SDylan.Johnson@ARM.comHypervisorCall::ec(ThreadContext *tc) const 89411576SDylan.Johnson@ARM.com{ 89511576SDylan.Johnson@ARM.com return from64 ? EC_HVC_64 : vals.ec; 89611576SDylan.Johnson@ARM.com} 89711576SDylan.Johnson@ARM.com 89811576SDylan.Johnson@ARM.comExceptionClass 89910037SARM gem5 DevelopersHypervisorTrap::ec(ThreadContext *tc) const 90010037SARM gem5 Developers{ 90110037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 90210037SARM gem5 Developers} 90310037SARM gem5 Developers 90410037SARM gem5 Developerstemplate<class T> 90510037SARM gem5 DevelopersFaultOffset 90610037SARM gem5 DevelopersArmFaultVals<T>::offset(ThreadContext *tc) 90710037SARM gem5 Developers{ 90810037SARM gem5 Developers bool isHypTrap = false; 90910037SARM gem5 Developers 91010037SARM gem5 Developers // Normally we just use the exception vector from the table at the top if 91110037SARM gem5 Developers // this file, however if this exception has caused a transition to hype 91210037SARM gem5 Developers // mode, and its an exception type that would only do this if it has been 91310037SARM gem5 Developers // trapped then we use the hyp trap vector instead of the normal vector 91410037SARM gem5 Developers if (vals.hypTrappable) { 91510037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 91610037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 91710037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 91810037SARM gem5 Developers isHypTrap = spsr.mode != MODE_HYP; 91910037SARM gem5 Developers } 92010037SARM gem5 Developers } 92110037SARM gem5 Developers return isHypTrap ? 0x14 : vals.offset; 92210037SARM gem5 Developers} 92310037SARM gem5 Developers 92412511Schuan.zhu@arm.comtemplate<class T> 92512511Schuan.zhu@arm.comFaultOffset 92612511Schuan.zhu@arm.comArmFaultVals<T>::offset64(ThreadContext *tc) 92712511Schuan.zhu@arm.com{ 92812511Schuan.zhu@arm.com if (toEL == fromEL) { 92912511Schuan.zhu@arm.com if (opModeIsT(fromMode)) 93012511Schuan.zhu@arm.com return vals.currELTOffset; 93112511Schuan.zhu@arm.com return vals.currELHOffset; 93212511Schuan.zhu@arm.com } else { 93312511Schuan.zhu@arm.com bool lower_32 = false; 93412511Schuan.zhu@arm.com if (toEL == EL3) { 93512511Schuan.zhu@arm.com if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2)) 93612511Schuan.zhu@arm.com lower_32 = ELIs32(tc, EL2); 93712511Schuan.zhu@arm.com else 93812511Schuan.zhu@arm.com lower_32 = ELIs32(tc, EL1); 93912511Schuan.zhu@arm.com } else { 94012511Schuan.zhu@arm.com lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1)); 94112511Schuan.zhu@arm.com } 94212511Schuan.zhu@arm.com 94312511Schuan.zhu@arm.com if (lower_32) 94412511Schuan.zhu@arm.com return vals.lowerEL32Offset; 94512511Schuan.zhu@arm.com return vals.lowerEL64Offset; 94612511Schuan.zhu@arm.com } 94712511Schuan.zhu@arm.com} 94812511Schuan.zhu@arm.com 94910037SARM gem5 Developers// void 95010037SARM gem5 Developers// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 95110037SARM gem5 Developers// { 95210037SARM gem5 Developers// ESR esr = 0; 95310037SARM gem5 Developers// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 95410037SARM gem5 Developers// esr.il = !machInst.thumb; 95510037SARM gem5 Developers// if (machInst.aarch64) 95610037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 20, 5); 95710037SARM gem5 Developers// else if (machInst.thumb) 95810037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 7, 0); 95910037SARM gem5 Developers// else 96010037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 15, 0); 96110037SARM gem5 Developers// tc->setMiscReg(esr_idx, esr); 96210037SARM gem5 Developers// } 96310037SARM gem5 Developers 96410037SARM gem5 Developersvoid 96510417Sandreas.hansson@arm.comSecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 96610037SARM gem5 Developers{ 96710037SARM gem5 Developers if (FullSystem) { 96810037SARM gem5 Developers ArmFault::invoke(tc, inst); 96910037SARM gem5 Developers return; 97010037SARM gem5 Developers } 97110037SARM gem5 Developers} 97210037SARM gem5 Developers 97310037SARM gem5 DevelopersExceptionClass 97410037SARM gem5 DevelopersSecureMonitorCall::ec(ThreadContext *tc) const 97510037SARM gem5 Developers{ 97610037SARM gem5 Developers return (from64 ? EC_SMC_64 : vals.ec); 97710037SARM gem5 Developers} 97810037SARM gem5 Developers 97912509Schuan.zhu@arm.combool 98012509Schuan.zhu@arm.comSupervisorTrap::routeToHyp(ThreadContext *tc) const 98112509Schuan.zhu@arm.com{ 98212509Schuan.zhu@arm.com bool toHyp = false; 98312509Schuan.zhu@arm.com 98412509Schuan.zhu@arm.com SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 98512509Schuan.zhu@arm.com HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 98612509Schuan.zhu@arm.com CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 98712509Schuan.zhu@arm.com 98812509Schuan.zhu@arm.com // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 98912509Schuan.zhu@arm.com toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 99012509Schuan.zhu@arm.com return toHyp; 99112509Schuan.zhu@arm.com} 99212509Schuan.zhu@arm.com 99312509Schuan.zhu@arm.comuint32_t 99412509Schuan.zhu@arm.comSupervisorTrap::iss() const 99512509Schuan.zhu@arm.com{ 99612509Schuan.zhu@arm.com // If SupervisorTrap is routed to hypervisor, iss field is 0. 99712509Schuan.zhu@arm.com if (hypRouted) { 99812509Schuan.zhu@arm.com return 0; 99912509Schuan.zhu@arm.com } 100012509Schuan.zhu@arm.com return issRaw; 100112509Schuan.zhu@arm.com} 100212509Schuan.zhu@arm.com 100310037SARM gem5 DevelopersExceptionClass 100410037SARM gem5 DevelopersSupervisorTrap::ec(ThreadContext *tc) const 100510037SARM gem5 Developers{ 100612509Schuan.zhu@arm.com if (hypRouted) 100712509Schuan.zhu@arm.com return EC_UNKNOWN; 100812509Schuan.zhu@arm.com else 100912509Schuan.zhu@arm.com return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 101010037SARM gem5 Developers} 101110037SARM gem5 Developers 101210037SARM gem5 DevelopersExceptionClass 101310037SARM gem5 DevelopersSecureMonitorTrap::ec(ThreadContext *tc) const 101410037SARM gem5 Developers{ 101510037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 101610037SARM gem5 Developers (from64 ? EC_SMC_64 : vals.ec); 101710037SARM gem5 Developers} 101810037SARM gem5 Developers 10197362Sgblack@eecs.umich.edutemplate<class T> 10207362Sgblack@eecs.umich.eduvoid 102110417Sandreas.hansson@arm.comAbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 10227362Sgblack@eecs.umich.edu{ 102310037SARM gem5 Developers if (tranMethod == ArmFault::UnknownTran) { 102410037SARM gem5 Developers tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 102510037SARM gem5 Developers : ArmFault::VmsaTran; 102610037SARM gem5 Developers 102710037SARM gem5 Developers if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 102810037SARM gem5 Developers // See ARM ARM B3-1416 102910037SARM gem5 Developers bool override_LPAE = false; 103010037SARM gem5 Developers TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 103110037SARM gem5 Developers TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 103210037SARM gem5 Developers if (ttbcr_s.eae) { 103310037SARM gem5 Developers override_LPAE = true; 103410037SARM gem5 Developers } else { 103510037SARM gem5 Developers // Unimplemented code option, not seen in testing. May need 103610037SARM gem5 Developers // extension according to the manual exceprt above. 103710037SARM gem5 Developers DPRINTF(Faults, "Warning: Incomplete translation method " 103810037SARM gem5 Developers "override detected.\n"); 103910037SARM gem5 Developers } 104010037SARM gem5 Developers if (override_LPAE) 104110037SARM gem5 Developers tranMethod = ArmFault::LpaeTran; 104210037SARM gem5 Developers } 104310037SARM gem5 Developers } 104410037SARM gem5 Developers 104510037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 104611150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 104710037SARM gem5 Developers } 104810037SARM gem5 Developers // Get effective fault source encoding 104910037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 105010037SARM gem5 Developers 105110037SARM gem5 Developers // source must be determined BEFORE invoking generic routines which will 105210037SARM gem5 Developers // try to set hsr etc. and are based upon source! 10538205SAli.Saidi@ARM.com ArmFaultVals<T>::invoke(tc, inst); 105410037SARM gem5 Developers 105511496Sandreas.sandberg@arm.com if (!this->to64) { // AArch32 105612570Sgiacomo.travaglini@arm.com FSR fsr = getFsr(tc); 105710037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 105810037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, faultAddr); 105910037SARM gem5 Developers } else if (stage2) { 106010037SARM gem5 Developers tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 106110037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, OVAddr); 106210037SARM gem5 Developers } else { 106310037SARM gem5 Developers tc->setMiscReg(T::FsrIndex, fsr); 106410037SARM gem5 Developers tc->setMiscReg(T::FarIndex, faultAddr); 106510037SARM gem5 Developers } 106610037SARM gem5 Developers DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 106710037SARM gem5 Developers "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 106810037SARM gem5 Developers } else { // AArch64 106910037SARM gem5 Developers // Set the FAR register. Nothing else to do if we are in AArch64 state 107010037SARM gem5 Developers // because the syndrome register has already been set inside invoke64() 107111585SDylan.Johnson@ARM.com if (stage2) { 107211585SDylan.Johnson@ARM.com // stage 2 fault, set HPFAR_EL2 to the faulting IPA 107311585SDylan.Johnson@ARM.com // and FAR_EL2 to the Original VA 107411585SDylan.Johnson@ARM.com tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr); 107511585SDylan.Johnson@ARM.com tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4); 107611585SDylan.Johnson@ARM.com 107711585SDylan.Johnson@ARM.com DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n", 107811585SDylan.Johnson@ARM.com OVAddr, faultAddr); 107911585SDylan.Johnson@ARM.com } else { 108011585SDylan.Johnson@ARM.com tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 108111585SDylan.Johnson@ARM.com } 108210037SARM gem5 Developers } 108310037SARM gem5 Developers} 108410037SARM gem5 Developers 108510037SARM gem5 Developerstemplate<class T> 108612570Sgiacomo.travaglini@arm.comvoid 108712570Sgiacomo.travaglini@arm.comAbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 108812570Sgiacomo.travaglini@arm.com{ 108912570Sgiacomo.travaglini@arm.com srcEncoded = getFaultStatusCode(tc); 109012570Sgiacomo.travaglini@arm.com if (srcEncoded == ArmFault::FaultSourceInvalid) { 109112570Sgiacomo.travaglini@arm.com panic("Invalid fault source\n"); 109212570Sgiacomo.travaglini@arm.com } 109312570Sgiacomo.travaglini@arm.com ArmFault::setSyndrome(tc, syndrome_reg); 109412570Sgiacomo.travaglini@arm.com} 109512570Sgiacomo.travaglini@arm.com 109612570Sgiacomo.travaglini@arm.comtemplate<class T> 109712570Sgiacomo.travaglini@arm.comuint8_t 109812570Sgiacomo.travaglini@arm.comAbortFault<T>::getFaultStatusCode(ThreadContext *tc) const 109912570Sgiacomo.travaglini@arm.com{ 110012570Sgiacomo.travaglini@arm.com 110112570Sgiacomo.travaglini@arm.com panic_if(!this->faultUpdated, 110212570Sgiacomo.travaglini@arm.com "Trying to use un-updated ArmFault internal variables\n"); 110312570Sgiacomo.travaglini@arm.com 110412570Sgiacomo.travaglini@arm.com uint8_t fsc = 0; 110512570Sgiacomo.travaglini@arm.com 110612570Sgiacomo.travaglini@arm.com if (!this->to64) { 110712570Sgiacomo.travaglini@arm.com // AArch32 110812570Sgiacomo.travaglini@arm.com assert(tranMethod != ArmFault::UnknownTran); 110912570Sgiacomo.travaglini@arm.com if (tranMethod == ArmFault::LpaeTran) { 111012570Sgiacomo.travaglini@arm.com fsc = ArmFault::longDescFaultSources[source]; 111112570Sgiacomo.travaglini@arm.com } else { 111212570Sgiacomo.travaglini@arm.com fsc = ArmFault::shortDescFaultSources[source]; 111312570Sgiacomo.travaglini@arm.com } 111412570Sgiacomo.travaglini@arm.com } else { 111512570Sgiacomo.travaglini@arm.com // AArch64 111612570Sgiacomo.travaglini@arm.com fsc = ArmFault::aarch64FaultSources[source]; 111712570Sgiacomo.travaglini@arm.com } 111812570Sgiacomo.travaglini@arm.com 111912570Sgiacomo.travaglini@arm.com return fsc; 112012570Sgiacomo.travaglini@arm.com} 112112570Sgiacomo.travaglini@arm.com 112212570Sgiacomo.travaglini@arm.comtemplate<class T> 112310037SARM gem5 DevelopersFSR 112412570Sgiacomo.travaglini@arm.comAbortFault<T>::getFsr(ThreadContext *tc) const 112510037SARM gem5 Developers{ 11267362Sgblack@eecs.umich.edu FSR fsr = 0; 11278314Sgeoffrey.blake@arm.com 112812570Sgiacomo.travaglini@arm.com auto fsc = getFaultStatusCode(tc); 112912570Sgiacomo.travaglini@arm.com 113012570Sgiacomo.travaglini@arm.com // AArch32 113112570Sgiacomo.travaglini@arm.com assert(tranMethod != ArmFault::UnknownTran); 113212570Sgiacomo.travaglini@arm.com if (tranMethod == ArmFault::LpaeTran) { 113312570Sgiacomo.travaglini@arm.com fsr.status = fsc; 113412570Sgiacomo.travaglini@arm.com fsr.lpae = 1; 113510037SARM gem5 Developers } else { 113612570Sgiacomo.travaglini@arm.com fsr.fsLow = bits(fsc, 3, 0); 113712570Sgiacomo.travaglini@arm.com fsr.fsHigh = bits(fsc, 4); 113812570Sgiacomo.travaglini@arm.com fsr.domain = static_cast<uint8_t>(domain); 113910037SARM gem5 Developers } 114012570Sgiacomo.travaglini@arm.com 114112570Sgiacomo.travaglini@arm.com fsr.wnr = (write ? 1 : 0); 114212570Sgiacomo.travaglini@arm.com fsr.ext = 0; 114312570Sgiacomo.travaglini@arm.com 114410037SARM gem5 Developers return fsr; 114510037SARM gem5 Developers} 114610037SARM gem5 Developers 114710037SARM gem5 Developerstemplate<class T> 114810037SARM gem5 Developersbool 114910037SARM gem5 DevelopersAbortFault<T>::abortDisable(ThreadContext *tc) 115010037SARM gem5 Developers{ 115110037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 115210037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 115310037SARM gem5 Developers return (!scr.ns || scr.aw); 115410037SARM gem5 Developers } 115510037SARM gem5 Developers return true; 115610037SARM gem5 Developers} 115710037SARM gem5 Developers 115810037SARM gem5 Developerstemplate<class T> 115910037SARM gem5 Developersvoid 116010037SARM gem5 DevelopersAbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 116110037SARM gem5 Developers{ 116210037SARM gem5 Developers switch (id) 116310037SARM gem5 Developers { 116410037SARM gem5 Developers case ArmFault::S1PTW: 116510037SARM gem5 Developers s1ptw = val; 116610037SARM gem5 Developers break; 116710037SARM gem5 Developers case ArmFault::OVA: 116810037SARM gem5 Developers OVAddr = val; 116910037SARM gem5 Developers break; 117010037SARM gem5 Developers 117110037SARM gem5 Developers // Just ignore unknown ID's 117210037SARM gem5 Developers default: 117310037SARM gem5 Developers break; 117410037SARM gem5 Developers } 117510037SARM gem5 Developers} 117610037SARM gem5 Developers 117710037SARM gem5 Developerstemplate<class T> 117810037SARM gem5 Developersuint32_t 117910037SARM gem5 DevelopersAbortFault<T>::iss() const 118010037SARM gem5 Developers{ 118110037SARM gem5 Developers uint32_t val; 118210037SARM gem5 Developers 118310037SARM gem5 Developers val = srcEncoded & 0x3F; 118410037SARM gem5 Developers val |= write << 6; 118510037SARM gem5 Developers val |= s1ptw << 7; 118610037SARM gem5 Developers return (val); 118710037SARM gem5 Developers} 118810037SARM gem5 Developers 118910037SARM gem5 Developerstemplate<class T> 119010037SARM gem5 Developersbool 119110037SARM gem5 DevelopersAbortFault<T>::isMMUFault() const 119210037SARM gem5 Developers{ 119310037SARM gem5 Developers // NOTE: Not relying on LL information being aligned to lowest bits here 119410037SARM gem5 Developers return 119510037SARM gem5 Developers (source == ArmFault::AlignmentFault) || 119610037SARM gem5 Developers ((source >= ArmFault::TranslationLL) && 119710037SARM gem5 Developers (source < ArmFault::TranslationLL + 4)) || 119810037SARM gem5 Developers ((source >= ArmFault::AccessFlagLL) && 119910037SARM gem5 Developers (source < ArmFault::AccessFlagLL + 4)) || 120010037SARM gem5 Developers ((source >= ArmFault::DomainLL) && 120110037SARM gem5 Developers (source < ArmFault::DomainLL + 4)) || 120210037SARM gem5 Developers ((source >= ArmFault::PermissionLL) && 120310037SARM gem5 Developers (source < ArmFault::PermissionLL + 4)); 120410037SARM gem5 Developers} 120510037SARM gem5 Developers 120610037SARM gem5 DevelopersExceptionClass 120710037SARM gem5 DevelopersPrefetchAbort::ec(ThreadContext *tc) const 120810037SARM gem5 Developers{ 120910037SARM gem5 Developers if (to64) { 121010037SARM gem5 Developers // AArch64 121110037SARM gem5 Developers if (toEL == fromEL) 121210037SARM gem5 Developers return EC_PREFETCH_ABORT_CURR_EL; 121310037SARM gem5 Developers else 121410037SARM gem5 Developers return EC_PREFETCH_ABORT_LOWER_EL; 121510037SARM gem5 Developers } else { 121610037SARM gem5 Developers // AArch32 121710037SARM gem5 Developers // Abort faults have different EC codes depending on whether 121810037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 121910037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 122010037SARM gem5 Developers 122110037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 122210037SARM gem5 Developers 122310037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 122410037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 122510037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 122610037SARM gem5 Developers } 122710037SARM gem5 Developers return ec; 122810037SARM gem5 Developers } 122910037SARM gem5 Developers} 123010037SARM gem5 Developers 123110037SARM gem5 Developersbool 123210037SARM gem5 DevelopersPrefetchAbort::routeToMonitor(ThreadContext *tc) const 123310037SARM gem5 Developers{ 123410037SARM gem5 Developers SCR scr = 0; 123510037SARM gem5 Developers if (from64) 123610037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 123710037SARM gem5 Developers else 123810037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 123910037SARM gem5 Developers 124010037SARM gem5 Developers return scr.ea && !isMMUFault(); 124110037SARM gem5 Developers} 124210037SARM gem5 Developers 124310037SARM gem5 Developersbool 124410037SARM gem5 DevelopersPrefetchAbort::routeToHyp(ThreadContext *tc) const 124510037SARM gem5 Developers{ 124610037SARM gem5 Developers bool toHyp; 124710037SARM gem5 Developers 124810037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 124910037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 125010037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 125110037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 125210037SARM gem5 Developers 125310037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 125410037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 125510037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 125610037SARM gem5 Developers toHyp |= (stage2 || 125710037SARM gem5 Developers ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 125810037SARM gem5 Developers ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 125911581SDylan.Johnson@ARM.com ) && !inSecureState(tc); 126010037SARM gem5 Developers return toHyp; 126110037SARM gem5 Developers} 126210037SARM gem5 Developers 126310037SARM gem5 DevelopersExceptionClass 126410037SARM gem5 DevelopersDataAbort::ec(ThreadContext *tc) const 126510037SARM gem5 Developers{ 126610037SARM gem5 Developers if (to64) { 126710037SARM gem5 Developers // AArch64 126810037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 126910367SAndrew.Bardsley@arm.com panic("Asynchronous External Abort should be handled with " 127010367SAndrew.Bardsley@arm.com "SystemErrors (SErrors)!"); 127110037SARM gem5 Developers } 127210037SARM gem5 Developers if (toEL == fromEL) 127310037SARM gem5 Developers return EC_DATA_ABORT_CURR_EL; 127410037SARM gem5 Developers else 127510037SARM gem5 Developers return EC_DATA_ABORT_LOWER_EL; 127610037SARM gem5 Developers } else { 127710037SARM gem5 Developers // AArch32 127810037SARM gem5 Developers // Abort faults have different EC codes depending on whether 127910037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 128010037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 128110037SARM gem5 Developers 128210037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 128310037SARM gem5 Developers 128410037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 128510037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 128610037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 128710037SARM gem5 Developers } 128810037SARM gem5 Developers return ec; 128910037SARM gem5 Developers } 129010037SARM gem5 Developers} 129110037SARM gem5 Developers 129210037SARM gem5 Developersbool 129310037SARM gem5 DevelopersDataAbort::routeToMonitor(ThreadContext *tc) const 129410037SARM gem5 Developers{ 129510037SARM gem5 Developers SCR scr = 0; 129610037SARM gem5 Developers if (from64) 129710037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 129810037SARM gem5 Developers else 129910037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 130010037SARM gem5 Developers 130110037SARM gem5 Developers return scr.ea && !isMMUFault(); 130210037SARM gem5 Developers} 130310037SARM gem5 Developers 130410037SARM gem5 Developersbool 130510037SARM gem5 DevelopersDataAbort::routeToHyp(ThreadContext *tc) const 130610037SARM gem5 Developers{ 130710037SARM gem5 Developers bool toHyp; 130810037SARM gem5 Developers 130910037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 131010037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 131110037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 131210037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 131310037SARM gem5 Developers 131410037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 131510037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 131610037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 131710037SARM gem5 Developers toHyp |= (stage2 || 131810037SARM gem5 Developers ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 131910037SARM gem5 Developers ((source == DebugEvent) && hdcr.tde) ) 132010037SARM gem5 Developers ) || 132110037SARM gem5 Developers ( (cpsr.mode == MODE_USER) && hcr.tge && 132210037SARM gem5 Developers ((source == AlignmentFault) || 132310037SARM gem5 Developers (source == SynchronousExternalAbort)) 132410037SARM gem5 Developers ) 132511581SDylan.Johnson@ARM.com ) && !inSecureState(tc); 132610037SARM gem5 Developers return toHyp; 132710037SARM gem5 Developers} 132810037SARM gem5 Developers 132910037SARM gem5 Developersuint32_t 133010037SARM gem5 DevelopersDataAbort::iss() const 133110037SARM gem5 Developers{ 133210037SARM gem5 Developers uint32_t val; 133310037SARM gem5 Developers 133410037SARM gem5 Developers // Add on the data abort specific fields to the generic abort ISS value 133510037SARM gem5 Developers val = AbortFault<DataAbort>::iss(); 133610037SARM gem5 Developers // ISS is valid if not caused by a stage 1 page table walk, and when taken 133710037SARM gem5 Developers // to AArch64 only when directed to EL2 133810037SARM gem5 Developers if (!s1ptw && (!to64 || toEL == EL2)) { 133910037SARM gem5 Developers val |= isv << 24; 134010037SARM gem5 Developers if (isv) { 134110037SARM gem5 Developers val |= sas << 22; 134210037SARM gem5 Developers val |= sse << 21; 134310037SARM gem5 Developers val |= srt << 16; 134410037SARM gem5 Developers // AArch64 only. These assignments are safe on AArch32 as well 134510037SARM gem5 Developers // because these vars are initialized to false 134610037SARM gem5 Developers val |= sf << 15; 134710037SARM gem5 Developers val |= ar << 14; 134810037SARM gem5 Developers } 134910037SARM gem5 Developers } 135010037SARM gem5 Developers return (val); 135110037SARM gem5 Developers} 135210037SARM gem5 Developers 135310037SARM gem5 Developersvoid 135410037SARM gem5 DevelopersDataAbort::annotate(AnnotationIDs id, uint64_t val) 135510037SARM gem5 Developers{ 135610037SARM gem5 Developers AbortFault<DataAbort>::annotate(id, val); 135710037SARM gem5 Developers switch (id) 135810037SARM gem5 Developers { 135910037SARM gem5 Developers case SAS: 136010037SARM gem5 Developers isv = true; 136110037SARM gem5 Developers sas = val; 136210037SARM gem5 Developers break; 136310037SARM gem5 Developers case SSE: 136410037SARM gem5 Developers isv = true; 136510037SARM gem5 Developers sse = val; 136610037SARM gem5 Developers break; 136710037SARM gem5 Developers case SRT: 136810037SARM gem5 Developers isv = true; 136910037SARM gem5 Developers srt = val; 137010037SARM gem5 Developers break; 137110037SARM gem5 Developers case SF: 137210037SARM gem5 Developers isv = true; 137310037SARM gem5 Developers sf = val; 137410037SARM gem5 Developers break; 137510037SARM gem5 Developers case AR: 137610037SARM gem5 Developers isv = true; 137710037SARM gem5 Developers ar = val; 137810037SARM gem5 Developers break; 137910037SARM gem5 Developers // Just ignore unknown ID's 138010037SARM gem5 Developers default: 138110037SARM gem5 Developers break; 138210037SARM gem5 Developers } 138310037SARM gem5 Developers} 138410037SARM gem5 Developers 138510037SARM gem5 Developersvoid 138610417Sandreas.hansson@arm.comVirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 138710037SARM gem5 Developers{ 138810037SARM gem5 Developers AbortFault<VirtualDataAbort>::invoke(tc, inst); 138910037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 139010037SARM gem5 Developers hcr.va = 0; 139110037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 139210037SARM gem5 Developers} 139310037SARM gem5 Developers 139410037SARM gem5 Developersbool 139510037SARM gem5 DevelopersInterrupt::routeToMonitor(ThreadContext *tc) const 139610037SARM gem5 Developers{ 139710037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 139810037SARM gem5 Developers SCR scr = 0; 139910037SARM gem5 Developers if (from64) 140010037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 140110037SARM gem5 Developers else 140210037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 140310037SARM gem5 Developers return scr.irq; 140410037SARM gem5 Developers} 140510037SARM gem5 Developers 140610037SARM gem5 Developersbool 140710037SARM gem5 DevelopersInterrupt::routeToHyp(ThreadContext *tc) const 140810037SARM gem5 Developers{ 140910037SARM gem5 Developers bool toHyp; 141010037SARM gem5 Developers 141110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 141210037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 141310037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 141410037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 141511581SDylan.Johnson@ARM.com toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) || 141610037SARM gem5 Developers (cpsr.mode == MODE_HYP); 141710037SARM gem5 Developers return toHyp; 141810037SARM gem5 Developers} 141910037SARM gem5 Developers 142010037SARM gem5 Developersbool 142110037SARM gem5 DevelopersInterrupt::abortDisable(ThreadContext *tc) 142210037SARM gem5 Developers{ 142310037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 142410037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 142510037SARM gem5 Developers return (!scr.ns || scr.aw); 142610037SARM gem5 Developers } 142710037SARM gem5 Developers return true; 142810037SARM gem5 Developers} 142910037SARM gem5 Developers 143010037SARM gem5 DevelopersVirtualInterrupt::VirtualInterrupt() 143110037SARM gem5 Developers{} 143210037SARM gem5 Developers 143310037SARM gem5 Developersbool 143410037SARM gem5 DevelopersFastInterrupt::routeToMonitor(ThreadContext *tc) const 143510037SARM gem5 Developers{ 143610037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 143710037SARM gem5 Developers SCR scr = 0; 143810037SARM gem5 Developers if (from64) 143910037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 144010037SARM gem5 Developers else 144110037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 144210037SARM gem5 Developers return scr.fiq; 144310037SARM gem5 Developers} 144410037SARM gem5 Developers 144510037SARM gem5 Developersbool 144610037SARM gem5 DevelopersFastInterrupt::routeToHyp(ThreadContext *tc) const 144710037SARM gem5 Developers{ 144810037SARM gem5 Developers bool toHyp; 144910037SARM gem5 Developers 145010037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 145110037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 145210037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 145310037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 145411581SDylan.Johnson@ARM.com toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) || 145510037SARM gem5 Developers (cpsr.mode == MODE_HYP); 145610037SARM gem5 Developers return toHyp; 145710037SARM gem5 Developers} 145810037SARM gem5 Developers 145910037SARM gem5 Developersbool 146010037SARM gem5 DevelopersFastInterrupt::abortDisable(ThreadContext *tc) 146110037SARM gem5 Developers{ 146210037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 146310037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 146410037SARM gem5 Developers return (!scr.ns || scr.aw); 146510037SARM gem5 Developers } 146610037SARM gem5 Developers return true; 146710037SARM gem5 Developers} 146810037SARM gem5 Developers 146910037SARM gem5 Developersbool 147010037SARM gem5 DevelopersFastInterrupt::fiqDisable(ThreadContext *tc) 147110037SARM gem5 Developers{ 147210037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc)) { 147310037SARM gem5 Developers return true; 147410037SARM gem5 Developers } else if (ArmSystem::haveSecurity(tc)) { 147510037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 147610037SARM gem5 Developers return (!scr.ns || scr.fw); 147710037SARM gem5 Developers } 147810037SARM gem5 Developers return true; 147910037SARM gem5 Developers} 148010037SARM gem5 Developers 148110037SARM gem5 DevelopersVirtualFastInterrupt::VirtualFastInterrupt() 148210037SARM gem5 Developers{} 148310037SARM gem5 Developers 148410037SARM gem5 Developersvoid 148510417Sandreas.hansson@arm.comPCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 148610037SARM gem5 Developers{ 148710037SARM gem5 Developers ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 148810037SARM gem5 Developers assert(from64); 148910037SARM gem5 Developers // Set the FAR 149010037SARM gem5 Developers tc->setMiscReg(getFaultAddrReg64(), faultPC); 149110037SARM gem5 Developers} 149210037SARM gem5 Developers 149312568Sgiacomo.travaglini@arm.combool 149412568Sgiacomo.travaglini@arm.comPCAlignmentFault::routeToHyp(ThreadContext *tc) const 149512568Sgiacomo.travaglini@arm.com{ 149612568Sgiacomo.travaglini@arm.com bool toHyp = false; 149712568Sgiacomo.travaglini@arm.com 149812568Sgiacomo.travaglini@arm.com SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 149912568Sgiacomo.travaglini@arm.com HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 150012568Sgiacomo.travaglini@arm.com CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 150112568Sgiacomo.travaglini@arm.com 150212568Sgiacomo.travaglini@arm.com // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 150312568Sgiacomo.travaglini@arm.com toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 150412568Sgiacomo.travaglini@arm.com return toHyp; 150512568Sgiacomo.travaglini@arm.com} 150612568Sgiacomo.travaglini@arm.com 150710037SARM gem5 DevelopersSPAlignmentFault::SPAlignmentFault() 150810037SARM gem5 Developers{} 150910037SARM gem5 Developers 151010037SARM gem5 DevelopersSystemError::SystemError() 151110037SARM gem5 Developers{} 151210037SARM gem5 Developers 151310037SARM gem5 Developersvoid 151410417Sandreas.hansson@arm.comSystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 151510037SARM gem5 Developers{ 151611150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 151710037SARM gem5 Developers ArmFault::invoke(tc, inst); 151810037SARM gem5 Developers} 151910037SARM gem5 Developers 152010037SARM gem5 Developersbool 152110037SARM gem5 DevelopersSystemError::routeToMonitor(ThreadContext *tc) const 152210037SARM gem5 Developers{ 152310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 152410037SARM gem5 Developers assert(from64); 152510037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 152610037SARM gem5 Developers return scr.ea; 152710037SARM gem5 Developers} 152810037SARM gem5 Developers 152910037SARM gem5 Developersbool 153010037SARM gem5 DevelopersSystemError::routeToHyp(ThreadContext *tc) const 153110037SARM gem5 Developers{ 153210037SARM gem5 Developers bool toHyp; 153310037SARM gem5 Developers assert(from64); 153410037SARM gem5 Developers 153510037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 153610037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 153710037SARM gem5 Developers 153811581SDylan.Johnson@ARM.com toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 153911581SDylan.Johnson@ARM.com (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 154010037SARM gem5 Developers return toHyp; 15417362Sgblack@eecs.umich.edu} 15427362Sgblack@eecs.umich.edu 154312299Sandreas.sandberg@arm.com 154412299Sandreas.sandberg@arm.comSoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) 154512299Sandreas.sandberg@arm.com : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) 154612299Sandreas.sandberg@arm.com{} 154712299Sandreas.sandberg@arm.com 154812299Sandreas.sandberg@arm.combool 154912299Sandreas.sandberg@arm.comSoftwareBreakpoint::routeToHyp(ThreadContext *tc) const 155012299Sandreas.sandberg@arm.com{ 155112299Sandreas.sandberg@arm.com const bool have_el2 = ArmSystem::haveVirtualization(tc); 155212299Sandreas.sandberg@arm.com 155312299Sandreas.sandberg@arm.com const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 155412299Sandreas.sandberg@arm.com const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); 155512299Sandreas.sandberg@arm.com 155612299Sandreas.sandberg@arm.com return have_el2 && !inSecureState(tc) && fromEL <= EL1 && 155712299Sandreas.sandberg@arm.com (hcr.tge || mdcr.tde); 155812299Sandreas.sandberg@arm.com} 155912299Sandreas.sandberg@arm.com 156012732Sandreas.sandberg@arm.comExceptionClass 156112732Sandreas.sandberg@arm.comSoftwareBreakpoint::ec(ThreadContext *tc) const 156212732Sandreas.sandberg@arm.com{ 156312732Sandreas.sandberg@arm.com return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec; 156412732Sandreas.sandberg@arm.com} 156512732Sandreas.sandberg@arm.com 15667652Sminkyu.jeong@arm.comvoid 156710417Sandreas.hansson@arm.comArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 15688518Sgeoffrey.blake@arm.com DPRINTF(Faults, "Invoking ArmSev Fault\n"); 15698806Sgblack@eecs.umich.edu if (!FullSystem) 15708806Sgblack@eecs.umich.edu return; 15718806Sgblack@eecs.umich.edu 15728806Sgblack@eecs.umich.edu // Set sev_mailbox to 1, clear the pending interrupt from remote 15738806Sgblack@eecs.umich.edu // SEV execution and let pipeline continue as pcState is still 15748806Sgblack@eecs.umich.edu // valid. 15758806Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 157611150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 15778518Sgeoffrey.blake@arm.com} 15788518Sgeoffrey.blake@arm.com 157910037SARM gem5 Developers// Instantiate all the templates to make the linker happy 158010037SARM gem5 Developerstemplate class ArmFaultVals<Reset>; 158110037SARM gem5 Developerstemplate class ArmFaultVals<UndefinedInstruction>; 158210037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorCall>; 158310037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorCall>; 158410037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorCall>; 158510037SARM gem5 Developerstemplate class ArmFaultVals<PrefetchAbort>; 158610037SARM gem5 Developerstemplate class ArmFaultVals<DataAbort>; 158710037SARM gem5 Developerstemplate class ArmFaultVals<VirtualDataAbort>; 158810037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorTrap>; 158910037SARM gem5 Developerstemplate class ArmFaultVals<Interrupt>; 159010037SARM gem5 Developerstemplate class ArmFaultVals<VirtualInterrupt>; 159110037SARM gem5 Developerstemplate class ArmFaultVals<FastInterrupt>; 159210037SARM gem5 Developerstemplate class ArmFaultVals<VirtualFastInterrupt>; 159310037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorTrap>; 159410037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorTrap>; 159510037SARM gem5 Developerstemplate class ArmFaultVals<PCAlignmentFault>; 159610037SARM gem5 Developerstemplate class ArmFaultVals<SPAlignmentFault>; 159710037SARM gem5 Developerstemplate class ArmFaultVals<SystemError>; 159812299Sandreas.sandberg@arm.comtemplate class ArmFaultVals<SoftwareBreakpoint>; 159910037SARM gem5 Developerstemplate class ArmFaultVals<ArmSev>; 160010037SARM gem5 Developerstemplate class AbortFault<PrefetchAbort>; 160110037SARM gem5 Developerstemplate class AbortFault<DataAbort>; 160210037SARM gem5 Developerstemplate class AbortFault<VirtualDataAbort>; 160310037SARM gem5 Developers 160410037SARM gem5 Developers 160510037SARM gem5 DevelopersIllegalInstSetStateFault::IllegalInstSetStateFault() 160610037SARM gem5 Developers{} 160710037SARM gem5 Developers 16086019Shines@cs.fsu.edu 16096019Shines@cs.fsu.edu} // namespace ArmISA 1610