faults.cc revision 13895
1/* 2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 * Giacomo Gabrielli 44 * Thomas Grocutt 45 */ 46 47#include "arch/arm/faults.hh" 48 49#include "arch/arm/insts/static_inst.hh" 50#include "arch/arm/system.hh" 51#include "arch/arm/utility.hh" 52#include "base/compiler.hh" 53#include "base/trace.hh" 54#include "cpu/base.hh" 55#include "cpu/thread_context.hh" 56#include "debug/Faults.hh" 57#include "sim/full_system.hh" 58 59namespace ArmISA 60{ 61 62uint8_t ArmFault::shortDescFaultSources[] = { 63 0x01, // AlignmentFault 64 0x04, // InstructionCacheMaintenance 65 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 66 0x0c, // SynchExtAbtOnTranslTableWalkL1 67 0x0e, // SynchExtAbtOnTranslTableWalkL2 68 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 69 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 70 0x1c, // SynchPtyErrOnTranslTableWalkL1 71 0x1e, // SynchPtyErrOnTranslTableWalkL2 72 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 73 0xff, // TranslationL0 (INVALID) 74 0x05, // TranslationL1 75 0x07, // TranslationL2 76 0xff, // TranslationL3 (INVALID) 77 0xff, // AccessFlagL0 (INVALID) 78 0x03, // AccessFlagL1 79 0x06, // AccessFlagL2 80 0xff, // AccessFlagL3 (INVALID) 81 0xff, // DomainL0 (INVALID) 82 0x09, // DomainL1 83 0x0b, // DomainL2 84 0xff, // DomainL3 (INVALID) 85 0xff, // PermissionL0 (INVALID) 86 0x0d, // PermissionL1 87 0x0f, // PermissionL2 88 0xff, // PermissionL3 (INVALID) 89 0x02, // DebugEvent 90 0x08, // SynchronousExternalAbort 91 0x10, // TLBConflictAbort 92 0x19, // SynchPtyErrOnMemoryAccess 93 0x16, // AsynchronousExternalAbort 94 0x18, // AsynchPtyErrOnMemoryAccess 95 0xff, // AddressSizeL0 (INVALID) 96 0xff, // AddressSizeL1 (INVALID) 97 0xff, // AddressSizeL2 (INVALID) 98 0xff, // AddressSizeL3 (INVALID) 99 0x40, // PrefetchTLBMiss 100 0x80 // PrefetchUncacheable 101}; 102 103static_assert(sizeof(ArmFault::shortDescFaultSources) == 104 ArmFault::NumFaultSources, 105 "Invalid size of ArmFault::shortDescFaultSources[]"); 106 107uint8_t ArmFault::longDescFaultSources[] = { 108 0x21, // AlignmentFault 109 0xff, // InstructionCacheMaintenance (INVALID) 110 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 111 0x15, // SynchExtAbtOnTranslTableWalkL1 112 0x16, // SynchExtAbtOnTranslTableWalkL2 113 0x17, // SynchExtAbtOnTranslTableWalkL3 114 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 115 0x1d, // SynchPtyErrOnTranslTableWalkL1 116 0x1e, // SynchPtyErrOnTranslTableWalkL2 117 0x1f, // SynchPtyErrOnTranslTableWalkL3 118 0xff, // TranslationL0 (INVALID) 119 0x05, // TranslationL1 120 0x06, // TranslationL2 121 0x07, // TranslationL3 122 0xff, // AccessFlagL0 (INVALID) 123 0x09, // AccessFlagL1 124 0x0a, // AccessFlagL2 125 0x0b, // AccessFlagL3 126 0xff, // DomainL0 (INVALID) 127 0x3d, // DomainL1 128 0x3e, // DomainL2 129 0xff, // DomainL3 (RESERVED) 130 0xff, // PermissionL0 (INVALID) 131 0x0d, // PermissionL1 132 0x0e, // PermissionL2 133 0x0f, // PermissionL3 134 0x22, // DebugEvent 135 0x10, // SynchronousExternalAbort 136 0x30, // TLBConflictAbort 137 0x18, // SynchPtyErrOnMemoryAccess 138 0x11, // AsynchronousExternalAbort 139 0x19, // AsynchPtyErrOnMemoryAccess 140 0xff, // AddressSizeL0 (INVALID) 141 0xff, // AddressSizeL1 (INVALID) 142 0xff, // AddressSizeL2 (INVALID) 143 0xff, // AddressSizeL3 (INVALID) 144 0x40, // PrefetchTLBMiss 145 0x80 // PrefetchUncacheable 146}; 147 148static_assert(sizeof(ArmFault::longDescFaultSources) == 149 ArmFault::NumFaultSources, 150 "Invalid size of ArmFault::longDescFaultSources[]"); 151 152uint8_t ArmFault::aarch64FaultSources[] = { 153 0x21, // AlignmentFault 154 0xff, // InstructionCacheMaintenance (INVALID) 155 0x14, // SynchExtAbtOnTranslTableWalkL0 156 0x15, // SynchExtAbtOnTranslTableWalkL1 157 0x16, // SynchExtAbtOnTranslTableWalkL2 158 0x17, // SynchExtAbtOnTranslTableWalkL3 159 0x1c, // SynchPtyErrOnTranslTableWalkL0 160 0x1d, // SynchPtyErrOnTranslTableWalkL1 161 0x1e, // SynchPtyErrOnTranslTableWalkL2 162 0x1f, // SynchPtyErrOnTranslTableWalkL3 163 0x04, // TranslationL0 164 0x05, // TranslationL1 165 0x06, // TranslationL2 166 0x07, // TranslationL3 167 0x08, // AccessFlagL0 168 0x09, // AccessFlagL1 169 0x0a, // AccessFlagL2 170 0x0b, // AccessFlagL3 171 // @todo: Section & Page Domain Fault in AArch64? 172 0xff, // DomainL0 (INVALID) 173 0xff, // DomainL1 (INVALID) 174 0xff, // DomainL2 (INVALID) 175 0xff, // DomainL3 (INVALID) 176 0x0c, // PermissionL0 177 0x0d, // PermissionL1 178 0x0e, // PermissionL2 179 0x0f, // PermissionL3 180 0x22, // DebugEvent 181 0x10, // SynchronousExternalAbort 182 0x30, // TLBConflictAbort 183 0x18, // SynchPtyErrOnMemoryAccess 184 0xff, // AsynchronousExternalAbort (INVALID) 185 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 186 0x00, // AddressSizeL0 187 0x01, // AddressSizeL1 188 0x02, // AddressSizeL2 189 0x03, // AddressSizeL3 190 0x40, // PrefetchTLBMiss 191 0x80 // PrefetchUncacheable 192}; 193 194static_assert(sizeof(ArmFault::aarch64FaultSources) == 195 ArmFault::NumFaultSources, 196 "Invalid size of ArmFault::aarch64FaultSources[]"); 197 198// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 199// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 200// {A, F} disable, class, stat 201template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals( 202 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 203 // location in AArch64) 204 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 205 0, 0, 0, 0, false, true, true, EC_UNKNOWN 206); 207template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals( 208 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 209 4, 2, 0, 0, true, false, false, EC_UNKNOWN 210); 211template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals( 212 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 213 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP 214); 215template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals( 216 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 217 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP 218); 219template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals( 220 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 221 4, 4, 4, 4, true, false, false, EC_HVC 222); 223template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals( 224 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 225 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP 226); 227template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals( 228 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 229 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP 230); 231template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals( 232 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 233 8, 8, 0, 0, true, true, false, EC_INVALID 234); 235template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals( 236 // @todo: double check these values 237 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 238 0, 0, 0, 0, false, false, false, EC_UNKNOWN 239); 240template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals( 241 "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 242 4, 2, 0, 0, false, false, false, EC_UNKNOWN 243); 244template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals( 245 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 246 4, 4, 0, 0, false, true, false, EC_UNKNOWN 247); 248template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals( 249 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 250 4, 4, 0, 0, false, true, false, EC_INVALID 251); 252template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals( 253 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 254 4, 4, 0, 0, false, true, true, EC_UNKNOWN 255); 256template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals( 257 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 258 4, 4, 0, 0, false, true, true, EC_INVALID 259); 260template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals( 261 "Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 262 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST 263); 264template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals( 265 // Some dummy values (SupervisorTrap is AArch64-only) 266 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 267 0, 0, 0, 0, false, false, false, EC_UNKNOWN 268); 269template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals( 270 // Some dummy values (PCAlignmentFault is AArch64-only) 271 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 272 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT 273); 274template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals( 275 // Some dummy values (SPAlignmentFault is AArch64-only) 276 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 277 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT 278); 279template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals( 280 // Some dummy values (SError is AArch64-only) 281 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 282 0, 0, 0, 0, false, true, true, EC_SERROR 283); 284template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals( 285 // Some dummy values (SoftwareBreakpoint is AArch64-only) 286 "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 287 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT 288); 289template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals( 290 // Some dummy values 291 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 292 0, 0, 0, 0, false, true, true, EC_UNKNOWN 293); 294 295Addr 296ArmFault::getVector(ThreadContext *tc) 297{ 298 Addr base; 299 300 // Check for invalid modes 301 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 302 assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON); 303 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 304 305 switch (cpsr.mode) 306 { 307 case MODE_MON: 308 base = tc->readMiscReg(MISCREG_MVBAR); 309 break; 310 case MODE_HYP: 311 base = tc->readMiscReg(MISCREG_HVBAR); 312 break; 313 default: 314 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 315 if (sctlr.v) { 316 base = HighVecs; 317 } else { 318 base = ArmSystem::haveSecurity(tc) ? 319 tc->readMiscReg(MISCREG_VBAR) : 0; 320 } 321 break; 322 } 323 324 return base + offset(tc); 325} 326 327Addr 328ArmFault::getVector64(ThreadContext *tc) 329{ 330 Addr vbar; 331 switch (toEL) { 332 case EL3: 333 assert(ArmSystem::haveSecurity(tc)); 334 vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 335 break; 336 case EL2: 337 assert(ArmSystem::haveVirtualization(tc)); 338 vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 339 break; 340 case EL1: 341 vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 342 break; 343 default: 344 panic("Invalid target exception level"); 345 break; 346 } 347 return vbar + offset64(tc); 348} 349 350MiscRegIndex 351ArmFault::getSyndromeReg64() const 352{ 353 switch (toEL) { 354 case EL1: 355 return MISCREG_ESR_EL1; 356 case EL2: 357 return MISCREG_ESR_EL2; 358 case EL3: 359 return MISCREG_ESR_EL3; 360 default: 361 panic("Invalid exception level"); 362 break; 363 } 364} 365 366MiscRegIndex 367ArmFault::getFaultAddrReg64() const 368{ 369 switch (toEL) { 370 case EL1: 371 return MISCREG_FAR_EL1; 372 case EL2: 373 return MISCREG_FAR_EL2; 374 case EL3: 375 return MISCREG_FAR_EL3; 376 default: 377 panic("Invalid exception level"); 378 break; 379 } 380} 381 382void 383ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 384{ 385 uint32_t value; 386 uint32_t exc_class = (uint32_t) ec(tc); 387 uint32_t issVal = iss(); 388 389 assert(!from64 || ArmSystem::highestELIs64(tc)); 390 391 value = exc_class << 26; 392 393 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 394 // 0x25) for which the ISS information is not valid (ARMv7). 395 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 396 // valid it is treated as RES1. 397 if (to64) { 398 value |= 1 << 25; 399 } else if ((bits(exc_class, 5, 3) != 4) || 400 (bits(exc_class, 2) && bits(issVal, 24))) { 401 if (!machInst.thumb || machInst.bigThumb) 402 value |= 1 << 25; 403 } 404 // Condition code valid for EC[5:4] nonzero 405 if (!from64 && ((bits(exc_class, 5, 4) == 0) && 406 (bits(exc_class, 3, 0) != 0))) { 407 if (!machInst.thumb) { 408 uint32_t cond; 409 ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 410 // If its on unconditional instruction report with a cond code of 411 // 0xE, ie the unconditional code 412 cond = (condCode == COND_UC) ? COND_AL : condCode; 413 value |= cond << 20; 414 value |= 1 << 24; 415 } 416 value |= bits(issVal, 19, 0); 417 } else { 418 value |= issVal; 419 } 420 tc->setMiscReg(syndrome_reg, value); 421} 422 423void 424ArmFault::update(ThreadContext *tc) 425{ 426 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 427 428 // Determine source exception level and mode 429 fromMode = (OperatingMode) (uint8_t) cpsr.mode; 430 fromEL = opModeToEL(fromMode); 431 if (opModeIs64(fromMode)) 432 from64 = true; 433 434 // Determine target exception level (aarch64) or target execution 435 // mode (aarch32). 436 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) { 437 toMode = MODE_MON; 438 toEL = EL3; 439 } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) { 440 toMode = MODE_HYP; 441 toEL = EL2; 442 hypRouted = true; 443 } else { 444 toMode = nextMode(); 445 toEL = opModeToEL(toMode); 446 } 447 448 if (fromEL > toEL) 449 toEL = fromEL; 450 451 to64 = ELIs64(tc, toEL); 452 453 // The fault specific informations have been updated; it is 454 // now possible to use them inside the fault. 455 faultUpdated = true; 456} 457 458void 459ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 460{ 461 462 // Update fault state informations, like the starting mode (aarch32) 463 // or EL (aarch64) and the ending mode or EL. 464 // From the update function we are also evaluating if the fault must 465 // be handled in AArch64 mode (to64). 466 update(tc); 467 468 if (to64) { 469 // Invoke exception handler in AArch64 state 470 invoke64(tc, inst); 471 return; 472 } 473 474 // ARMv7 (ARM ARM issue C B1.9) 475 476 bool have_security = ArmSystem::haveSecurity(tc); 477 478 FaultBase::invoke(tc); 479 if (!FullSystem) 480 return; 481 countStat()++; 482 483 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 484 SCR scr = tc->readMiscReg(MISCREG_SCR); 485 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 486 saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 487 saved_cpsr.c = tc->readCCReg(CCREG_C); 488 saved_cpsr.v = tc->readCCReg(CCREG_V); 489 saved_cpsr.ge = tc->readCCReg(CCREG_GE); 490 491 Addr curPc M5_VAR_USED = tc->pcState().pc(); 492 ITSTATE it = tc->pcState().itstate(); 493 saved_cpsr.it2 = it.top6; 494 saved_cpsr.it1 = it.bottom2; 495 496 // if we have a valid instruction then use it to annotate this fault with 497 // extra information. This is used to generate the correct fault syndrome 498 // information 499 if (inst) { 500 ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get()); 501 armInst->annotateFault(this); 502 } 503 504 // Ensure Secure state if initially in Monitor mode 505 if (have_security && saved_cpsr.mode == MODE_MON) { 506 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 507 if (scr.ns) { 508 scr.ns = 0; 509 tc->setMiscRegNoEffect(MISCREG_SCR, scr); 510 } 511 } 512 513 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 514 cpsr.mode = toMode; 515 516 // some bits are set differently if we have been routed to hyp mode 517 if (cpsr.mode == MODE_HYP) { 518 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 519 cpsr.t = hsctlr.te; 520 cpsr.e = hsctlr.ee; 521 if (!scr.ea) {cpsr.a = 1;} 522 if (!scr.fiq) {cpsr.f = 1;} 523 if (!scr.irq) {cpsr.i = 1;} 524 } else if (cpsr.mode == MODE_MON) { 525 // Special case handling when entering monitor mode 526 cpsr.t = sctlr.te; 527 cpsr.e = sctlr.ee; 528 cpsr.a = 1; 529 cpsr.f = 1; 530 cpsr.i = 1; 531 } else { 532 cpsr.t = sctlr.te; 533 cpsr.e = sctlr.ee; 534 535 // The *Disable functions are virtual and different per fault 536 cpsr.a = cpsr.a | abortDisable(tc); 537 cpsr.f = cpsr.f | fiqDisable(tc); 538 cpsr.i = 1; 539 } 540 cpsr.it1 = cpsr.it2 = 0; 541 cpsr.j = 0; 542 tc->setMiscReg(MISCREG_CPSR, cpsr); 543 544 // Make sure mailbox sets to one always 545 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 546 547 // Clear the exclusive monitor 548 tc->setMiscReg(MISCREG_LOCKFLAG, 0); 549 550 if (cpsr.mode == MODE_HYP) { 551 tc->setMiscReg(MISCREG_ELR_HYP, curPc + 552 (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 553 } else { 554 tc->setIntReg(INTREG_LR, curPc + 555 (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 556 } 557 558 switch (cpsr.mode) { 559 case MODE_FIQ: 560 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 561 break; 562 case MODE_IRQ: 563 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 564 break; 565 case MODE_SVC: 566 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 567 break; 568 case MODE_MON: 569 assert(have_security); 570 tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 571 break; 572 case MODE_ABORT: 573 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 574 break; 575 case MODE_UNDEFINED: 576 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 577 if (ec(tc) != EC_UNKNOWN) 578 setSyndrome(tc, MISCREG_HSR); 579 break; 580 case MODE_HYP: 581 assert(ArmSystem::haveVirtualization(tc)); 582 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 583 setSyndrome(tc, MISCREG_HSR); 584 break; 585 default: 586 panic("unknown Mode\n"); 587 } 588 589 Addr newPc = getVector(tc); 590 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 591 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 592 PCState pc(newPc); 593 pc.thumb(cpsr.t); 594 pc.nextThumb(pc.thumb()); 595 pc.jazelle(cpsr.j); 596 pc.nextJazelle(pc.jazelle()); 597 pc.aarch64(!cpsr.width); 598 pc.nextAArch64(!cpsr.width); 599 pc.illegalExec(false); 600 tc->pcState(pc); 601} 602 603void 604ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 605{ 606 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 607 MiscRegIndex elr_idx, spsr_idx; 608 switch (toEL) { 609 case EL1: 610 elr_idx = MISCREG_ELR_EL1; 611 spsr_idx = MISCREG_SPSR_EL1; 612 break; 613 case EL2: 614 assert(ArmSystem::haveVirtualization(tc)); 615 elr_idx = MISCREG_ELR_EL2; 616 spsr_idx = MISCREG_SPSR_EL2; 617 break; 618 case EL3: 619 assert(ArmSystem::haveSecurity(tc)); 620 elr_idx = MISCREG_ELR_EL3; 621 spsr_idx = MISCREG_SPSR_EL3; 622 break; 623 default: 624 panic("Invalid target exception level"); 625 break; 626 } 627 628 // Save process state into SPSR_ELx 629 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 630 CPSR spsr = cpsr; 631 spsr.nz = tc->readCCReg(CCREG_NZ); 632 spsr.c = tc->readCCReg(CCREG_C); 633 spsr.v = tc->readCCReg(CCREG_V); 634 if (from64) { 635 // Force some bitfields to 0 636 spsr.q = 0; 637 spsr.it1 = 0; 638 spsr.j = 0; 639 spsr.res0_23_22 = 0; 640 spsr.ge = 0; 641 spsr.it2 = 0; 642 spsr.t = 0; 643 } else { 644 spsr.ge = tc->readCCReg(CCREG_GE); 645 ITSTATE it = tc->pcState().itstate(); 646 spsr.it2 = it.top6; 647 spsr.it1 = it.bottom2; 648 // Force some bitfields to 0 649 spsr.res0_23_22 = 0; 650 spsr.ss = 0; 651 } 652 tc->setMiscReg(spsr_idx, spsr); 653 654 // Save preferred return address into ELR_ELx 655 Addr curr_pc = tc->pcState().pc(); 656 Addr ret_addr = curr_pc; 657 if (from64) 658 ret_addr += armPcElrOffset(); 659 else 660 ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 661 tc->setMiscReg(elr_idx, ret_addr); 662 663 Addr vec_address = getVector64(tc); 664 665 // Update process state 666 OperatingMode64 mode = 0; 667 mode.spX = 1; 668 mode.el = toEL; 669 mode.width = 0; 670 cpsr.mode = mode; 671 cpsr.daif = 0xf; 672 cpsr.il = 0; 673 cpsr.ss = 0; 674 tc->setMiscReg(MISCREG_CPSR, cpsr); 675 676 // Set PC to start of exception handler 677 Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL); 678 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 679 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); 680 PCState pc(new_pc); 681 pc.aarch64(!cpsr.width); 682 pc.nextAArch64(!cpsr.width); 683 pc.illegalExec(false); 684 tc->pcState(pc); 685 686 // If we have a valid instruction then use it to annotate this fault with 687 // extra information. This is used to generate the correct fault syndrome 688 // information 689 if (inst) 690 static_cast<ArmStaticInst *>(inst.get())->annotateFault(this); 691 // Save exception syndrome 692 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 693 setSyndrome(tc, getSyndromeReg64()); 694} 695 696Addr 697Reset::getVector(ThreadContext *tc) 698{ 699 Addr base; 700 701 // Check for invalid modes 702 CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 703 assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON); 704 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 705 706 // RVBAR is aliased (implemented as) MVBAR in gem5, since the two 707 // are mutually exclusive; there is no need to check here for 708 // which register to use since they hold the same value 709 base = tc->readMiscReg(MISCREG_MVBAR); 710 711 return base + offset(tc); 712} 713 714void 715Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 716{ 717 if (FullSystem) { 718 tc->getCpuPtr()->clearInterrupts(tc->threadId()); 719 tc->clearArchRegs(); 720 } 721 if (!ArmSystem::highestELIs64(tc)) { 722 ArmFault::invoke(tc, inst); 723 tc->setMiscReg(MISCREG_VMPIDR, 724 getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 725 726 // Unless we have SMC code to get us there, boot in HYP! 727 if (ArmSystem::haveVirtualization(tc) && 728 !ArmSystem::haveSecurity(tc)) { 729 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 730 cpsr.mode = MODE_HYP; 731 tc->setMiscReg(MISCREG_CPSR, cpsr); 732 } 733 } else { 734 // Advance the PC to the IMPLEMENTATION DEFINED reset value 735 PCState pc = ArmSystem::resetAddr(tc); 736 pc.aarch64(true); 737 pc.nextAArch64(true); 738 tc->pcState(pc); 739 } 740} 741 742void 743UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 744{ 745 if (FullSystem) { 746 ArmFault::invoke(tc, inst); 747 return; 748 } 749 750 // If the mnemonic isn't defined this has to be an unknown instruction. 751 assert(unknown || mnemonic != NULL); 752 auto arm_inst = static_cast<ArmStaticInst *>(inst.get()); 753 if (disabled) { 754 panic("Attempted to execute disabled instruction " 755 "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); 756 } else if (unknown) { 757 panic("Attempted to execute unknown instruction (inst 0x%08x)", 758 arm_inst->encoding()); 759 } else { 760 panic("Attempted to execute unimplemented instruction " 761 "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); 762 } 763} 764 765bool 766UndefinedInstruction::routeToHyp(ThreadContext *tc) const 767{ 768 bool toHyp; 769 770 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 771 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 772 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 773 774 // if in Hyp mode then stay in Hyp mode 775 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 776 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 777 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 778 return toHyp; 779} 780 781uint32_t 782UndefinedInstruction::iss() const 783{ 784 785 // If UndefinedInstruction is routed to hypervisor, iss field is 0. 786 if (hypRouted) { 787 return 0; 788 } 789 790 if (overrideEc == EC_INVALID) 791 return issRaw; 792 793 uint32_t new_iss = 0; 794 uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 795 796 dir = bits(machInst, 21, 21); 797 op0 = bits(machInst, 20, 19); 798 op1 = bits(machInst, 18, 16); 799 CRn = bits(machInst, 15, 12); 800 CRm = bits(machInst, 11, 8); 801 op2 = bits(machInst, 7, 5); 802 Rt = bits(machInst, 4, 0); 803 804 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 805 Rt << 5 | CRm << 1 | dir; 806 807 return new_iss; 808} 809 810void 811SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 812{ 813 if (FullSystem) { 814 ArmFault::invoke(tc, inst); 815 return; 816 } 817 818 // As of now, there isn't a 32 bit thumb version of this instruction. 819 assert(!machInst.bigThumb); 820 uint32_t callNum; 821 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 822 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 823 if (opModeIs64(mode)) 824 callNum = tc->readIntReg(INTREG_X8); 825 else 826 callNum = tc->readIntReg(INTREG_R7); 827 Fault fault; 828 tc->syscall(callNum, &fault); 829 830 // Advance the PC since that won't happen automatically. 831 PCState pc = tc->pcState(); 832 assert(inst); 833 inst->advancePC(pc); 834 tc->pcState(pc); 835} 836 837bool 838SupervisorCall::routeToHyp(ThreadContext *tc) const 839{ 840 bool toHyp; 841 842 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 843 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 844 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 845 846 // if in Hyp mode then stay in Hyp mode 847 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 848 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 849 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 850 return toHyp; 851} 852 853ExceptionClass 854SupervisorCall::ec(ThreadContext *tc) const 855{ 856 return (overrideEc != EC_INVALID) ? overrideEc : 857 (from64 ? EC_SVC_64 : vals.ec); 858} 859 860uint32_t 861SupervisorCall::iss() const 862{ 863 // Even if we have a 24 bit imm from an arm32 instruction then we only use 864 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 865 return issRaw & 0xFFFF; 866} 867 868uint32_t 869SecureMonitorCall::iss() const 870{ 871 if (from64) 872 return bits(machInst, 20, 5); 873 return 0; 874} 875 876ExceptionClass 877UndefinedInstruction::ec(ThreadContext *tc) const 878{ 879 // If UndefinedInstruction is routed to hypervisor, 880 // HSR.EC field is 0. 881 if (hypRouted) 882 return EC_UNKNOWN; 883 else 884 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 885} 886 887 888HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 889 ArmFaultVals<HypervisorCall>(_machInst, _imm) 890{} 891 892ExceptionClass 893HypervisorCall::ec(ThreadContext *tc) const 894{ 895 return from64 ? EC_HVC_64 : vals.ec; 896} 897 898ExceptionClass 899HypervisorTrap::ec(ThreadContext *tc) const 900{ 901 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 902} 903 904template<class T> 905FaultOffset 906ArmFaultVals<T>::offset(ThreadContext *tc) 907{ 908 bool isHypTrap = false; 909 910 // Normally we just use the exception vector from the table at the top if 911 // this file, however if this exception has caused a transition to hype 912 // mode, and its an exception type that would only do this if it has been 913 // trapped then we use the hyp trap vector instead of the normal vector 914 if (vals.hypTrappable) { 915 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 916 if (cpsr.mode == MODE_HYP) { 917 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 918 isHypTrap = spsr.mode != MODE_HYP; 919 } 920 } 921 return isHypTrap ? 0x14 : vals.offset; 922} 923 924template<class T> 925FaultOffset 926ArmFaultVals<T>::offset64(ThreadContext *tc) 927{ 928 if (toEL == fromEL) { 929 if (opModeIsT(fromMode)) 930 return vals.currELTOffset; 931 return vals.currELHOffset; 932 } else { 933 bool lower_32 = false; 934 if (toEL == EL3) { 935 if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2)) 936 lower_32 = ELIs32(tc, EL2); 937 else 938 lower_32 = ELIs32(tc, EL1); 939 } else { 940 lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1)); 941 } 942 943 if (lower_32) 944 return vals.lowerEL32Offset; 945 return vals.lowerEL64Offset; 946 } 947} 948 949// void 950// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 951// { 952// ESR esr = 0; 953// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 954// esr.il = !machInst.thumb; 955// if (machInst.aarch64) 956// esr.imm16 = bits(machInst.instBits, 20, 5); 957// else if (machInst.thumb) 958// esr.imm16 = bits(machInst.instBits, 7, 0); 959// else 960// esr.imm16 = bits(machInst.instBits, 15, 0); 961// tc->setMiscReg(esr_idx, esr); 962// } 963 964void 965SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 966{ 967 if (FullSystem) { 968 ArmFault::invoke(tc, inst); 969 return; 970 } 971} 972 973ExceptionClass 974SecureMonitorCall::ec(ThreadContext *tc) const 975{ 976 return (from64 ? EC_SMC_64 : vals.ec); 977} 978 979bool 980SupervisorTrap::routeToHyp(ThreadContext *tc) const 981{ 982 bool toHyp = false; 983 984 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 985 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 986 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 987 988 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 989 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 990 return toHyp; 991} 992 993uint32_t 994SupervisorTrap::iss() const 995{ 996 // If SupervisorTrap is routed to hypervisor, iss field is 0. 997 if (hypRouted) { 998 return 0; 999 } 1000 return issRaw; 1001} 1002 1003ExceptionClass 1004SupervisorTrap::ec(ThreadContext *tc) const 1005{ 1006 if (hypRouted) 1007 return EC_UNKNOWN; 1008 else 1009 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 1010} 1011 1012ExceptionClass 1013SecureMonitorTrap::ec(ThreadContext *tc) const 1014{ 1015 return (overrideEc != EC_INVALID) ? overrideEc : 1016 (from64 ? EC_SMC_64 : vals.ec); 1017} 1018 1019template<class T> 1020void 1021AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1022{ 1023 if (tranMethod == ArmFault::UnknownTran) { 1024 tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 1025 : ArmFault::VmsaTran; 1026 1027 if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 1028 // See ARM ARM B3-1416 1029 bool override_LPAE = false; 1030 TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 1031 TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 1032 if (ttbcr_s.eae) { 1033 override_LPAE = true; 1034 } else { 1035 // Unimplemented code option, not seen in testing. May need 1036 // extension according to the manual exceprt above. 1037 DPRINTF(Faults, "Warning: Incomplete translation method " 1038 "override detected.\n"); 1039 } 1040 if (override_LPAE) 1041 tranMethod = ArmFault::LpaeTran; 1042 } 1043 } 1044 1045 if (source == ArmFault::AsynchronousExternalAbort) { 1046 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 1047 } 1048 // Get effective fault source encoding 1049 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1050 1051 // source must be determined BEFORE invoking generic routines which will 1052 // try to set hsr etc. and are based upon source! 1053 ArmFaultVals<T>::invoke(tc, inst); 1054 1055 if (!this->to64) { // AArch32 1056 FSR fsr = getFsr(tc); 1057 if (cpsr.mode == MODE_HYP) { 1058 tc->setMiscReg(T::HFarIndex, faultAddr); 1059 } else if (stage2) { 1060 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 1061 tc->setMiscReg(T::HFarIndex, OVAddr); 1062 } else { 1063 tc->setMiscReg(T::FsrIndex, fsr); 1064 tc->setMiscReg(T::FarIndex, faultAddr); 1065 } 1066 DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 1067 "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 1068 } else { // AArch64 1069 // Set the FAR register. Nothing else to do if we are in AArch64 state 1070 // because the syndrome register has already been set inside invoke64() 1071 if (stage2) { 1072 // stage 2 fault, set HPFAR_EL2 to the faulting IPA 1073 // and FAR_EL2 to the Original VA 1074 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr); 1075 tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4); 1076 1077 DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n", 1078 OVAddr, faultAddr); 1079 } else { 1080 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 1081 } 1082 } 1083} 1084 1085template<class T> 1086void 1087AbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 1088{ 1089 srcEncoded = getFaultStatusCode(tc); 1090 if (srcEncoded == ArmFault::FaultSourceInvalid) { 1091 panic("Invalid fault source\n"); 1092 } 1093 ArmFault::setSyndrome(tc, syndrome_reg); 1094} 1095 1096template<class T> 1097uint8_t 1098AbortFault<T>::getFaultStatusCode(ThreadContext *tc) const 1099{ 1100 1101 panic_if(!this->faultUpdated, 1102 "Trying to use un-updated ArmFault internal variables\n"); 1103 1104 uint8_t fsc = 0; 1105 1106 if (!this->to64) { 1107 // AArch32 1108 assert(tranMethod != ArmFault::UnknownTran); 1109 if (tranMethod == ArmFault::LpaeTran) { 1110 fsc = ArmFault::longDescFaultSources[source]; 1111 } else { 1112 fsc = ArmFault::shortDescFaultSources[source]; 1113 } 1114 } else { 1115 // AArch64 1116 fsc = ArmFault::aarch64FaultSources[source]; 1117 } 1118 1119 return fsc; 1120} 1121 1122template<class T> 1123FSR 1124AbortFault<T>::getFsr(ThreadContext *tc) const 1125{ 1126 FSR fsr = 0; 1127 1128 auto fsc = getFaultStatusCode(tc); 1129 1130 // AArch32 1131 assert(tranMethod != ArmFault::UnknownTran); 1132 if (tranMethod == ArmFault::LpaeTran) { 1133 fsr.status = fsc; 1134 fsr.lpae = 1; 1135 } else { 1136 fsr.fsLow = bits(fsc, 3, 0); 1137 fsr.fsHigh = bits(fsc, 4); 1138 fsr.domain = static_cast<uint8_t>(domain); 1139 } 1140 1141 fsr.wnr = (write ? 1 : 0); 1142 fsr.ext = 0; 1143 1144 return fsr; 1145} 1146 1147template<class T> 1148bool 1149AbortFault<T>::abortDisable(ThreadContext *tc) 1150{ 1151 if (ArmSystem::haveSecurity(tc)) { 1152 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1153 return (!scr.ns || scr.aw); 1154 } 1155 return true; 1156} 1157 1158template<class T> 1159void 1160AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 1161{ 1162 switch (id) 1163 { 1164 case ArmFault::S1PTW: 1165 s1ptw = val; 1166 break; 1167 case ArmFault::OVA: 1168 OVAddr = val; 1169 break; 1170 1171 // Just ignore unknown ID's 1172 default: 1173 break; 1174 } 1175} 1176 1177template<class T> 1178uint32_t 1179AbortFault<T>::iss() const 1180{ 1181 uint32_t val; 1182 1183 val = srcEncoded & 0x3F; 1184 val |= write << 6; 1185 val |= s1ptw << 7; 1186 return (val); 1187} 1188 1189template<class T> 1190bool 1191AbortFault<T>::isMMUFault() const 1192{ 1193 // NOTE: Not relying on LL information being aligned to lowest bits here 1194 return 1195 (source == ArmFault::AlignmentFault) || 1196 ((source >= ArmFault::TranslationLL) && 1197 (source < ArmFault::TranslationLL + 4)) || 1198 ((source >= ArmFault::AccessFlagLL) && 1199 (source < ArmFault::AccessFlagLL + 4)) || 1200 ((source >= ArmFault::DomainLL) && 1201 (source < ArmFault::DomainLL + 4)) || 1202 ((source >= ArmFault::PermissionLL) && 1203 (source < ArmFault::PermissionLL + 4)); 1204} 1205 1206ExceptionClass 1207PrefetchAbort::ec(ThreadContext *tc) const 1208{ 1209 if (to64) { 1210 // AArch64 1211 if (toEL == fromEL) 1212 return EC_PREFETCH_ABORT_CURR_EL; 1213 else 1214 return EC_PREFETCH_ABORT_LOWER_EL; 1215 } else { 1216 // AArch32 1217 // Abort faults have different EC codes depending on whether 1218 // the fault originated within HYP mode, or not. So override 1219 // the method and add the extra adjustment of the EC value. 1220 1221 ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 1222 1223 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 1224 if (spsr.mode == MODE_HYP) { 1225 ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 1226 } 1227 return ec; 1228 } 1229} 1230 1231bool 1232PrefetchAbort::routeToMonitor(ThreadContext *tc) const 1233{ 1234 SCR scr = 0; 1235 if (from64) 1236 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1237 else 1238 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1239 1240 return scr.ea && !isMMUFault(); 1241} 1242 1243bool 1244PrefetchAbort::routeToHyp(ThreadContext *tc) const 1245{ 1246 bool toHyp; 1247 1248 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1249 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1250 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1251 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 1252 1253 // if in Hyp mode then stay in Hyp mode 1254 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 1255 // otherwise, check whether to take to Hyp mode through Hyp Trap vector 1256 toHyp |= (stage2 || 1257 ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 1258 ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 1259 ) && !inSecureState(tc); 1260 return toHyp; 1261} 1262 1263ExceptionClass 1264DataAbort::ec(ThreadContext *tc) const 1265{ 1266 if (to64) { 1267 // AArch64 1268 if (source == ArmFault::AsynchronousExternalAbort) { 1269 panic("Asynchronous External Abort should be handled with " 1270 "SystemErrors (SErrors)!"); 1271 } 1272 if (toEL == fromEL) 1273 return EC_DATA_ABORT_CURR_EL; 1274 else 1275 return EC_DATA_ABORT_LOWER_EL; 1276 } else { 1277 // AArch32 1278 // Abort faults have different EC codes depending on whether 1279 // the fault originated within HYP mode, or not. So override 1280 // the method and add the extra adjustment of the EC value. 1281 1282 ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 1283 1284 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 1285 if (spsr.mode == MODE_HYP) { 1286 ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 1287 } 1288 return ec; 1289 } 1290} 1291 1292bool 1293DataAbort::routeToMonitor(ThreadContext *tc) const 1294{ 1295 SCR scr = 0; 1296 if (from64) 1297 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1298 else 1299 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1300 1301 return scr.ea && !isMMUFault(); 1302} 1303 1304bool 1305DataAbort::routeToHyp(ThreadContext *tc) const 1306{ 1307 bool toHyp; 1308 1309 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1310 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1311 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1312 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 1313 1314 // if in Hyp mode then stay in Hyp mode 1315 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 1316 // otherwise, check whether to take to Hyp mode through Hyp Trap vector 1317 toHyp |= (stage2 || 1318 ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 1319 ((source == DebugEvent) && hdcr.tde) ) 1320 ) || 1321 ( (cpsr.mode == MODE_USER) && hcr.tge && 1322 ((source == AlignmentFault) || 1323 (source == SynchronousExternalAbort)) 1324 ) 1325 ) && !inSecureState(tc); 1326 return toHyp; 1327} 1328 1329uint32_t 1330DataAbort::iss() const 1331{ 1332 uint32_t val; 1333 1334 // Add on the data abort specific fields to the generic abort ISS value 1335 val = AbortFault<DataAbort>::iss(); 1336 // ISS is valid if not caused by a stage 1 page table walk, and when taken 1337 // to AArch64 only when directed to EL2 1338 if (!s1ptw && (!to64 || toEL == EL2)) { 1339 val |= isv << 24; 1340 if (isv) { 1341 val |= sas << 22; 1342 val |= sse << 21; 1343 val |= srt << 16; 1344 // AArch64 only. These assignments are safe on AArch32 as well 1345 // because these vars are initialized to false 1346 val |= sf << 15; 1347 val |= ar << 14; 1348 } 1349 } 1350 return (val); 1351} 1352 1353void 1354DataAbort::annotate(AnnotationIDs id, uint64_t val) 1355{ 1356 AbortFault<DataAbort>::annotate(id, val); 1357 switch (id) 1358 { 1359 case SAS: 1360 isv = true; 1361 sas = val; 1362 break; 1363 case SSE: 1364 isv = true; 1365 sse = val; 1366 break; 1367 case SRT: 1368 isv = true; 1369 srt = val; 1370 break; 1371 case SF: 1372 isv = true; 1373 sf = val; 1374 break; 1375 case AR: 1376 isv = true; 1377 ar = val; 1378 break; 1379 // Just ignore unknown ID's 1380 default: 1381 break; 1382 } 1383} 1384 1385void 1386VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1387{ 1388 AbortFault<VirtualDataAbort>::invoke(tc, inst); 1389 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1390 hcr.va = 0; 1391 tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 1392} 1393 1394bool 1395Interrupt::routeToMonitor(ThreadContext *tc) const 1396{ 1397 assert(ArmSystem::haveSecurity(tc)); 1398 SCR scr = 0; 1399 if (from64) 1400 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1401 else 1402 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1403 return scr.irq; 1404} 1405 1406bool 1407Interrupt::routeToHyp(ThreadContext *tc) const 1408{ 1409 bool toHyp; 1410 1411 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1412 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1413 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1414 // Determine whether IRQs are routed to Hyp mode. 1415 toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) || 1416 (cpsr.mode == MODE_HYP); 1417 return toHyp; 1418} 1419 1420bool 1421Interrupt::abortDisable(ThreadContext *tc) 1422{ 1423 if (ArmSystem::haveSecurity(tc)) { 1424 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1425 return (!scr.ns || scr.aw); 1426 } 1427 return true; 1428} 1429 1430VirtualInterrupt::VirtualInterrupt() 1431{} 1432 1433bool 1434FastInterrupt::routeToMonitor(ThreadContext *tc) const 1435{ 1436 assert(ArmSystem::haveSecurity(tc)); 1437 SCR scr = 0; 1438 if (from64) 1439 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1440 else 1441 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1442 return scr.fiq; 1443} 1444 1445bool 1446FastInterrupt::routeToHyp(ThreadContext *tc) const 1447{ 1448 bool toHyp; 1449 1450 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1451 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1452 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1453 // Determine whether IRQs are routed to Hyp mode. 1454 toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) || 1455 (cpsr.mode == MODE_HYP); 1456 return toHyp; 1457} 1458 1459bool 1460FastInterrupt::abortDisable(ThreadContext *tc) 1461{ 1462 if (ArmSystem::haveSecurity(tc)) { 1463 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1464 return (!scr.ns || scr.aw); 1465 } 1466 return true; 1467} 1468 1469bool 1470FastInterrupt::fiqDisable(ThreadContext *tc) 1471{ 1472 if (ArmSystem::haveVirtualization(tc)) { 1473 return true; 1474 } else if (ArmSystem::haveSecurity(tc)) { 1475 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1476 return (!scr.ns || scr.fw); 1477 } 1478 return true; 1479} 1480 1481VirtualFastInterrupt::VirtualFastInterrupt() 1482{} 1483 1484void 1485PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1486{ 1487 ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 1488 assert(from64); 1489 // Set the FAR 1490 tc->setMiscReg(getFaultAddrReg64(), faultPC); 1491} 1492 1493bool 1494PCAlignmentFault::routeToHyp(ThreadContext *tc) const 1495{ 1496 bool toHyp = false; 1497 1498 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1499 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 1500 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1501 1502 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 1503 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 1504 return toHyp; 1505} 1506 1507SPAlignmentFault::SPAlignmentFault() 1508{} 1509 1510SystemError::SystemError() 1511{} 1512 1513void 1514SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1515{ 1516 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 1517 ArmFault::invoke(tc, inst); 1518} 1519 1520bool 1521SystemError::routeToMonitor(ThreadContext *tc) const 1522{ 1523 assert(ArmSystem::haveSecurity(tc)); 1524 assert(from64); 1525 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1526 return scr.ea; 1527} 1528 1529bool 1530SystemError::routeToHyp(ThreadContext *tc) const 1531{ 1532 bool toHyp; 1533 assert(from64); 1534 1535 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1536 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1537 1538 toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 1539 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 1540 return toHyp; 1541} 1542 1543 1544SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) 1545 : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) 1546{} 1547 1548bool 1549SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const 1550{ 1551 const bool have_el2 = ArmSystem::haveVirtualization(tc); 1552 1553 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 1554 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); 1555 1556 return have_el2 && !inSecureState(tc) && fromEL <= EL1 && 1557 (hcr.tge || mdcr.tde); 1558} 1559 1560ExceptionClass 1561SoftwareBreakpoint::ec(ThreadContext *tc) const 1562{ 1563 return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec; 1564} 1565 1566void 1567ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 1568 DPRINTF(Faults, "Invoking ArmSev Fault\n"); 1569 if (!FullSystem) 1570 return; 1571 1572 // Set sev_mailbox to 1, clear the pending interrupt from remote 1573 // SEV execution and let pipeline continue as pcState is still 1574 // valid. 1575 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 1576 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 1577} 1578 1579// Instantiate all the templates to make the linker happy 1580template class ArmFaultVals<Reset>; 1581template class ArmFaultVals<UndefinedInstruction>; 1582template class ArmFaultVals<SupervisorCall>; 1583template class ArmFaultVals<SecureMonitorCall>; 1584template class ArmFaultVals<HypervisorCall>; 1585template class ArmFaultVals<PrefetchAbort>; 1586template class ArmFaultVals<DataAbort>; 1587template class ArmFaultVals<VirtualDataAbort>; 1588template class ArmFaultVals<HypervisorTrap>; 1589template class ArmFaultVals<Interrupt>; 1590template class ArmFaultVals<VirtualInterrupt>; 1591template class ArmFaultVals<FastInterrupt>; 1592template class ArmFaultVals<VirtualFastInterrupt>; 1593template class ArmFaultVals<SupervisorTrap>; 1594template class ArmFaultVals<SecureMonitorTrap>; 1595template class ArmFaultVals<PCAlignmentFault>; 1596template class ArmFaultVals<SPAlignmentFault>; 1597template class ArmFaultVals<SystemError>; 1598template class ArmFaultVals<SoftwareBreakpoint>; 1599template class ArmFaultVals<ArmSev>; 1600template class AbortFault<PrefetchAbort>; 1601template class AbortFault<DataAbort>; 1602template class AbortFault<VirtualDataAbort>; 1603 1604 1605IllegalInstSetStateFault::IllegalInstSetStateFault() 1606{} 1607 1608 1609} // namespace ArmISA 1610