vtophys.cc revision 2665
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Ali Saidi 312SN/A */ 322SN/A 332SN/A#include <string> 342SN/A 352521SN/A#include "arch/alpha/ev5.hh" 361110SN/A#include "arch/alpha/vtophys.hh" 372521SN/A#include "base/chunk_generator.hh" 381110SN/A#include "base/trace.hh" 3956SN/A#include "cpu/exec_context.hh" 402521SN/A#include "mem/vport.hh" 412SN/A 422SN/Ausing namespace std; 432107SN/Ausing namespace AlphaISA; 442SN/A 451111SN/AAlphaISA::PageTableEntry 462521SN/AAlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr) 472SN/A{ 481111SN/A Addr level1_pte = ptbr + vaddr.level1(); 492521SN/A AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte); 501111SN/A if (!level1.valid()) { 512SN/A DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); 522SN/A return 0; 532SN/A } 542SN/A 551111SN/A Addr level2_pte = level1.paddr() + vaddr.level2(); 562521SN/A AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte); 571111SN/A if (!level2.valid()) { 582SN/A DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); 592SN/A return 0; 602SN/A } 612SN/A 621111SN/A Addr level3_pte = level2.paddr() + vaddr.level3(); 632521SN/A AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte); 641111SN/A if (!level3.valid()) { 651111SN/A DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); 661111SN/A return 0; 671111SN/A } 681111SN/A return level3; 692SN/A} 702SN/A 712SN/AAddr 722521SN/AAlphaISA::vtophys(Addr vaddr) 732SN/A{ 742SN/A Addr paddr = 0; 751111SN/A if (AlphaISA::IsUSeg(vaddr)) 762SN/A DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); 771111SN/A else if (AlphaISA::IsK0Seg(vaddr)) 781111SN/A paddr = AlphaISA::K0Seg2Phys(vaddr); 792SN/A else 802SN/A panic("vtophys: ptbr is not set on virtual lookup"); 812SN/A 822SN/A DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 832SN/A 842SN/A return paddr; 852SN/A} 862SN/A 872SN/AAddr 882521SN/AAlphaISA::vtophys(ExecContext *xc, Addr addr) 892SN/A{ 901111SN/A AlphaISA::VAddr vaddr = addr; 912159SN/A Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20); 922SN/A Addr paddr = 0; 93924SN/A //@todo Andrew couldn't remember why he commented some of this code 94924SN/A //so I put it back in. Perhaps something to do with gdb debugging? 951147SN/A if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) { 96924SN/A paddr = vaddr & ~ULL(1); 97924SN/A } else { 981111SN/A if (AlphaISA::IsK0Seg(vaddr)) { 991111SN/A paddr = AlphaISA::K0Seg2Phys(vaddr); 100973SN/A } else if (!ptbr) { 101973SN/A paddr = vaddr; 102547SN/A } else { 1031111SN/A AlphaISA::PageTableEntry pte = 1042521SN/A kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr); 1051111SN/A if (pte.valid()) 1061111SN/A paddr = pte.paddr() | vaddr.offset(); 107547SN/A } 108924SN/A } 109924SN/A 1102SN/A 1112SN/A DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 1122SN/A 1132SN/A return paddr; 1142SN/A} 1152SN/A 1162521SN/A 1172521SN/Avoid 1182521SN/AAlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen) 119547SN/A{ 1202521SN/A uint8_t *dst = (uint8_t *)dest; 1212521SN/A VirtualPort *vp = xc->getVirtPort(xc); 122547SN/A 1232521SN/A vp->readBlob(src, dst, cplen); 1242521SN/A 1252521SN/A xc->delVirtPort(vp); 1262521SN/A 1272SN/A} 12873SN/A 12973SN/Avoid 1302521SN/AAlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen) 13173SN/A{ 1322521SN/A uint8_t *src = (uint8_t *)source; 1332521SN/A VirtualPort *vp = xc->getVirtPort(xc); 13473SN/A 1352521SN/A vp->writeBlob(dest, src, cplen); 13673SN/A 1372521SN/A xc->delVirtPort(vp); 13873SN/A} 13973SN/A 14073SN/Avoid 1412521SN/AAlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen) 142953SN/A{ 1432521SN/A int len = 0; 1442521SN/A VirtualPort *vp = xc->getVirtPort(xc); 145953SN/A 1462521SN/A do { 1472521SN/A vp->readBlob(vaddr++, (uint8_t*)dst++, 1); 1482521SN/A len++; 1492521SN/A } while (len < maxlen && dst[len] != 0 ); 150953SN/A 1512521SN/A xc->delVirtPort(vp); 1522521SN/A dst[len] = 0; 153953SN/A} 154953SN/A 155953SN/Avoid 1562521SN/AAlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr) 15773SN/A{ 1582521SN/A VirtualPort *vp = xc->getVirtPort(xc); 1592521SN/A for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); 1602521SN/A gen.next()) 1612521SN/A { 1622521SN/A vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); 1632521SN/A src += gen.size(); 16473SN/A } 1652521SN/A xc->delVirtPort(vp); 16673SN/A} 167